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Change subject: src/arch/ppc64/*: pass FDT address to payload
......................................................................
src/arch/ppc64/*: pass FDT address to payload
It's available in %r3 in bootblock and needs to be passed first to
romstage, then to ramstage, where it's put into CMBEM to be read on
starting payload.
Change-Id: I0911f4b534c6f8cacfa057a5bad7576fec711637
Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com>
---
M src/arch/ppc64/boot.c
M src/arch/ppc64/bootblock_crt0.S
M src/commonlib/include/commonlib/cbmem_id.h
M src/mainboard/emulation/qemu-power9/memlayout.ld
4 files changed, 45 insertions(+), 0 deletions(-)
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Change subject: src/mainboard/emulation/qemu-power9: require hb-mode=on
......................................................................
src/mainboard/emulation/qemu-power9: require hb-mode=on
"hb-mode" is a -machine flag for QEMU. "hb" stands for Hostboot, which
is OpenPower firmware created by IBM.
QEMU for PPC64 can run initial program in two different modes:
* hb-mode=off with load address 0x00000000
* hb-mode=on with load address 0x08000000
Real hardware always loads firmware at 0x08000000 and coreboot shouldn't
require a special build to be run on QEMU.
Memory layout is updated to reflect change of load address.
Change-Id: I1bdc97a095bd46fccc862985b3bd24f4fa5bc054
Signed-off-by: Yaroslav Kurlaev <yaroslav.kurlaev(a)3mdeb.com>
Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com>
---
M src/arch/ppc64/rom_media.c
M src/arch/ppc64/stages.c
M src/mainboard/emulation/qemu-power9/memlayout.ld
3 files changed, 37 insertions(+), 11 deletions(-)
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Change subject: src/mainboard/emulation/qemu-power9: add RAM detection
......................................................................
src/mainboard/emulation/qemu-power9: add RAM detection
Change-Id: Ie333294c7a311f6d47bdfbd1fc3cec0128cf63e7
Signed-off-by: Yaroslav Kurlaev <yaroslav.kurlaev(a)3mdeb.com>
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M src/mainboard/emulation/qemu-power9/cbmem.c
M src/mainboard/emulation/qemu-power9/mainboard.c
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M src/mainboard/emulation/qemu-power9/romstage.c
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Change subject: src/mainboard/emulation/qemu-power9/*: add QEMU POWER9 mainboard
......................................................................
src/mainboard/emulation/qemu-power9/*: add QEMU POWER9 mainboard
Add initial implementation for booting on QEMU POWER9 emulation
Change-Id: I079c5b9ad564024dd13296ef75c263bdc40c9d39
Signed-off-by: Yaroslav Kurlaev <yaroslav.kurlaev(a)3mdeb.com>
Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com>
---
A Documentation/mainboard/emulation/qemu-power9.md
A configs/config.emulation_qemu_power9
A src/mainboard/emulation/qemu-power9/Kconfig
A src/mainboard/emulation/qemu-power9/Kconfig.name
A src/mainboard/emulation/qemu-power9/Makefile.inc
A src/mainboard/emulation/qemu-power9/board_info.txt
A src/mainboard/emulation/qemu-power9/cbmem.c
A src/mainboard/emulation/qemu-power9/devicetree.cb
A src/mainboard/emulation/qemu-power9/mainboard.c
A src/mainboard/emulation/qemu-power9/memlayout.ld
A src/mainboard/emulation/qemu-power9/romstage.c
11 files changed, 142 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/57079/12
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Change subject: src/cpu/power9: add file structure for power9, implement SCOM access
......................................................................
src/cpu/power9: add file structure for power9, implement SCOM access
Change-Id: Ib555ce51294c94b22d9a7c0db84d38d7928f7015
Signed-off-by: Krystian Hebel <krystian.hebel(a)3mdeb.com>
---
M src/arch/ppc64/include/arch/byteorder.h
M src/arch/ppc64/include/arch/io.h
M src/cpu/Makefile.inc
A src/cpu/power9/Kconfig
A src/cpu/power9/Makefile.inc
A src/cpu/power9/power9.c
A src/cpu/power9/scom.c
A src/include/cpu/power/scom.h
A src/include/cpu/power/spr.h
9 files changed, 414 insertions(+), 0 deletions(-)
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Change subject: src/security/vboot: Set up secure counter space in TPM NVRAM
......................................................................
Patch Set 3:
(3 comments)
File src/security/vboot/antirollback.h:
https://review.coreboot.org/c/coreboot/+/59476/comment/2f7f66bc_fc224c92
PS2, Line 30: #define HASH_NV_SIZE VB2_SHA256_DIGEST_SIZE
> I would insert them here so the spaces are listed in ascending order. […]
Done
https://review.coreboot.org/c/coreboot/+/59476/comment/c7e28066_2fe074db
PS2, Line 42: #define SECURE_COUNTER4_NV_INDEX 0x1012
> right, but the indexes of the counters are cr50 specific. […]
I have made references to use-case here(Widevine) so that it is more clear.
File src/security/vboot/secure_counter.h:
https://review.coreboot.org/c/coreboot/+/59476/comment/de8222c9_930790b3
PS1, Line 14: SECURE_COUNTER4_NV_INDEX, /* 0x1012 */
> No, I think the counters should be specifically named after their purpose. […]
Ack. Rephrased the kconfig item, macros etc. to make it clear that this is specific to Widevine Counters.
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Change subject: src/security/vboot: Set up secure counter space in TPM NVRAM
......................................................................
Patch Set 3:
(1 comment)
File src/security/vboot/antirollback.h:
https://review.coreboot.org/c/coreboot/+/59476/comment/19ec8352_736ee102
PS2, Line 42: #define SECURE_COUNTER4_NV_INDEX 0x1012
> I would maybe go a bit further and just define this as SECURE_COUNTER_NV_INDEX(n) (0x... […]
right, but the indexes of the counters are cr50 specific. I think there is a go link that tracks them, but I can't seem to find it.
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I'd like you to reexamine a change. Please visit
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Change subject: soc/amd/cezanne: Enable secure counters
......................................................................
soc/amd/cezanne: Enable secure counters
Guybrush uses secure counters to protect against High Definition (HD)
protected content rollback. These secure counters are hosted in TPM
NVRAM. Enable secure counters so that they are defined in PSP verstage.
BUG=b:205261728
TEST=Build and boot to OS in Guybrush. Ensure that the secure counters
are defined successfully in TPM NVRAM.
Change-Id: I6818c6f7905aa2eb815059e23c4f79437593f8ca
Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com>
---
M src/soc/amd/cezanne/Kconfig
1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/59477/3
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Change subject: src/security/vboot: Set up secure counter space in TPM NVRAM
......................................................................
src/security/vboot: Set up secure counter space in TPM NVRAM
High Definition (HD) protected content playback requires secure counters
that are updated at regular interval while the protected content is
playing. To support similar use-cases, define space for secure counters
in TPM NVRAM and initialize them. These counters are defined once during
the factory initialization stage. Also add a config item to enable these
secure counters only on the mainboard where they are required/used.
BUG=b:205261728
TEST=Build and boot to OS in guybrush. Ensure that the secure counters
are defined successfully in TPM NVRAM space.
tlcl_define_space: response is 0
tlcl_define_space: response is 0
tlcl_define_space: response is 0
tlcl_define_space: response is 0
On reboot if forced to redefine the space, it is identified as already
defined.
tlcl_define_space: response is 14c
define_space():219: define_space: Secure Counter space already exists
tlcl_define_space: response is 14c
define_space():219: define_space: Secure Counter space already exists
tlcl_define_space: response is 14c
define_space():219: define_space: Secure Counter space already exists
tlcl_define_space: response is 14c
define_space():219: define_space: Secure Counter space already exists
Change-Id: I915fbdada60e242d911b748ad5dc28028de9b657
Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com>
---
M src/security/vboot/Kconfig
M src/security/vboot/antirollback.h
M src/security/vboot/secdata_tpm.c
3 files changed, 42 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/59476/3
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Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59320 )
Change subject: lib: Add a mutex
......................................................................
Patch Set 6:
(1 comment)
File src/include/mutex.h:
https://review.coreboot.org/c/coreboot/+/59320/comment/bb20e19f_16b1f754
PS2, Line 11: void mutex_unlock(struct mutex *mutex);
> Ah you aren't using LTO? Is that just an ARM thing? […]
Done
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