coreboot-gerrit November 2021

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: lib: Add a mutex
by Raul Rangel (Code Review) 19 Nov '21

19 Nov '21

Attention is currently required from: Julius Werner, Rob Barnes, Kyösti Mälkki, Karthik Ramasubramanian. Hello build bot (Jenkins), Julius Werner, Rob Barnes, Kyösti Mälkki, Karthik Ramasubramanian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59320 to look at the new patch set (#6). Change subject: lib: Add a mutex ...................................................................... lib: Add a mutex We currently have two synchronization primatives, spinlock and thread_mutex. spinlock is meant to block multiple CPUs from entering a critical section. thread_mutex is meant to block multiple coop-threads from entering a critical section. It is not AP aware at all. This CL introduces a mutex that can handle both concepts. The implementation is using the GCC/LLVM atomic builtin functions. The generated code uses the xchg instruction vs spinlock which uses (lock) decb. 8: b0 01 mov $0x1,%al a: 86 03 xchg %al,(%ebx) c: 84 c0 test %al,%al BUG=b:179699789 TEST=Boot guybrush to OS Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I41e02a54a17b1f6513b36a0274e43fc715472d78 --- A src/include/mutex.h M src/lib/Makefile.inc A src/lib/mutex.c 3 files changed, 88 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/59320/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/59320 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I41e02a54a17b1f6513b36a0274e43fc715472d78 Gerrit-Change-Number: 59320 Gerrit-PatchSet: 6 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: lib: Add a mutex
by Raul Rangel (Code Review) 19 Nov '21

19 Nov '21

Attention is currently required from: Julius Werner, Rob Barnes, Kyösti Mälkki, Karthik Ramasubramanian. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59320 ) Change subject: lib: Add a mutex ...................................................................... Patch Set 5: (1 comment) File src/include/mutex.h: https://review.coreboot.org/c/coreboot/+/59320/comment/a0c3df45_83c0773f PS2, Line 11: void mutex_unlock(struct mutex *mutex); > > A no-op function will get garbage collected anyway. […] Ah you aren't using LTO? Is that just an ARM thing? Ah, you want me to expose the internals. I guess I'l do that :( -- To view, visit https://review.coreboot.org/c/coreboot/+/59320 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I41e02a54a17b1f6513b36a0274e43fc715472d78 Gerrit-Change-Number: 59320 Gerrit-PatchSet: 5 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Sat, 20 Nov 2021 00:01:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: cpu/intel/hyperthreading: Add missing header <arch/cpu.h>
by Felix Held (Code Review) 19 Nov '21

19 Nov '21

Attention is currently required from: Raul Rangel, Patrick Rudolph. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59356 ) Change subject: cpu/intel/hyperthreading: Add missing header <arch/cpu.h> ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59356 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idc3daa64562c4a4d57b678f13726509b480ba050 Gerrit-Change-Number: 59356 Gerrit-PatchSet: 4 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Sat, 20 Nov 2021 00:00:22 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: acpi,Makefile: Add preload_acpi_dsdt
by Raul Rangel (Code Review) 19 Nov '21

19 Nov '21

Attention is currently required from: Lance Zhao, Martin Roth, Tim Wawrzynczak, Julius Werner. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59504 ) Change subject: acpi,Makefile: Add preload_acpi_dsdt ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: > I kind of agree with Tim's sentiment, having each platform kick all of these off manually gets prett […] The order right now has been hand crafted and analyzed extensively. The biggest problem we run into is having a SPI DMA transaction in flight while something else tries to access the SPI rom. i.e., if we have a SPI DMA transaction in flight while ELOG or APOB is writing, then they will be blocked unnecessarily and thus negate any benefits. I moved the APOB update into romstage to make the sequencing easier. Also by sequencing the preloads the way I did, I can make sure we don't exhaust the cbfs_cache. Some platforms might need to load additional files between two "generic" preloads. So I'm still a little hesitant to make the whole thing generic. I think Tim's point was more having these functions in the first place. imo, they are better then copy/pasting the code that derives the cbfs filename. -- To view, visit https://review.coreboot.org/c/coreboot/+/59504 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibf69ecb947811a2eec861018e3ba5f858155f1c3 Gerrit-Change-Number: 59504 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Lance Zhao Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Fri, 19 Nov 2021 23:59:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: lib: Add a mutex
by Julius Werner (Code Review) 19 Nov '21

19 Nov '21

Attention is currently required from: Raul Rangel, Rob Barnes, Kyösti Mälkki, Karthik Ramasubramanian. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59320 ) Change subject: lib: Add a mutex ...................................................................... Patch Set 5: (1 comment) File src/include/mutex.h: https://review.coreboot.org/c/coreboot/+/59320/comment/1688c9bd_8232c308 PS2, Line 11: void mutex_unlock(struct mutex *mutex); > A no-op function will get garbage collected anyway. Uhh... not if it's not inline, no. Unless I'm really confused about something here. (Or you're using LTO which we aren't, yet.) I'm not really sure I understand the Makefile problem. If you just move the mutex_lock() you have right now as a static inline into the header, split your mutex_unlock() into a mutex_unlock_smp() and mutex_unlock_coop(), and then write a static inline mutex_unlock() stub in the header that calls either of those, doesn't that work? (You can compile the .c file unconditionally, that's fine, it'll just not be used if neither SMP nor coop are enabled.) -- To view, visit https://review.coreboot.org/c/coreboot/+/59320 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I41e02a54a17b1f6513b36a0274e43fc715472d78 Gerrit-Change-Number: 59320 Gerrit-PatchSet: 5 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Fri, 19 Nov 2021 23:36:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: acpi,Makefile: Add preload_acpi_dsdt
by Julius Werner (Code Review) 19 Nov '21

19 Nov '21

Attention is currently required from: Lance Zhao, Raul Rangel, Martin Roth, Tim Wawrzynczak. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59504 ) Change subject: acpi,Makefile: Add preload_acpi_dsdt ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: > This is the last one required for cezanne. I kind of agree with Tim's sentiment, having each platform kick all of these off manually gets pretty clunky. We kinda had a bit of this discussion in https://review.coreboot.org/c/coreboot/+/56051/8..18/src/lib/Kconfig#b102 already. I think ideally we'd just have one central point in the generic code of each stage (e.g. early in hardwaremain.c for ramstage) where it automatically kicks off all preloads, and the platform shouldn't have to worry about it anymore (other than enabling the right Kconfigs). What are your remaining concerns with that? -- To view, visit https://review.coreboot.org/c/coreboot/+/59504 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibf69ecb947811a2eec861018e3ba5f858155f1c3 Gerrit-Change-Number: 59504 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Lance Zhao Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Fri, 19 Nov 2021 23:29:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: src/security/vboot: Set up secure counter space in TPM NVRAM
by Julius Werner (Code Review) 19 Nov '21

19 Nov '21

Attention is currently required from: Andrey Pronin, Raul Rangel, Paul Menzel, Yu-Ping Wu, Karthik Ramasubramanian. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59476 ) Change subject: src/security/vboot: Set up secure counter space in TPM NVRAM ...................................................................... Patch Set 2: (4 comments) File src/security/vboot/antirollback.h: https://review.coreboot.org/c/coreboot/+/59476/comment/ba541d38_744b0acf PS2, Line 30: #define HASH_NV_SIZE VB2_SHA256_DIGEST_SIZE I would insert them here so the spaces are listed in ascending order. (In fact, I don't know why we picked such different indices for the ZTE spaces... Andrey, do you remember? Is there any significance to those indices or can you just pick whatever number? Maybe we should put these secure counters aside in their own area as well, so that if we find out that we need more in the future it's easy to add some (and the directly following indices won't be taken up by other unrelated spaces that get added later yet). https://review.coreboot.org/c/coreboot/+/59476/comment/e3682459_4113ad0d PS2, Line 39: SECURE_COUNTER1_NV_INDEX > If you go this route, I would say put a comment saying that they are CR50 specific. Well, they aren't really (I think?), counters are part of the TPM 2.0 standard. https://review.coreboot.org/c/coreboot/+/59476/comment/560ba2d1_5e1dc35f PS2, Line 42: #define SECURE_COUNTER4_NV_INDEX 0x1012 I would maybe go a bit further and just define this as SECURE_COUNTER_NV_INDEX(n) (0x... + n), and a SECURE_COUNTER_NUM 4. That makes your for-loop cleaner to write. File src/security/vboot/secure_counter.h: https://review.coreboot.org/c/coreboot/+/59476/comment/7354f847_9ad35db7 PS1, Line 14: SECURE_COUNTER4_NV_INDEX, /* 0x1012 */ > Sorry for prematurely saying done. I moved it to antirollback.h. […] No, I think the counters should be specifically named after their purpose. "counter" is just a general TPM concept (and they're all "secure" in the same way), we can create as many as we want for those, and in fact we already have some (for ZTE and soon for CB:59097). But I don't think you want coreboot to just create a range of generic counters that the OS can then decide what to do with, so that one platform uses the same indices for Widevine and another for something completely different... because then what happens if the platform that decided to use these same counters for something else eventually decides that it wants to start doing the Widevine stuff as well (and reuse the same userland code from those other platforms that originally did it)? Then you have a mess on your hands. I think the right way to organize this is that here, in this header, we sort of have a unique registry for TPM space indices where every purpose that any OS running on top of coreboot could ever want to use a TPM space for is assigned its own unique index, and we make sure there are no overlaps. The index space is big enough so we shouldn't run out (and since the extra code is all guarded by compile time flags it's not really a "bloat" problem either). Each of those indices should only be used for one specific purpose (according to one specific "API"), and that way we won't get nasty clashes when platforms later try to mix and match some things together that previous platforms did with the TPM. -- To view, visit https://review.coreboot.org/c/coreboot/+/59476 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I915fbdada60e242d911b748ad5dc28028de9b657 Gerrit-Change-Number: 59476 Gerrit-PatchSet: 2 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Andrey Pronin <apronin(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Andrey Pronin <apronin(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Andrey Pronin <apronin(a)google.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Andrey Pronin <apronin(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Fri, 19 Nov 2021 23:20:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/felwinter: Add ALC5682I-VS codec support
by Tim Wawrzynczak (Code Review) 19 Nov '21

19 Nov '21

Attention is currently required from: EricR Lai. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59412 ) Change subject: mb/google/brya/var/felwinter: Add ALC5682I-VS codec support ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59412 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I34d736fe1c39860443dac07435a21ccd0ee2f21c Gerrit-Change-Number: 59412 Gerrit-PatchSet: 1 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Fri, 19 Nov 2021 23:18:01 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/variants/primus: add fw_config_probe for ALC5682I-VS
by Tim Wawrzynczak (Code Review) 19 Nov '21

19 Nov '21

Attention is currently required from: Malik Hsu. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59367 ) Change subject: mb/google/brya/variants/primus: add fw_config_probe for ALC5682I-VS ...................................................................... Patch Set 6: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59367 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0d5b95e89154b2cb6b371f24cc1b151c23ff642f Gerrit-Change-Number: 59367 Gerrit-PatchSet: 6 Gerrit-Owner: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-Attention: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-Comment-Date: Fri, 19 Nov 2021 23:15:54 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mainboard/google/brya: Enable dev screen in bios-stage for Brask
by Tim Wawrzynczak (Code Review) 19 Nov '21

19 Nov '21

Attention is currently required from: Adam Liu. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59414 ) Change subject: mainboard/google/brya: Enable dev screen in bios-stage for Brask ...................................................................... Patch Set 7: Code-Review+2 (1 comment) File src/mainboard/google/brya/Kconfig: https://review.coreboot.org/c/coreboot/+/59414/comment/049ba820_9e348dc8 PS3, Line 10: INTEL_GMA_HAVE_VBT > The config is unnecessary. Removed it. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/59414 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5f34be030a6d819a0e93a2d479c4ff41bb14cfe2 Gerrit-Change-Number: 59414 Gerrit-PatchSet: 7 Gerrit-Owner: Adam Liu <adam.liu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Adam Liu <adam.liu(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Fri, 19 Nov 2021 23:15:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Adam Liu <adam.liu(a)quanta.corp-partner.google.com> Gerrit-MessageType: comment

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coreboot-gerrit November 2021