Attention is currently required from: Jason Glenesk, Marshall Dawson, Felix Held.
Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59503 )
Change subject: soc/amd/cezanne: Move payload preload after ELOG init
......................................................................
soc/amd/cezanne: Move payload preload after ELOG init
We can only load so much while FSP-S is executing. If we don't finish
everything in time, the preloads will start competing with the ELOG init
that happens right after FSP-S. Since the payload isn't needed until the
end, we can move the preload call later in the boot flow.
This CL doesn't change any timings, instead it makes it so we can preload
the vga oprom while FSP-S loads.
BUG=b:179699789
TEST=Boot guybrush and verify timings didn't change.
Signed-off-by: Raul E Rangel <rrangel(a)chromium.org>
Change-Id: Ib9baf43fab70f6a11d8a240e1dd94af70271c568
---
M src/soc/amd/cezanne/fsp_s_params.c
M src/soc/amd/cezanne/preload.c
2 files changed, 13 insertions(+), 13 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/59503/1
diff --git a/src/soc/amd/cezanne/fsp_s_params.c b/src/soc/amd/cezanne/fsp_s_params.c
index 64cc722..64af58a 100644
--- a/src/soc/amd/cezanne/fsp_s_params.c
+++ b/src/soc/amd/cezanne/fsp_s_params.c
@@ -1,9 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-#include <acpi/acpi.h>
#include <device/pci.h>
#include <fsp/api.h>
-#include <program_loading.h>
#include <thread.h>
static void fsp_assign_vbios_upds(FSP_S_CONFIG *scfg)
@@ -23,15 +21,4 @@
scfg->void_function = (uintptr_t)fsp_s_yield;
fsp_assign_vbios_upds(scfg);
-
- /*
- * Since FSP-S takes a while to execute and performs no SPI operations, we can preload
- * while FSP-S executes.
- *
- * At this point FSP-S has been loaded into RAM. This means the cbfs_cache buffer used
- * for the FSP-S preload has been freed, so we don't have to worry about exhausting the
- * cbfs_cache.
- */
- if (!acpi_is_wakeup_s3())
- payload_preload();
}
diff --git a/src/soc/amd/cezanne/preload.c b/src/soc/amd/cezanne/preload.c
index d8b0891..e713912 100644
--- a/src/soc/amd/cezanne/preload.c
+++ b/src/soc/amd/cezanne/preload.c
@@ -1,7 +1,9 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#include <acpi/acpi.h>
#include <bootstate.h>
#include <fsp/api.h>
+#include <program_loading.h>
static void start_fsps_preload(void *unused)
{
@@ -9,3 +11,14 @@
}
BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, start_fsps_preload, NULL);
+
+/*
+ * After FSP-S completes, we perform ELOG initialization. We don't want any preloads competing
+ * with ELOG init, so we trigger the additional preloads afterwards.
+ */
+static void start_post_elog_preloads(void *unused)
+{
+ if (!acpi_is_wakeup_s3())
+ payload_preload();
+}
+BOOT_STATE_INIT_ENTRY(BS_DEV_INIT_CHIPS, BS_ON_EXIT, start_post_elog_preloads, NULL);
--
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Gerrit-Change-Id: Ib9baf43fab70f6a11d8a240e1dd94af70271c568
Gerrit-Change-Number: 59503
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Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org>
Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de>
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Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59502 )
Change subject: soc/amd/cezanne/romstage: Start loading APOB asynchronously
......................................................................
soc/amd/cezanne/romstage: Start loading APOB asynchronously
This was previously happening in ramstage. Now that threading is
functional in romstage, we can perform APOB preloading.
BUG=b:179699789
TEST=Boot guybrush to OS and verify APOB was loaded before FSP-M
completed.
Signed-off-by: Raul E Rangel <rrangel(a)chromium.org>
Change-Id: Ifb993debaf67027d4cd57920bcfb78fb05b9e68b
---
M src/soc/amd/cezanne/romstage.c
1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/59502/1
diff --git a/src/soc/amd/cezanne/romstage.c b/src/soc/amd/cezanne/romstage.c
index 8015c7a..db79f65 100644
--- a/src/soc/amd/cezanne/romstage.c
+++ b/src/soc/amd/cezanne/romstage.c
@@ -25,6 +25,7 @@
fill_chipset_state();
preload_fspm();
+ start_apob_cache_read();
fsp_memory_init(acpi_is_wakeup_s3());
soc_update_apob_cache();
--
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Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59500 )
Change subject: Revert "soc/amd/cezanne: Start loading APOB asynchronously"
......................................................................
Revert "soc/amd/cezanne: Start loading APOB asynchronously"
This reverts commit 61f44127f0c06688343fdfa3f518a58b4efe170c.
We now support coop-threads in romstage. This means we can use the SPI
DMA controller to preload the APOB while FSP-M executes. This will give
us more time to preload things in ramstage while FSP-S is executing.
BUG=b:179699789
TEST=build guybrush
Signed-off-by: Raul E Rangel <rrangel(a)chromium.org>
Change-Id: I8bd19ab1b202322ea6b185a660517d03c700d436
---
M src/soc/amd/cezanne/fsp_s_params.c
1 file changed, 0 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/59500/1
diff --git a/src/soc/amd/cezanne/fsp_s_params.c b/src/soc/amd/cezanne/fsp_s_params.c
index 0aa3c96..64cc722 100644
--- a/src/soc/amd/cezanne/fsp_s_params.c
+++ b/src/soc/amd/cezanne/fsp_s_params.c
@@ -1,7 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <acpi/acpi.h>
-#include <amdblocks/apob_cache.h>
#include <device/pci.h>
#include <fsp/api.h>
#include <program_loading.h>
@@ -33,7 +32,6 @@
* for the FSP-S preload has been freed, so we don't have to worry about exhausting the
* cbfs_cache.
*/
- start_apob_cache_read();
if (!acpi_is_wakeup_s3())
payload_preload();
}
--
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Hello build bot (Jenkins), Jason Glenesk, Marshall Dawson, Rob Barnes, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/58963
to look at the new patch set (#3).
Change subject: src/cpu,soc/amd/common/block/cpu: Add preload_microcode
......................................................................
src/cpu,soc/amd/common/block/cpu: Add preload_microcode
This will enable preloading the microcode. By preloading the
file, into cbfs_cache we reduce boot time.
BUG=b:179699789
TEST=Boot guybrush with CL chain and see microcode preloading and a
reduction of 1 ms.
| 112 - started reading uCode | 1.041 | 1.204 Δ( 0.16, 0.01%) |
| 113 - finished reading uCode | 1.365 | 0.011 Δ( -1.35, -0.10%) |
Signed-off-by: Raul E Rangel <rrangel(a)chromium.org>
Change-Id: If0c634c692c97769e71acd1175fc464dc592c356
---
M src/cpu/Makefile.inc
M src/include/cpu/amd/microcode.h
M src/soc/amd/common/block/cpu/update_microcode.c
3 files changed, 20 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/58963/3
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I'd like you to reexamine a change. Please visit
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Change subject: soc/amd/cezanne: Start preloading VGA_BIOS_FILE
......................................................................
soc/amd/cezanne: Start preloading VGA_BIOS_FILE
This CL enables support for CBFS_PRELOAD and starts preloading the
VGA_BIOS_FILE. The CBFS_SIZE was chosen because I will preload ramstage
in follow up CLs and wanted it large enough to hold it.
BUG=b:179699789
TEST=Boot guybrush to OS and see 4 ms reduction in boot time.
| 40 - device configuration | 2.596 | 2.598 Δ( 0.00, 0.00%) |
| 65 - Option ROM initialization | 10.576 | 10.609 Δ( 0.03, 0.00%) |
| 66 - Option ROM copy done | 4.683 | 0.02 Δ( -4.66, -0.33%) |
Signed-off-by: Raul E Rangel <rrangel(a)chromium.org>
Change-Id: Idc96299ee0186470df0ff113ecacb604a877f6ad
---
M src/soc/amd/cezanne/fsp_s_params.c
1 file changed, 11 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/56582/8
--
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