coreboot-gerrit November 2021

coreboot-gerrit@coreboot.org

1 participants
6394 discussions

Change in coreboot[master]: soc/amd/cezanne/romstage: Call preload_ramstage
by Raul Rangel (Code Review) 19 Nov '21

19 Nov '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Karthik Ramasubramanian, Felix Held. Hello build bot (Jenkins), Jason Glenesk, Marshall Dawson, Rob Barnes, Karthik Ramasubramanian, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/58983 to look at the new patch set (#4). Change subject: soc/amd/cezanne/romstage: Call preload_ramstage ...................................................................... soc/amd/cezanne/romstage: Call preload_ramstage This will use the SPI DMA controller to preload ramstage while FSP-M executes. BUG=b:179699789 TEST=Boot nipperkin to OS and verify ramstage is loaded before FSP-M completes. Timestamp - before RAM initialization: 648377 bootmode is set to: 0 FW_CONFIG value from CBI is 0x273 Preloading ramstage CBFS DEBUG: cbfs_preload(name='fallback/ramstage') CBFS: Found 'fallback/ramstage' @0x156480 size 0x1de64 in mcache @0x02016900 spi_dma_readat_dma: start: dest: 0x02200080, source: 0x468500, size: 122468 Timestamp - calling FspMemoryInit: 650514 <-- FSP-M starting spi_dma_readat_dma: end: dest: 0x0209a500, source: 0x0, remaining: 0 start_spi_dma_transaction: dest: 0x02200080, source: 0x468500, remaining: 122468 APOB thread done start_spi_dma_transaction: dest: 0x02210080, source: 0x478500, remaining: 56932 spi_dma_readat_dma: end: dest: 0x02200080, source: 0x468500, remaining: 0 <-- ramstage done Timestamp - returning from FspMemoryInit: 875159 This does cause a slight delay in FSP-M. The FSP-M timestamps do fluctuate a bit from run to run. The interesting part is that we save `12 ms` by preloading ramstage, but FSP-S then gobbles up the savings. I suspect there is a bottleneck in FSP-S. | 950 - calling FspMemoryInit | 2.174 | 2.137 Δ( -0.04, -0.00%) | | 951 - returning from FspMemoryInit | 220.637 | 224.645 Δ( 4.01, 0.29%) | | 550 - starting to load Chrome OS VPD | 0.048 | 0.047 Δ( -0.00, -0.00%) | | 552 - finished loading Chrome OS VPD (RW) | 0.036 | 0.036 Δ( 0.00, 0.00%) | | 3 - after RAM initialization | 0.013 | 0.013 Δ( 0.00, 0.00%) | | 920 - starting APOB read | 0.005 | 0.006 Δ( 0.00, 0.00%) | | 923 - finished APOB | 0.125 | 0.124 Δ( -0.00, -0.00%) | | 4 - end of romstage | 0.006 | 0.006 Δ( 0.00, 0.00%) | | 8 - starting to load ramstage | 0.001 | 0.001 Δ( 0.00, 0.00%) | | 15 - starting LZMA decompress (ignore for x86) | 0.009 | 0.012 Δ( 0.00, 0.00%) | | 16 - finished LZMA decompress (ignore for x86) | 27.41 | 14.704 Δ(-12.71, -0.91%) | | 9 - finished loading ramstage | 0.584 | 0.583 Δ( -0.00, -0.00%) | | 10 - start of ramstage | 0.045 | 0.045 Δ( 0.00, 0.00%) | | 30 - device enumeration | 2.039 | 2.029 Δ( -0.01, -0.00%) | | 971 - loading FSP-S | 7.112 | 6.685 Δ( -0.43, -0.03%) | | 17 - starting LZ4 decompress (ignore for x86) | 0.012 | 0.011 Δ( -0.00, -0.00%) | | 18 - finished LZ4 decompress (ignore for x86) | 0.204 | 0.204 Δ( 0.00, 0.00%) | | 954 - calling FspSiliconInit | 0.058 | 0.058 Δ( 0.00, 0.00%) | | 955 - returning from FspSiliconInit | 188.133 | 201.426 Δ( 13.29, 0.95%) | Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I93ae358986059cdae6069421f4efba586235df51 --- M src/soc/amd/cezanne/fsp_m_params.c 1 file changed, 11 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/58983/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/58983 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I93ae358986059cdae6069421f4efba586235df51 Gerrit-Change-Number: 58983 Gerrit-PatchSet: 4 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: soc/amd/cezanne/fsp: Set the void_function parameter
by Raul Rangel (Code Review) 19 Nov '21

19 Nov '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Felix Held. Hello build bot (Jenkins), Jason Glenesk, Marshall Dawson, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/58991 to look at the new patch set (#2). Change subject: soc/amd/cezanne/fsp: Set the void_function parameter ...................................................................... soc/amd/cezanne/fsp: Set the void_function parameter FSP will periodically call the void_function while FSP-M and FSP-S are executing. FSP-M and FSP-S take 225ms and 180ms to execute. By having FSP call back into coreboot, we can enqueue multiple SPI DMA transactions during that time. This allows the APOB and payload to be preloaded before FSP-S completes. This reduces boot time a bit because we no longer contents with the ELOG init. BUG=b:179699789 TEST=Boot guybrush and verify callback is getting called and payload is preloaded. | 114 - started elog init | 0.098 | 0.1 Δ( 0.00, 0.00%) | | 115 - finished elog init | 16.917 | 11.179 Δ( -5.74, -0.41%) | Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I02818987a574f14f790d34f4f0af6b993c520727 --- M src/soc/amd/cezanne/fsp_m_params.c M src/soc/amd/cezanne/fsp_s_params.c 2 files changed, 22 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/58991/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/58991 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I02818987a574f14f790d34f4f0af6b993c520727 Gerrit-Change-Number: 58991 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: soc/amd/cezanne/romstage: Preload fspm.bin
by Raul Rangel (Code Review) 19 Nov '21

19 Nov '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Rob Barnes. Hello build bot (Jenkins), Jason Glenesk, Marshall Dawson, Rob Barnes, Karthik Ramasubramanian, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/58988 to look at the new patch set (#8). Change subject: soc/amd/cezanne/romstage: Preload fspm.bin ...................................................................... soc/amd/cezanne/romstage: Preload fspm.bin FSP-M is normally memmapped and then decompressed. The SPI DMA controller can actually read faster than mmap. So by reading the contents into a buffer and then decompressing we reduce boot time. It is interesting that FSP-M takes an additional 8ms to execute. I suspect since we call it 50ms earlier it's having to wait for one of its dependencies. BUG=b:179699789 TEST=Boot guybrush and see 30ms reduction in boot time | 970 - loading FSP-M | 0.316 | 0.997 Δ( 0.68, 0.05%) | | 17 - starting LZ4 decompress (ignore for x86) | 0.026 | 13.874 Δ( 13.85, 0.96%) | | 18 - finished LZ4 decompress (ignore for x86) | 64.361 | 0.337 Δ(-64.02, -4.43%) | | 2 - before RAM initialization | 0.534 | 0.529 Δ( -0.01, -0.00%) | | 950 - calling FspMemoryInit | 1.455 | 1.132 Δ( -0.32, -0.02%) | | 951 - returning from FspMemoryInit | 207.695 | 216.537 Δ( 8.84, 0.61%) | Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I850b1576501753a355e7b23745e04802a0560387 --- M src/soc/amd/cezanne/fsp_s_params.c M src/soc/amd/cezanne/romstage.c 2 files changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/58988/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/58988 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I850b1576501753a355e7b23745e04802a0560387 Gerrit-Change-Number: 58988 Gerrit-PatchSet: 8 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: lib: Add a mutex
by Raul Rangel (Code Review) 19 Nov '21

19 Nov '21

Attention is currently required from: Julius Werner, Rob Barnes, Kyösti Mälkki, Karthik Ramasubramanian. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59320 ) Change subject: lib: Add a mutex ...................................................................... Patch Set 4: (4 comments) File src/include/mutex.h: https://review.coreboot.org/c/coreboot/+/59320/comment/fc409d08_7840106b PS2, Line 11: void mutex_unlock(struct mutex *mutex); > I don't think we should add all these calls to builds where they really do nothing at all, just to s […] Done File src/lib/mutex.c: https://review.coreboot.org/c/coreboot/+/59320/comment/9e48ae10_b68ab78d PS2, Line 24: #if ENV_X86 > Hmmm... […] The current spinlock implementation is just a tight loop: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/thi… File src/lib/mutex.c: https://review.coreboot.org/c/coreboot/+/59320/comment/e1efd9c1_da0c1a2a PS3, Line 27: continue; > If we're keeping this code I find the continue here pretty weird -- the effect is the same as not ha […] Done https://review.coreboot.org/c/coreboot/+/59320/comment/5d3fafc1_5ee5c3dd PS3, Line 31: } while (__atomic_load_1(&mutex->locked, __ATOMIC_RELAXED)); Yeah it does. Quoting from https://gcc.gnu.org/wiki/Atomic/GCCMM/AtomicSync#Relaxed > There is also the presumption that relaxed stores from one thread are seen by relaxed loads in another thread within a reasonable amount of time. That means that on non-cache-coherent architectures, relaxed operations need to flush the cache (although these flushes can be merged across several relaxed operations) The relaxed model just doesn't guarantee you can see side effects to other variables. But since we are only using 1 variable it work. -- To view, visit https://review.coreboot.org/c/coreboot/+/59320 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I41e02a54a17b1f6513b36a0274e43fc715472d78 Gerrit-Change-Number: 59320 Gerrit-PatchSet: 4 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Fri, 19 Nov 2021 21:04:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: lib: Add a mutex
by Raul Rangel (Code Review) 19 Nov '21

19 Nov '21

Attention is currently required from: Julius Werner, Rob Barnes, Kyösti Mälkki, Karthik Ramasubramanian. Hello build bot (Jenkins), Julius Werner, Rob Barnes, Kyösti Mälkki, Karthik Ramasubramanian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59320 to look at the new patch set (#4). Change subject: lib: Add a mutex ...................................................................... lib: Add a mutex We currently have two synchronization primatives, spinlock and thread_mutex. spinlock is meant to block multiple CPUs from entering a critical section. thread_mutex is meant to block multiple coop-threads from entering a critical section. It is not AP aware at all. This CL introduces a mutex that can handle both concepts. The implementation is using the GCC/LLVM atomic builtin functions. The generated code uses the xchg instruction vs spinlock which uses (lock) decb. 8: b0 01 mov $0x1,%al a: 86 03 xchg %al,(%ebx) c: 84 c0 test %al,%al BUG=b:179699789 TEST=Boot guybrush to OS Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I41e02a54a17b1f6513b36a0274e43fc715472d78 --- A src/include/mutex.h M src/lib/Makefile.inc A src/lib/mutex.c 3 files changed, 85 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/59320/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/59320 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I41e02a54a17b1f6513b36a0274e43fc715472d78 Gerrit-Change-Number: 59320 Gerrit-PatchSet: 4 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: cpu/intel/model_1067x: Use apic exposed in static.c directly
by Tim Wawrzynczak (Code Review) 19 Nov '21

19 Nov '21

Attention is currently required from: Arthur Heymans, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59317 ) Change subject: cpu/intel/model_1067x: Use apic exposed in static.c directly ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: why treat this one differently? -- To view, visit https://review.coreboot.org/c/coreboot/+/59317 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifa83ccf6033cbb135c7ec2e9593596dba4c6e3b5 Gerrit-Change-Number: 59317 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 19 Nov 2021 20:51:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: util/sconfig: Expose apic devices
by Tim Wawrzynczak (Code Review) 19 Nov '21

19 Nov '21

Attention is currently required from: Arthur Heymans, Raul Rangel, Nico Huber, Furquan Shaikh, Martin Roth, Angel Pons. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59313 ) Change subject: util/sconfig: Expose apic devices ...................................................................... Patch Set 2: (1 comment) File src/include/device/device.h: https://review.coreboot.org/c/coreboot/+/59313/comment/b847398f_7dd40cd2 PS2, Line 391: config_of_lapic > Just to be explicit, I'd use `config_of_lapic_0` sounds legit -- To view, visit https://review.coreboot.org/c/coreboot/+/59313 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I800f089998f4a9be2216ed997cec5cedeb63f3db Gerrit-Change-Number: 59313 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Fri, 19 Nov 2021 20:49:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: cpu/intel/model_2065x: Use static.c exposed lapic 0
by Tim Wawrzynczak (Code Review) 19 Nov '21

19 Nov '21

Attention is currently required from: Arthur Heymans, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59315 ) Change subject: cpu/intel/model_2065x: Use static.c exposed lapic 0 ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59315 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I296631511b0e31b0ed43ca8193552483bdab4482 Gerrit-Change-Number: 59315 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 19 Nov 2021 20:45:23 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: cpu/haswell/*.c: Use static.c exposed lapic 0
by Tim Wawrzynczak (Code Review) 19 Nov '21

19 Nov '21

Attention is currently required from: Arthur Heymans, Raul Rangel, Tristan Corrick, Angel Pons, Alexander Couzens, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59314 ) Change subject: cpu/haswell/*.c: Use static.c exposed lapic 0 ...................................................................... Patch Set 2: Code-Review+2 (1 comment) File src/mainboard/google/auron/devicetree.cb: https://review.coreboot.org/c/coreboot/+/59314/comment/d9d20708_4b816946 PS2, Line 20: device lapic 0xacac off end > > you would then have two isolated chips in the devicetree, which doesn't make sense. […] There are different ways to set up the devicetree organizationally, and they're probably all going to have their quirks unless you rewrite the whole thing -- To view, visit https://review.coreboot.org/c/coreboot/+/59314 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic449b2df8036e8c02b5559cca6b2e7479a70a786 Gerrit-Change-Number: 59314 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 19 Nov 2021 20:44:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: util/sconfig: Expose apic devices
by Tim Wawrzynczak (Code Review) 19 Nov '21

19 Nov '21

Attention is currently required from: Arthur Heymans, Raul Rangel, Nico Huber, Furquan Shaikh, Martin Roth. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59313 ) Change subject: util/sconfig: Expose apic devices ...................................................................... Patch Set 2: Code-Review+2 (1 comment) Patchset: PS2: I agree with Raul there are probably different organizational ways to set this up, but I think they're all going to have their quirks without a lot of overhauls. This seems much cleaner than adding devices with magic path values to the devicetree. -- To view, visit https://review.coreboot.org/c/coreboot/+/59313 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I800f089998f4a9be2216ed997cec5cedeb63f3db Gerrit-Change-Number: 59313 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Comment-Date: Fri, 19 Nov 2021 20:43:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit November 2021