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Hello Ryan Chuang,
I'd like you to do a code review. Please visit
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to review the following change.
Change subject: vc/mediatek/mt8195: Fix rank1 CKE setting for single-rank DRAM
......................................................................
vc/mediatek/mt8195: Fix rank1 CKE setting for single-rank DRAM
Fix rank1 CKE setting for single-rank DRAM power consumption issue.
BUG=b:196867407
TEST=DUT can boot to OS.
Signed-off-by: Ryan Chuang <ryan.chuang(a)mediatek.corp-partner.google.com>
Change-Id: If336197aea4770dda1332b6e83da8ec9a4f9d77b
---
M src/vendorcode/mediatek/mt8195/dramc/dramc_pi_main.c
1 file changed, 5 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/59715/1
diff --git a/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_main.c b/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_main.c
index e7e8f89..e3baf7b 100644
--- a/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_main.c
+++ b/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_main.c
@@ -1946,6 +1946,11 @@
#endif
}
+ if (p->support_rank_num == RANK_SINGLE){
+ CKEFixOnOff(p, RANK_1, CKE_DYNAMIC, TO_ALL_CHANNEL);
+ mcSHOW_DBG_MSG(("Set RANK1 CKE to DYNAMIC\n"));
+ }
+
#if (FOR_DV_SIMULATION_USED == 0 && SW_CHANGE_FOR_SIMULATION == 0)
U32 backup_broadcast;
backup_broadcast = GetDramcBroadcast();
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Hou-hsun Lee has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58241 )
Change subject: mb/google/brya/var/baseboard/brask: Add power limits functions
......................................................................
Patch Set 15:
(1 comment)
File src/mainboard/google/brya/variants/baseboard/brask/ramstage.c:
https://review.coreboot.org/c/coreboot/+/58241/comment/3c3509b6_4dbc4e00
PS14, Line 108: soc_config->tdp_pl4 = 0;
> Yes, it's correct. Added comments in variants.h.
Done
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Change subject: mb/google/brya/var/brask: Set PL and PsysPL
......................................................................
Patch Set 2:
(1 comment)
File src/mainboard/google/brya/variants/brask/ramstage.c:
https://review.coreboot.org/c/coreboot/+/59576/comment/0bc4edec_26317fa1
PS1, Line 18: { PCI_DEVICE_ID_INTEL_ADL_P_ID_1, 45, 5000, 45000, 80000, 80000, 159000 },
> Yes, you're correct.
Done
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Change subject: mb/google/brya/var/brask: Set PL and PsysPL
......................................................................
Patch Set 2:
(1 comment)
File src/mainboard/google/brya/variants/brask/ramstage.c:
https://review.coreboot.org/c/coreboot/+/59576/comment/5fc13410_7589020e
PS1, Line 18: { PCI_DEVICE_ID_INTEL_ADL_P_ID_1, 45, 5000, 45000, 80000, 80000, 159000 },
> According to the HW design, we will use performance config. […]
Yes, you're correct.
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Kane Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59558 )
Change subject: mb/google/zork/var/shuboz: Add fw_config probe for ALC5682-VD & VS
......................................................................
Patch Set 5:
(1 comment)
File src/mainboard/google/zork/variants/shuboz/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/59558/comment/fdd0acb7_09b3185b
PS5, Line 2: fw_config
> So IIUC it SSFC is not set devicetree doesn't match `option AUDIO_CODEC_ALC5682 0` and emit nothing […]
Hi Kangheui,
We tested the single setting codec in "overridetree.cb" SSFC can work, but we set two setting of codec, the first settings will be invalid. Thanks.
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Change subject: mainboard/google/brya/variants/brask: Enable audio driver option in bios-stage for brask
......................................................................
Set Ready For Review
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build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59705 )
Change subject: mainboard/starlabs/labtop: Enable/disable Thunderbolt based on CMOS
......................................................................
Patch Set 2:
(2 comments)
File src/mainboard/starlabs/labtop/variants/tgl/devtree.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-134564):
https://review.coreboot.org/c/coreboot/+/59705/comment/30b82344_e7e3bfbd
PS2, Line 59: }
code indent should use tabs where possible
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-134564):
https://review.coreboot.org/c/coreboot/+/59705/comment/d6d7721e_e111d11f
PS2, Line 59: }
please, no spaces at the start of a line
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Sean Rhodes has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/59706 )
Change subject: mainboard/starlabs/labtop: Change logic for CMOS handling
......................................................................
Abandoned
Not needed
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