coreboot-gerrit November 2021

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Change in coreboot[master]: soc/mediatek: move bustracker_init before watchdog resets again
by Felix Held (Code Review) 29 Nov '21

29 Nov '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59667 ) Change subject: soc/mediatek: move bustracker_init before watchdog resets again ...................................................................... soc/mediatek: move bustracker_init before watchdog resets again The checking register will be cleared after EC resets, so we move bustracker dump from ramstage to bootblock, before triggering EC reset. TEST=bustracker shows status before watchdog resets BUG=b:207743045 Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Change-Id: Ic18dc9742cd9f657a035a374e28371dfc5f04ac3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59667 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> --- M src/soc/mediatek/mt8192/Makefile.inc M src/soc/mediatek/mt8192/bootblock.c M src/soc/mediatek/mt8192/soc.c M src/soc/mediatek/mt8195/Makefile.inc M src/soc/mediatek/mt8195/bootblock.c M src/soc/mediatek/mt8195/soc.c 6 files changed, 7 insertions(+), 6 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc index a75ac28..b04acb5 100644 --- a/src/soc/mediatek/mt8192/Makefile.inc +++ b/src/soc/mediatek/mt8192/Makefile.inc @@ -10,6 +10,7 @@ bootblock-y += ../common/pll.c pll.c bootblock-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c bootblock-y += ../common/timer.c +bootblock-y += ../common/tracker.c bootblock-y += ../common/uart.c bootblock-y += ../common/wdt.c @@ -63,7 +64,6 @@ ramstage-y += soc.c ramstage-y += ../common/spm.c spm.c ramstage-y += ../common/sspm.c -ramstage-y += ../common/tracker.c ramstage-y += ../common/timer.c ramstage-y += ../common/uart.c ramstage-y += ../common/ufs.c diff --git a/src/soc/mediatek/mt8192/bootblock.c b/src/soc/mediatek/mt8192/bootblock.c index 17fd27e..3adf5c1 100644 --- a/src/soc/mediatek/mt8192/bootblock.c +++ b/src/soc/mediatek/mt8192/bootblock.c @@ -4,11 +4,13 @@ #include <soc/eint_event.h> #include <soc/mmu_operations.h> #include <soc/pll.h> +#include <soc/tracker_common.h> #include <soc/wdt.h> void bootblock_soc_init(void) { mtk_mmu_init(); + bustracker_init(); mtk_wdt_init(); mt_pll_init(); unmask_eint_event_mask(); diff --git a/src/soc/mediatek/mt8192/soc.c b/src/soc/mediatek/mt8192/soc.c index 355827a..006a212 100644 --- a/src/soc/mediatek/mt8192/soc.c +++ b/src/soc/mediatek/mt8192/soc.c @@ -9,7 +9,6 @@ #include <soc/mcupm.h> #include <soc/mmu_operations.h> #include <soc/sspm.h> -#include <soc/tracker_common.h> #include <soc/ufs.h> #include <symbols.h> @@ -34,7 +33,6 @@ if (CONFIG(MTK_DFD)) dfd_init(); ufs_disable_refclk(); - bustracker_init(); } static struct device_operations soc_ops = { diff --git a/src/soc/mediatek/mt8195/Makefile.inc b/src/soc/mediatek/mt8195/Makefile.inc index c6f4226..a7ada28 100644 --- a/src/soc/mediatek/mt8195/Makefile.inc +++ b/src/soc/mediatek/mt8195/Makefile.inc @@ -7,6 +7,7 @@ bootblock-y += ../common/gpio.c gpio.c bootblock-y += ../common/i2c.c i2c.c bootblock-y += ../common/mmu_operations.c +bootblock-y += ../common/tracker.c bootblock-y += ../common/pll.c pll.c bootblock-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c bootblock-y += ../common/timer.c timer.c @@ -50,7 +51,7 @@ romstage-y += mt6691.c romstage-y += mt6360.c romstage-y += ../common/rtc.c ../common/rtc_osc_init.c ../common/rtc_mt6359p.c -ramstage-y += ../common/tracker.c + ramstage-y += ../common/auxadc.c ramstage-y += ../common/ddp.c ddp.c ramstage-y += devapc.c diff --git a/src/soc/mediatek/mt8195/bootblock.c b/src/soc/mediatek/mt8195/bootblock.c index 17fd27e..3adf5c1 100644 --- a/src/soc/mediatek/mt8195/bootblock.c +++ b/src/soc/mediatek/mt8195/bootblock.c @@ -4,11 +4,13 @@ #include <soc/eint_event.h> #include <soc/mmu_operations.h> #include <soc/pll.h> +#include <soc/tracker_common.h> #include <soc/wdt.h> void bootblock_soc_init(void) { mtk_mmu_init(); + bustracker_init(); mtk_wdt_init(); mt_pll_init(); unmask_eint_event_mask(); diff --git a/src/soc/mediatek/mt8195/soc.c b/src/soc/mediatek/mt8195/soc.c index 80ca3d9..d28f668 100644 --- a/src/soc/mediatek/mt8195/soc.c +++ b/src/soc/mediatek/mt8195/soc.c @@ -10,7 +10,6 @@ #include <soc/mcupm.h> #include <soc/mmu_operations.h> #include <soc/sspm.h> -#include <soc/tracker_common.h> #include <soc/ufs.h> #include <symbols.h> @@ -38,7 +37,6 @@ ufs_disable_refclk(); hdmi_low_power_setting(); - bustracker_init(); } static struct device_operations soc_ops = { 4 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/59667 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic18dc9742cd9f657a035a374e28371dfc5f04ac3 Gerrit-Change-Number: 59667 Gerrit-PatchSet: 8 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/mediatek: Flush cache before triggering EC reset
by Felix Held (Code Review) 29 Nov '21

29 Nov '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59683 ) Change subject: soc/mediatek: Flush cache before triggering EC reset ...................................................................... soc/mediatek: Flush cache before triggering EC reset There will be no log in cbmem if we trigger ec reset on bootblock stage. Therefore, call dcache_clean_all() before triggering ec reset to flush cache to store logs on cbmem. BUG=b:207743045 TEST=show logs on cbmem Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Change-Id: I1bd900beb4cc84f7121c5fb66907fa73b62517fa Reviewed-on: https://review.coreboot.org/c/coreboot/+/59683 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> --- M src/soc/mediatek/common/wdt.c 1 file changed, 4 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved diff --git a/src/soc/mediatek/common/wdt.c b/src/soc/mediatek/common/wdt.c index f06fbf0..6e1b761 100644 --- a/src/soc/mediatek/common/wdt.c +++ b/src/soc/mediatek/common/wdt.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <arch/cache.h> #include <device/mmio.h> #include <console/console.h> #include <soc/wdt.h> @@ -27,7 +28,10 @@ * We trigger secondary reset by triggering WDT hardware to send signal to EC. * We do not use do_board_reset() to send signal to EC * which is controlled by software driver. + * Before triggering secondary reset, clean the data cache so the logs in cbmem + * console (either in SRAM or DRAM) can be flushed. */ + dcache_clean_all(); write32(&mtk_wdt->wdt_mode, MTK_WDT_MODE_EXTEN | MTK_WDT_MODE_KEY); write32(&mtk_wdt->wdt_swrst, MTK_WDT_SWRST_KEY); } else if (wdt_sta & MTK_WDT_STA_SW_RST) -- To view, visit https://review.coreboot.org/c/coreboot/+/59683 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1bd900beb4cc84f7121c5fb66907fa73b62517fa Gerrit-Change-Number: 59683 Gerrit-PatchSet: 6 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/common: Include Alder Lake-N device IDs
by Felix Held (Code Review) 29 Nov '21

29 Nov '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59306 ) Change subject: soc/intel/common: Include Alder Lake-N device IDs ...................................................................... soc/intel/common: Include Alder Lake-N device IDs Add Alder Lake-N specific CPU, System Agent, PCH (Alder Point aka ADP), IGD device IDs. Document Number: 619501, 645548 Signed-off-by: Usha P <usha.p(a)intel.com> Change-Id: I0974fc6ee2ca41d9525cc83155772f111c1fdf86 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59306 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/include/cpu/intel/cpu_ids.h M src/include/device/pci_ids.h M src/soc/intel/alderlake/bootblock/report_platform.c M src/soc/intel/common/block/cpu/mp_init.c M src/soc/intel/common/block/graphics/graphics.c M src/soc/intel/common/block/systemagent/systemagent.c 6 files changed, 20 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved diff --git a/src/include/cpu/intel/cpu_ids.h b/src/include/cpu/intel/cpu_ids.h index 5314076..0f7c5c1 100644 --- a/src/include/cpu/intel/cpu_ids.h +++ b/src/include/cpu/intel/cpu_ids.h @@ -55,5 +55,6 @@ #define CPUID_ALDERLAKE_A1 0x906a1 #define CPUID_ALDERLAKE_A2 0x906a2 #define CPUID_ALDERLAKE_A3 0x906a4 +#define CPUID_ALDERLAKE_N_A0 0xb06e0 #endif /* CPU_INTEL_CPU_IDS_H */ diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 63b735f..db51905 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -3886,6 +3886,10 @@ #define PCI_DEVICE_ID_INTEL_ADL_M_GT1 0x46c0 #define PCI_DEVICE_ID_INTEL_ADL_M_GT2 0x46aa #define PCI_DEVICE_ID_INTEL_ADL_M_GT3 0x46c3 +#define PCI_DEVICE_ID_INTEL_ADL_N_GT1 0x46D0 +#define PCI_DEVICE_ID_INTEL_ADL_N_GT2 0x46D1 +#define PCI_DEVICE_ID_INTEL_ADL_N_GT3 0x46D2 + /* Intel Northbridge Ids */ #define PCI_DEVICE_ID_INTEL_APL_NB 0x5af0 @@ -3997,6 +4001,9 @@ #define PCI_DEVICE_ID_INTEL_ADL_P_ID_9 0x467f #define PCI_DEVICE_ID_INTEL_ADL_M_ID_1 0x4602 #define PCI_DEVICE_ID_INTEL_ADL_M_ID_2 0x460a +#define PCI_DEVICE_ID_INTEL_ADL_N_ID_1 0x4617 +#define PCI_DEVICE_ID_INTEL_ADL_N_ID_2 0x461B + /* Intel SMBUS device Ids */ #define PCI_DEVICE_ID_INTEL_LPT_H_SMBUS 0x8c22 #define PCI_DEVICE_ID_INTEL_LPT_LP_SMBUS 0x9c22 diff --git a/src/soc/intel/alderlake/bootblock/report_platform.c b/src/soc/intel/alderlake/bootblock/report_platform.c index 2fc8eab..76e6c80 100644 --- a/src/soc/intel/alderlake/bootblock/report_platform.c +++ b/src/soc/intel/alderlake/bootblock/report_platform.c @@ -27,6 +27,7 @@ { CPUID_ALDERLAKE_A1, "Alderlake Platform" }, { CPUID_ALDERLAKE_A2, "Alderlake Platform" }, { CPUID_ALDERLAKE_A3, "Alderlake Platform" }, + { CPUID_ALDERLAKE_N_A0, "Alderlake-N Platform" }, }; static struct { @@ -43,6 +44,8 @@ { PCI_DEVICE_ID_INTEL_ADL_P_ID_9, "Alderlake-P" }, { PCI_DEVICE_ID_INTEL_ADL_M_ID_1, "Alderlake-M" }, { PCI_DEVICE_ID_INTEL_ADL_M_ID_2, "Alderlake-M" }, + { PCI_DEVICE_ID_INTEL_ADL_N_ID_1, "Alderlake-N" }, + { PCI_DEVICE_ID_INTEL_ADL_N_ID_2, "Alderlake-N" }, }; static struct { @@ -111,6 +114,9 @@ { PCI_DEVICE_ID_INTEL_ADL_M_GT1, "Alderlake M GT1" }, { PCI_DEVICE_ID_INTEL_ADL_M_GT2, "Alderlake M GT2" }, { PCI_DEVICE_ID_INTEL_ADL_M_GT3, "Alderlake M GT3" }, + { PCI_DEVICE_ID_INTEL_ADL_N_GT1, "Alderlake N GT1" }, + { PCI_DEVICE_ID_INTEL_ADL_N_GT2, "Alderlake N GT2" }, + { PCI_DEVICE_ID_INTEL_ADL_N_GT3, "Alderlake N GT3" }, }; static inline uint8_t get_dev_revision(pci_devfn_t dev) diff --git a/src/soc/intel/common/block/cpu/mp_init.c b/src/soc/intel/common/block/cpu/mp_init.c index acd15a8..b7e2243 100644 --- a/src/soc/intel/common/block/cpu/mp_init.c +++ b/src/soc/intel/common/block/cpu/mp_init.c @@ -72,6 +72,7 @@ { X86_VENDOR_INTEL, CPUID_ALDERLAKE_A1 }, { X86_VENDOR_INTEL, CPUID_ALDERLAKE_A2 }, { X86_VENDOR_INTEL, CPUID_ALDERLAKE_A3 }, + { X86_VENDOR_INTEL, CPUID_ALDERLAKE_N_A0}, { 0, 0 }, }; diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c index e7e96ad..1db0e46 100644 --- a/src/soc/intel/common/block/graphics/graphics.c +++ b/src/soc/intel/common/block/graphics/graphics.c @@ -311,6 +311,9 @@ PCI_DEVICE_ID_INTEL_ADL_M_GT1, PCI_DEVICE_ID_INTEL_ADL_M_GT2, PCI_DEVICE_ID_INTEL_ADL_M_GT3, + PCI_DEVICE_ID_INTEL_ADL_N_GT1, + PCI_DEVICE_ID_INTEL_ADL_N_GT2, + PCI_DEVICE_ID_INTEL_ADL_N_GT3, 0, }; diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c index 572b417..b7c6d4f 100644 --- a/src/soc/intel/common/block/systemagent/systemagent.c +++ b/src/soc/intel/common/block/systemagent/systemagent.c @@ -435,6 +435,8 @@ PCI_DEVICE_ID_INTEL_ADL_P_ID_9, PCI_DEVICE_ID_INTEL_ADL_M_ID_1, PCI_DEVICE_ID_INTEL_ADL_M_ID_2, + PCI_DEVICE_ID_INTEL_ADL_N_ID_1, + PCI_DEVICE_ID_INTEL_ADL_N_ID_2, 0 }; 2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/59306 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0974fc6ee2ca41d9525cc83155772f111c1fdf86 Gerrit-Change-Number: 59306 Gerrit-PatchSet: 4 Gerrit-Owner: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kangheui Won <khwon(a)google.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-CC: Usha P <usha.p(a)intel.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/alderlake: Trigger cse_fw_sync before DRAM Init
by Felix Held (Code Review) 29 Nov '21

29 Nov '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55364 ) Change subject: soc/intel/alderlake: Trigger cse_fw_sync before DRAM Init ...................................................................... soc/intel/alderlake: Trigger cse_fw_sync before DRAM Init The patch enables cse_fw_sync() before DRAM initialization. cse_fw_sync() sends HECI commands in order to set CSE's boot partition and to trigger CSE firmware update. As part of CSE firmware update, coreboot sends HMRPFO_ENABLE HECI command. Since CSE supports the command after DRAM Initialization, cse_fw_sync() is called after DRAM initialization. Starting from CSE Litev16.0.15.1545, CSE support HMRFPO_ENABLE command before DRAM initialization too. So, cse_fw_sync() is called before DRAM initialization. BUG=b:175516533 TEST=Dependency with CSE Litev16.0.15.1545 integration Change-Id: Iad7403650df8bc4e40aa6e48ccfeba95a5789a2d Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55364 Reviewed-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Reviewed-by: Subrata Banik <subrata.banik(a)intel.com> Reviewed-by: Ronak Kanabar <ronak.kanabar(a)intel.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/alderlake/romstage/romstage.c 1 file changed, 4 insertions(+), 10 deletions(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved Maulik V Vaghela: Looks good to me, but someone else must approve Ronak Kanabar: Looks good to me, but someone else must approve diff --git a/src/soc/intel/alderlake/romstage/romstage.c b/src/soc/intel/alderlake/romstage/romstage.c index e84eca8..d33d21f 100644 --- a/src/soc/intel/alderlake/romstage/romstage.c +++ b/src/soc/intel/alderlake/romstage/romstage.c @@ -129,6 +129,9 @@ s3wake = pmc_fill_power_state(ps) == ACPI_S3; + if (CONFIG(SOC_INTEL_CSE_LITE_SKU) && !s3wake) + cse_fw_sync(); + /* * Set low maximum temp threshold value used for dynamic thermal sensor * shutdown consideration. @@ -140,15 +143,6 @@ fsp_memory_init(s3wake); pmc_set_disb(); - if (!s3wake) { - /* - * cse_fw_sync() must be called after DRAM initialization as - * HMRFPO_ENABLE HECI command (which is used by cse_fw_sync()) - * is expected to be executed after DRAM initialization. - */ - if (CONFIG(SOC_INTEL_CSE_LITE_SKU)) - cse_fw_sync(); - + if (!s3wake) save_dimm_info(); - } } -- To view, visit https://review.coreboot.org/c/coreboot/+/55364 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iad7403650df8bc4e40aa6e48ccfeba95a5789a2d Gerrit-Change-Number: 55364 Gerrit-PatchSet: 15 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: cpu/x86: Rename X86_AMD_INIT_SIPI to X86_INIT_NEED_1_SIPI
by Felix Held (Code Review) 29 Nov '21

29 Nov '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56651 ) Change subject: cpu/x86: Rename X86_AMD_INIT_SIPI to X86_INIT_NEED_1_SIPI ...................................................................... cpu/x86: Rename X86_AMD_INIT_SIPI to X86_INIT_NEED_1_SIPI This patch renames X86_AMD_INIT_SIPI Kconfig to leverage the same logic (to skip 2nd SIPI and reduce delay between INIT and SIPI while perform AP initialization) even on newer Intel platform. Change-Id: I7a4e6a8b1edc6e8ba43597259bd8b2de697e4e62 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56651 Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/cpu/x86/Kconfig M src/cpu/x86/mp_init.c M src/soc/amd/cezanne/Kconfig M src/soc/amd/picasso/Kconfig 4 files changed, 7 insertions(+), 7 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index 44c9cb6..693b802 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -164,15 +164,15 @@ This option informs the MTRR code to use the RdMem and WrMem fields in the fixed MTRR MSRs. -config X86_AMD_INIT_SIPI +config X86_INIT_NEED_1_SIPI bool default n help This option limits the number of SIPI signals sent during during the common AP setup. Intel documentation specifies an INIT SIPI SIPI - sequence, however this doesn't work on some AMD platforms. These - newer AMD platforms don't need the 10ms wait between INIT and SIPI, - so skip that too to save some time. + sequence, however this doesn't work on some AMD and Intel platforms. + These newer AMD and Intel platforms don't need the 10ms wait between + INIT and SIPI, so skip that too to save some time. config SOC_SETS_MSRS bool diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index c99732f..9b5c230 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -469,7 +469,7 @@ /* Send INIT IPI to all but self. */ lapic_send_ipi(LAPIC_DEST_ALLBUT | LAPIC_INT_ASSERT | LAPIC_DM_INIT, 0); - if (!CONFIG(X86_AMD_INIT_SIPI)) { + if (!CONFIG(X86_INIT_NEED_1_SIPI)) { printk(BIOS_DEBUG, "Waiting for 10ms after sending INIT.\n"); mdelay(10); diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index 6c8c3e5..b4e808d 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -73,7 +73,7 @@ select SSE2 select UDK_2017_BINDING select X86_AMD_FIXED_MTRRS - select X86_AMD_INIT_SIPI + select X86_INIT_NEED_1_SIPI config ARCH_ALL_STAGES_X86 default n diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 92607a3..a52ce9a 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -16,7 +16,7 @@ select ARCH_X86 select RESET_VECTOR_IN_RAM select X86_AMD_FIXED_MTRRS - select X86_AMD_INIT_SIPI + select X86_INIT_NEED_1_SIPI select ACPI_SOC_NVS select ADD_FSP_BINARIES if USE_AMD_BLOBS select DRIVERS_I2C_DESIGNWARE -- To view, visit https://review.coreboot.org/c/coreboot/+/56651 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7a4e6a8b1edc6e8ba43597259bd8b2de697e4e62 Gerrit-Change-Number: 56651 Gerrit-PatchSet: 5 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Subrata Banik <subi.banik(a)gmail.com> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/medaitek: add prompt string to config MTK_DFD
by Felix Held (Code Review) 29 Nov '21

29 Nov '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59621 ) Change subject: soc/medaitek: add prompt string to config MTK_DFD ...................................................................... soc/medaitek: add prompt string to config MTK_DFD Add prompt string to allow selecting MTK_DFD manually. TEST=Select and enable MTK_DFD then successfully built firmware images. BUG=b:207450135 Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Change-Id: Ied711321efa592cf1bf7b318fe4d0aa155c15c70 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59621 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> --- M src/soc/mediatek/common/Kconfig 1 file changed, 4 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved diff --git a/src/soc/mediatek/common/Kconfig b/src/soc/mediatek/common/Kconfig index b581ffb..7d1e455 100644 --- a/src/soc/mediatek/common/Kconfig +++ b/src/soc/mediatek/common/Kconfig @@ -36,9 +36,10 @@ This option enables four channel configuration for DPM. config MTK_DFD - bool - default n + bool "Enable MediaTek DFD (Design For Debug) settings" help - This option enables DFD (Design for Debug) settings. + DFD (Design for Debug) is a debugging tool, which scans flip-flops + and dumps to internal RAM on the WDT reset. We reserve 1MB on DRAM + to store logs of DFD. endif -- To view, visit https://review.coreboot.org/c/coreboot/+/59621 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ied711321efa592cf1bf7b318fe4d0aa155c15c70 Gerrit-Change-Number: 59621 Gerrit-PatchSet: 7 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/stoneyridge/psp: move soc_get_mbox_address to common psp_gen1
by Felix Held (Code Review) 29 Nov '21

29 Nov '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Paul Menzel. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59701 ) Change subject: soc/amd/stoneyridge/psp: move soc_get_mbox_address to common psp_gen1 ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/59701/comment/12bf3195_38f53c6a PS1, Line 9: one only > the only? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/59701 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I78126cb710a6ee674b58b35c8294685a5965ecd6 Gerrit-Change-Number: 59701 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Mon, 29 Nov 2021 09:34:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/stoneyridge/psp: move soc_get_mbox_address to common psp_gen1
by Felix Held (Code Review) 29 Nov '21

29 Nov '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Felix Held. Hello Jason Glenesk, Raul Rangel, Marshall Dawson, Paul Menzel, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59701 to look at the new patch set (#2). Change subject: soc/amd/stoneyridge/psp: move soc_get_mbox_address to common psp_gen1 ...................................................................... soc/amd/stoneyridge/psp: move soc_get_mbox_address to common psp_gen1 Despite Stoneyridge being the only SoC in soc/amd that uses the first generation of the PSP mailblox interface, this code is common for all SoCs that use the first PSP mailbox interface generation, so move it to the common PSP generation 1 code. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I78126cb710a6ee674b58b35c8294685a5965ecd6 --- M src/soc/amd/common/block/include/amdblocks/psp.h M src/soc/amd/common/block/psp/psp_gen1.c M src/soc/amd/stoneyridge/include/soc/southbridge.h M src/soc/amd/stoneyridge/psp.c 4 files changed, 35 insertions(+), 33 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/59701/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59701 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I78126cb710a6ee674b58b35c8294685a5965ecd6 Gerrit-Change-Number: 59701 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/mediatek: Add PCIe support
by Yu-Ping Wu (Code Review) 29 Nov '21

29 Nov '21

Attention is currently required from: Shelley Chen, Hung-Te Lin, Furquan Shaikh, Paul Menzel, Jianjun Wang. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56791 ) Change subject: soc/mediatek: Add PCIe support ...................................................................... Patch Set 4: (8 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/56791/comment/de2fca35_10609295 PS3, Line 11: > Since this file is not platform related, I'm not sure if this is a good idea to add this comment in pcie.c like src/soc/mediatek/mt8186/pll.c does. Fine. Then please explain it in the commit message. File src/soc/mediatek/common/pcie.c: https://review.coreboot.org/c/coreboot/+/56791/comment/832a1669_d1fed5fd PS2, Line 329: mtk_pcie_gen3_probe > Thanks for your suggestion, I removed most of these redundant functions, but there are still some re […] Furquan is no longer in the team. Shelly, do you mind reviewing this? File src/soc/mediatek/common/pcie.c: https://review.coreboot.org/c/coreboot/+/56791/comment/672841bb_b391445b PS4, Line 116: i size_t for i https://review.coreboot.org/c/coreboot/+/56791/comment/ed5b4858_813e6dcb PS4, Line 194: - 1 There's already "(size) - 1" in PCIE_ATR_SIZE(). Please confirm if this extra "- 1" is needed. https://review.coreboot.org/c/coreboot/+/56791/comment/1251b875_7c424693 PS4, Line 200: printk(BIOS_INFO, "%s: set %s trans window[%d]: cpu_addr = %#llx, pci_addr = %#llx, size = %#llx\n", Line too long. https://review.coreboot.org/c/coreboot/+/56791/comment/14215fac_f442ebe8 PS4, Line 202: (unsigned long long) Why do we need to cast it? Can't we just print with %#x? https://review.coreboot.org/c/coreboot/+/56791/comment/9e8d767d_93864785 PS4, Line 216: if (!res->size) : continue; When will this happen? https://review.coreboot.org/c/coreboot/+/56791/comment/bc9fdf0d_af8968cb PS4, Line 326: (struct bus *) No need to cast. -- To view, visit https://review.coreboot.org/c/coreboot/+/56791 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib9b6adaafa20aeee136372ec9564273f86776da0 Gerrit-Change-Number: 56791 Gerrit-PatchSet: 4 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Comment-Date: Mon, 29 Nov 2021 09:16:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Comment-In-Reply-To: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek: Add PCIe support
by Jianjun Wang (Code Review) 29 Nov '21

29 Nov '21

Attention is currently required from: Shelley Chen, Hung-Te Lin, Furquan Shaikh, Paul Menzel, Yu-Ping Wu. Jianjun Wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56791 ) Change subject: soc/mediatek: Add PCIe support ...................................................................... Patch Set 4: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/56791/comment/c8036bf9_d95c129e PS3, Line 11: > > MT8195 Register Map V0.3-2, Chapter 3.18 PCIe controller (Page 1250). […] This file is created based on MT8195, but all these codes should be common in each platform with the same PCIe IP in the future. Since this file is not platform related, I'm not sure if this is a good idea to add this comment in pcie.c like src/soc/mediatek/mt8186/pll.c does. -- To view, visit https://review.coreboot.org/c/coreboot/+/56791 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib9b6adaafa20aeee136372ec9564273f86776da0 Gerrit-Change-Number: 56791 Gerrit-PatchSet: 4 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Mon, 29 Nov 2021 08:49:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Comment-In-Reply-To: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-MessageType: comment

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coreboot-gerrit November 2021