coreboot-gerrit November 2021

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: arch/x86: Init firmware pointer for EC SMSC KBC1098/KBC1126 at build ...
by Bill XIE (Code Review) 29 Nov '21

29 Nov '21

Attention is currently required from: Bill XIE, Nico Huber, Patrick Rudolph, Angel Pons, Julius Werner, Arthur Heymans, Michael Niewöhner, Kyösti Mälkki, Aaron Durbin. Hello build bot (Jenkins), Nico Huber, Patrick Rudolph, Angel Pons, Julius Werner, Arthur Heymans, Michael Niewöhner, Kyösti Mälkki, Aaron Durbin, Iru Cai, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/51671 to look at the new patch set (#29). Change subject: arch/x86: Init firmware pointer for EC SMSC KBC1098/KBC1126 at build time ...................................................................... arch/x86: Init firmware pointer for EC SMSC KBC1098/KBC1126 at build time According to util/kbc1126/README.md, for these ECs to work, the address and size of their two firmware should be written to $s-0x100` (`$s` means the image size, done with kbc1126_ec_insert), which means that every existing section (especially those used to store code) should not overlap this address, otherwise the bootblock will get damaged when inserting firmwares of the EC. In this commit, ecfw_ptr is a structure initialized at build time according to CONFIG_KBC1126_FW1_OFFSET and CONFIG_KBC1126_FW2_OFFSET (to do so, they should be redefined as hex), and linked to CONFIG_ECFW_PTR_ADDR within bootblock, so kbc1126_ec_insert is not needed at build time any more. Test passed on Elitebook Folio 9470m. Signed-off-by: Bill XIE <persmule(a)hardenedlinux.org> Change-Id: I4f0de0c4d7283e630242fbe84a46e0547783c49e --- M src/arch/x86/Kconfig M src/arch/x86/bootblock.ld M src/ec/hp/kbc1126/Kconfig M src/ec/hp/kbc1126/Makefile.inc A src/ec/hp/kbc1126/ecfw_ptr.c A src/ec/hp/kbc1126/ecfw_ptr.h 6 files changed, 77 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/51671/29 -- To view, visit https://review.coreboot.org/c/coreboot/+/51671 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4f0de0c4d7283e630242fbe84a46e0547783c49e Gerrit-Change-Number: 51671 Gerrit-PatchSet: 29 Gerrit-Owner: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Iru Cai <mytbk920423(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Aaron Durbin <adurbin(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/brya/var/brask: Configure the ISOLATE pin of LAN
by Zhuohao Lee (Code Review) 29 Nov '21

29 Nov '21

Attention is currently required from: David Wu, Tim Wawrzynczak, Paul Menzel, Alan Huang. Zhuohao Lee has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58105 ) Change subject: mb/google/brya/var/brask: Configure the ISOLATE pin of LAN ...................................................................... Patch Set 9: (1 comment) File src/mainboard/google/brya/variants/brask/overridetree.cb: https://review.coreboot.org/c/coreboot/+/58105/comment/abe247e9_6e952180 PS5, Line 86: register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H22)" > Yes. The ISOLATE pin is active low. […] Thanks for clarification. I don't have concern for this now. Please modify the gpio pin to GPP_A7 -- To view, visit https://review.coreboot.org/c/coreboot/+/58105 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2e82dbc1e6c68cbd84b603adc7fdc3ee1d4d3392 Gerrit-Change-Number: 58105 Gerrit-PatchSet: 9 Gerrit-Owner: Alan Huang <alan-huang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Alan Huang <alan-huang(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Mon, 29 Nov 2021 03:48:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Zhuohao Lee <zhuohao(a)google.com> Comment-In-Reply-To: Alan Huang <alan-huang(a)quanta.corp-partner.google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: pci_mmio_cfg: Rename pcicfg to pci_map_bus
by Hung-Te Lin (Code Review) 29 Nov '21

29 Nov '21

Hung-Te Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59702 ) Change subject: pci_mmio_cfg: Rename pcicfg to pci_map_bus ...................................................................... pci_mmio_cfg: Rename pcicfg to pci_map_bus Rename pcicfg to pci_map_bus and add prototype for the platforms not supporting ECAM. Signed-off-by: Jianjun Wang <jianjun.wang(a)mediatek.com> Change-Id: Id9517c5ec4fa6b7c7a34552bfdc6d509927f6730 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59702 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> --- M src/include/device/pci_mmio_cfg.h 1 file changed, 16 insertions(+), 10 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved diff --git a/src/include/device/pci_mmio_cfg.h b/src/include/device/pci_mmio_cfg.h index cabf5b7..89c9906 100644 --- a/src/include/device/pci_mmio_cfg.h +++ b/src/include/device/pci_mmio_cfg.h @@ -40,11 +40,17 @@ extern u8 *const pci_mmconf; static __always_inline -volatile union pci_bank *pcicfg(pci_devfn_t dev) +volatile union pci_bank *pci_map_bus(pci_devfn_t dev) { return (void *)&pci_mmconf[PCI_DEVFN_OFFSET(dev)]; } +#else + +/* For platforms not supporting ECAM, they need to define pci_map_bus function + * in their platform-specific code */ +volatile union pci_bank *pci_map_bus(pci_devfn_t dev); + #endif /* @@ -56,37 +62,37 @@ static __always_inline uint8_t pci_s_read_config8(pci_devfn_t dev, uint16_t reg) { - return pcicfg(dev)->reg8[reg]; + return pci_map_bus(dev)->reg8[reg]; } static __always_inline uint16_t pci_s_read_config16(pci_devfn_t dev, uint16_t reg) { - return pcicfg(dev)->reg16[reg / sizeof(uint16_t)]; + return pci_map_bus(dev)->reg16[reg / sizeof(uint16_t)]; } static __always_inline uint32_t pci_s_read_config32(pci_devfn_t dev, uint16_t reg) { - return pcicfg(dev)->reg32[reg / sizeof(uint32_t)]; + return pci_map_bus(dev)->reg32[reg / sizeof(uint32_t)]; } static __always_inline void pci_s_write_config8(pci_devfn_t dev, uint16_t reg, uint8_t value) { - pcicfg(dev)->reg8[reg] = value; + pci_map_bus(dev)->reg8[reg] = value; } static __always_inline void pci_s_write_config16(pci_devfn_t dev, uint16_t reg, uint16_t value) { - pcicfg(dev)->reg16[reg / sizeof(uint16_t)] = value; + pci_map_bus(dev)->reg16[reg / sizeof(uint16_t)] = value; } static __always_inline void pci_s_write_config32(pci_devfn_t dev, uint16_t reg, uint32_t value) { - pcicfg(dev)->reg32[reg / sizeof(uint32_t)] = value; + pci_map_bus(dev)->reg32[reg / sizeof(uint32_t)] = value; } /* @@ -98,19 +104,19 @@ static __always_inline uint8_t *pci_mmio_config8_addr(pci_devfn_t dev, uint16_t reg) { - return (uint8_t *)&pcicfg(dev)->reg8[reg]; + return (uint8_t *)&pci_map_bus(dev)->reg8[reg]; } static __always_inline uint16_t *pci_mmio_config16_addr(pci_devfn_t dev, uint16_t reg) { - return (uint16_t *)&pcicfg(dev)->reg16[reg / sizeof(uint16_t)]; + return (uint16_t *)&pci_map_bus(dev)->reg16[reg / sizeof(uint16_t)]; } static __always_inline uint32_t *pci_mmio_config32_addr(pci_devfn_t dev, uint16_t reg) { - return (uint32_t *)&pcicfg(dev)->reg32[reg / sizeof(uint32_t)]; + return (uint32_t *)&pci_map_bus(dev)->reg32[reg / sizeof(uint32_t)]; } #endif /* _PCI_MMIO_CFG_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/59702 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id9517c5ec4fa6b7c7a34552bfdc6d509927f6730 Gerrit-Change-Number: 59702 Gerrit-PatchSet: 2 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: device/pci_device.c: Scan only one device for PCIe
by Hung-Te Lin (Code Review) 29 Nov '21

29 Nov '21

Hung-Te Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56788 ) Change subject: device/pci_device.c: Scan only one device for PCIe ...................................................................... device/pci_device.c: Scan only one device for PCIe Only scan one device if it's a PCIe downstream port. A PCIe downstream port normally leads to a link with only device 0 on it. As an optimization, scan only for device 0 in that case. Signed-off-by: Jianjun Wang <jianjun.wang(a)mediatek.com> Change-Id: Id184d03b33e1742b18efb3f11aa9b2f81fa03806 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56788 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> --- M src/device/pci_device.c M src/include/device/pci_def.h M src/include/device/pciexp.h 3 files changed, 36 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved diff --git a/src/device/pci_device.c b/src/device/pci_device.c index 4b5e73b..1075ef7 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -1204,6 +1204,30 @@ } /** + * A PCIe Downstream Port normally leads to a Link with only Device 0 on it + * (PCIe spec r5.0, sec 7.3.1). As an optimization, scan only for Device 0 in + * that situation. + * + * @param bus Pointer to the bus structure. + */ +static bool pci_bus_only_one_child(struct bus *bus) +{ + struct device *bridge = bus->dev; + u16 pcie_pos, pcie_flags_reg; + int pcie_type; + + pcie_pos = pci_find_capability(bridge, PCI_CAP_ID_PCIE); + if (!pcie_pos) + return false; + + pcie_flags_reg = pci_read_config16(bridge, pcie_pos + PCI_EXP_FLAGS); + + pcie_type = (pcie_flags_reg & PCI_EXP_FLAGS_TYPE) >> 4; + + return pciexp_is_downstream_port(pcie_type); +} + +/** * Scan a PCI bus. * * Determine the existence of devices and bridges on a PCI bus. If there are @@ -1232,6 +1256,9 @@ post_code(0x24); + if (pci_bus_only_one_child(bus)) + max_devfn = MIN(max_devfn, 0x07); + /* * Probe all devices/functions on this bus with some optimization for * non-existence and single function devices. diff --git a/src/include/device/pci_def.h b/src/include/device/pci_def.h index 22a5390..0611436 100644 --- a/src/include/device/pci_def.h +++ b/src/include/device/pci_def.h @@ -385,6 +385,7 @@ #define PCI_EXP_TYPE_UPSTREAM 0x5 /* Upstream Port */ #define PCI_EXP_TYPE_DOWNSTREAM 0x6 /* Downstream Port */ #define PCI_EXP_TYPE_PCI_BRIDGE 0x7 /* PCI/PCI-X Bridge */ +#define PCI_EXP_TYPE_PCIE_BRIDGE 0x8 /* PCI/PCI-X to PCIe Bridge */ #define PCI_EXP_FLAGS_SLOT 0x0100 /* Slot implemented */ #define PCI_EXP_FLAGS_IRQ 0x3e00 /* Interrupt message number */ #define PCI_EXP_DEVCAP 4 /* Device capabilities */ diff --git a/src/include/device/pciexp.h b/src/include/device/pciexp.h index 014fcb1..fbc769e 100644 --- a/src/include/device/pciexp.h +++ b/src/include/device/pciexp.h @@ -31,4 +31,12 @@ extern struct device_operations default_pciexp_hotplug_ops_bus; unsigned int pciexp_find_extended_cap(struct device *dev, unsigned int cap); + +static inline bool pciexp_is_downstream_port(int type) +{ + return type == PCI_EXP_TYPE_ROOT_PORT || + type == PCI_EXP_TYPE_DOWNSTREAM || + type == PCI_EXP_TYPE_PCIE_BRIDGE; +} + #endif /* DEVICE_PCIEXP_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/56788 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id184d03b33e1742b18efb3f11aa9b2f81fa03806 Gerrit-Change-Number: 56788 Gerrit-PatchSet: 5 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/mediatek: Flush cache before triggering EC reset
by Yu-Ping Wu (Code Review) 29 Nov '21

29 Nov '21

Attention is currently required from: Hung-Te Lin, Rex-BC Chen, Paul Menzel. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59683 ) Change subject: soc/mediatek: Flush cache before triggering EC reset ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59683 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1bd900beb4cc84f7121c5fb66907fa73b62517fa Gerrit-Change-Number: 59683 Gerrit-PatchSet: 5 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Mon, 29 Nov 2021 03:18:03 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/gimble: Swap TPM I2C with touchscreen I2C
by Zhuohao Lee (Code Review) 29 Nov '21

29 Nov '21

Attention is currently required from: YH Lin, Tim Wawrzynczak, Marco Chen, Mark Hsieh, Felix Held. Zhuohao Lee has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59580 ) Change subject: mb/google/brya/var/gimble: Swap TPM I2C with touchscreen I2C ...................................................................... Patch Set 7: Code-Review+1 (1 comment) File src/mainboard/google/brya/variants/gimble/overridetree.cb: https://review.coreboot.org/c/coreboot/+/59580/comment/0229c4c5_516b28fd PS6, Line 189: chip drivers/i2c/tpm : register "hid" = ""GOOG0005"" : register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A13_IRQ)" : device i2c 50 on end : end : end > Hi Zhuohao, […] Ok, It looks like the TPM driver isn't support the runtime configuration for the i2c bus. -- To view, visit https://review.coreboot.org/c/coreboot/+/59580 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I26d059a7ea5a3fdf00de260214c00d3bba9aa7f7 Gerrit-Change-Number: 59580 Gerrit-PatchSet: 7 Gerrit-Owner: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Marco Chen <marcochen(a)google.com> Gerrit-Reviewer: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anfernee Chen <anfernee_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Ariel Fang <ariel_fang(a)wistron.corp-partner.google.com> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-CC: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-CC: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Will Tsai <will_tsai(a)wistron.corp-partner.google.com> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Marco Chen <marcochen(a)google.com> Gerrit-Attention: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 29 Nov 2021 03:17:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Comment-In-Reply-To: Zhuohao Lee <zhuohao(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek: Add PCIe support
by Yu-Ping Wu (Code Review) 29 Nov '21

29 Nov '21

Attention is currently required from: Shelley Chen, Hung-Te Lin, Furquan Shaikh, Paul Menzel, Jianjun Wang. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56791 ) Change subject: soc/mediatek: Add PCIe support ...................................................................... Patch Set 4: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/56791/comment/a8b170f0_4f1069cb PS3, Line 10: support > supporting Ack https://review.coreboot.org/c/coreboot/+/56791/comment/8f4b73d9_55be4537 PS3, Line 11: > MT8195 Register Map V0.3-2, Chapter 3.18 PCIe controller (Page 1250). Please follow the style of https://review.coreboot.org/c/coreboot/+/58936/7/src/soc/mediatek/mt8186/pl… and add a comment at the beginning of pcie.c. > Should I add this information in commit message? Yes, please. > Build pass and boot up to kernel successfully via SSD. Please add TEST=Build pass and boot up to kernel successfully via SSD BUG=b:123 See CB:59569 as an example. File src/soc/mediatek/common/pcie.c: https://review.coreboot.org/c/coreboot/+/56791/comment/f79a4100_5af95f92 PS3, Line 85: static inline int mtk_fls(int x) > Agree, do you have any suggestions on which file this function should be added to? Maybe commonlib/bsd/include/commonlib/bsd/helpers.h? Note that there're other definitions you will need to handle to avoid breaking existing platforms: 1. commonlib/storage/sdhci.c: Change to use the definition in helpers.h 2. include/cpu/x86/mtrr.h: This is x86-specific, so you may need to either add an #ifdef for the common version, or merge that into the common version. Also, please do it in a separate patch. -- To view, visit https://review.coreboot.org/c/coreboot/+/56791 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib9b6adaafa20aeee136372ec9564273f86776da0 Gerrit-Change-Number: 56791 Gerrit-PatchSet: 4 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Comment-Date: Mon, 29 Nov 2021 03:15:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Comment-In-Reply-To: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek: Flush cache before triggering EC reset
by Rex-BC Chen (Code Review) 29 Nov '21

29 Nov '21

Attention is currently required from: Hung-Te Lin, Paul Menzel. Rex-BC Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59683 ) Change subject: soc/mediatek: Flush cache before triggering EC reset ...................................................................... Patch Set 5: (1 comment) Patchset: PS5: @yu-ping, could you help to CR+2 for this patch? Thanks! -- To view, visit https://review.coreboot.org/c/coreboot/+/59683 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1bd900beb4cc84f7121c5fb66907fa73b62517fa Gerrit-Change-Number: 59683 Gerrit-PatchSet: 5 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Mon, 29 Nov 2021 02:55:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/brask: Set PL and PsysPL
by Zhuohao Lee (Code Review) 29 Nov '21

29 Nov '21

Attention is currently required from: David Wu, Alan Huang. Zhuohao Lee has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59576 ) Change subject: mb/google/brya/var/brask: Set PL and PsysPL ...................................................................... Patch Set 2: (2 comments) File src/mainboard/google/brya/variants/brask/ramstage.c: https://review.coreboot.org/c/coreboot/+/59576/comment/09326dbe_3551884f PS2, Line 41: 13.52A This looks weird to me. The max current of the typec is 5A. How could this be larger than 5A? IIUC, the typec data should be coming from the EC. The psys_config below is only for the barrel jack. https://review.coreboot.org/c/coreboot/+/59576/comment/cd8aaae5_62090d2d PS2, Line 41: sholud should -- To view, visit https://review.coreboot.org/c/coreboot/+/59576 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9261902b8c892d0b866f326b24988039c1d30b56 Gerrit-Change-Number: 59576 Gerrit-PatchSet: 2 Gerrit-Owner: Alan Huang <alan-huang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Hou-hsun Lee <hou-hsun.lee(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Alan Huang <alan-huang(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Mon, 29 Nov 2021 02:33:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/variants/primus: update gpios for power consumption
by Malik Hsu (Code Review) 29 Nov '21

29 Nov '21

Malik Hsu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59563 ) Change subject: mb/google/brya/variants/primus: update gpios for power consumption ...................................................................... Patch Set 6: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/59563/comment/16cdb9a9_b15ee1f5 PS6, Line 13: and check power > How did you do it, and how much power was saved? The servo board is used on dut with the following command "dut-control -p $PORT -t $TIME $PWR_CMDS | grep "@@"" to check the value change. Please refer to the description on the BUG issue, thank you. -- To view, visit https://review.coreboot.org/c/coreboot/+/59563 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I753e41dec1825299e6cd437b5f67e2d957bc6148 Gerrit-Change-Number: 59563 Gerrit-PatchSet: 6 Gerrit-Owner: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Mon, 29 Nov 2021 02:18:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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coreboot-gerrit November 2021