coreboot-gerrit November 2021

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Change in coreboot[master]: sb/amd/cimx/sb800: Separate a section from fch.asl
by Angel Pons (Code Review) 28 Nov '21

28 Nov '21

Attention is currently required from: Kyösti Mälkki. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59178 ) Change subject: sb/amd/cimx/sb800: Separate a section from fch.asl ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59178 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3b3ff2fddc7d4db09903151bcb92e3e1b5dc7d69 Gerrit-Change-Number: 59178 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Sun, 28 Nov 2021 16:24:47 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mainboard/starlabs/labtop: Change TDP based on AC & DC state
by Sean Rhodes (Code Review) 28 Nov '21

28 Nov '21

Sean Rhodes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59707 ) Change subject: mainboard/starlabs/labtop: Change TDP based on AC & DC state ...................................................................... mainboard/starlabs/labtop: Change TDP based on AC & DC state Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: I149e7a5a48b6b4a3e5607c4399681602b04a097f --- M src/mainboard/starlabs/labtop/variants/tgl/Makefile.inc A src/mainboard/starlabs/labtop/variants/tgl/smihandler.c A src/mainboard/starlabs/labtop/variants/tgl/smihandler.h 3 files changed, 113 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/59707/1 diff --git a/src/mainboard/starlabs/labtop/variants/tgl/Makefile.inc b/src/mainboard/starlabs/labtop/variants/tgl/Makefile.inc index 2a505c3..7c50b7b7 100644 --- a/src/mainboard/starlabs/labtop/variants/tgl/Makefile.inc +++ b/src/mainboard/starlabs/labtop/variants/tgl/Makefile.inc @@ -7,3 +7,5 @@ ramstage-y += devtree.c ramstage-y += gpio.c ramstage-y += hda_verb.c + +smm-y += smihandler.c diff --git a/src/mainboard/starlabs/labtop/variants/tgl/smihandler.c b/src/mainboard/starlabs/labtop/variants/tgl/smihandler.c new file mode 100644 index 0000000..b6ccb38 --- /dev/null +++ b/src/mainboard/starlabs/labtop/variants/tgl/smihandler.c @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <chip.h> +#include <cpu/x86/smm.h> +#include <option.h> +#include <types.h> + +#include "smihandler.h" + +int mainboard_smi_apmc(u8 data) +{ + uint8_t val; + const uint8_t events[] = { + EC_SMI_AC_AND_DC, + EC_SMI_DC_BELOW_100, + EC_SMI_DC_BELOW_60, + EC_SMI_DC_BELOW_20, + EC_SMI_AC_ONLY, + } + + /* + * Update PL1 & PL2 based on AC & DC states + * and CMOS settings + */ + switch (get_uint_option("power_profile", 0)) { + case 1: + /* Use balanced_tdp */ + soc_conf_2core->tdp_pl1_override = 15; + soc_conf_4core->tdp_pl1_override = 15; + soc_conf_2core->tdp_pl2_override = 25; + soc_conf_4core->tdp_pl2_override = 25; + break; + case 2: + /* Use performance_tdp */ + soc_conf_2core->tdp_pl1_override = 28; + soc_conf_4core->tdp_pl1_override = 28; + soc_conf_2core->tdp_pl2_override = 40; + soc_conf_4core->tdp_pl2_override = 40; + break; + default: + /* Use power_saving_tdp */ + disable_turbo(); + soc_conf_2core->tdp_pl1_override = 15; + soc_conf_4core->tdp_pl1_override = 15; + soc_conf_2core->tdp_pl2_override = 15; + soc_conf_4core->tdp_pl2_override = 15; + break; + } +} diff --git a/src/mainboard/starlabs/labtop/variants/tgl/smihandler.h b/src/mainboard/starlabs/labtop/variants/tgl/smihandler.h new file mode 100644 index 0000000..dedea7c --- /dev/null +++ b/src/mainboard/starlabs/labtop/variants/tgl/smihandler.h @@ -0,0 +1,62 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* Events */ +#define EC_SMI_AC_AND_DC = 0xc6 +#define EC_SMI_DC_BELOW_100 = 0xc9 +#define EC_SMI_DC_BELOW_60 = 0xc8 +#define EC_SMI_DC_BELOW_20 = 0xc7 +#define EC_SMI_AC_ONLY = 0xca + +/* Performance */ +enum performance_tdp { + PL1_AC_AND_DC = 35 + PL2_AC_AND_DC = 64 + + PL1_DC_BELOW_100 = 35 + PL2_DC_BELOW_100 = 51 + + PL1_DC_BELOW_60 = 28 + PL2_DC_BELOW_60 = 35 + + PL1_DC_BELOW_20 = 15 + PL2_DC_BELOW_20 = 15 + + PL1_AC_ONLY = 28 + PL2_AC_ONLY = 40 +} + +/* Balanced */ +enum balanced_tdp { + PL1_AC_AND_DC = 15 + PL2_AC_AND_DC = 45 + + PL1_DC_BELOW_100 = 15 + PL2_DC_BELOW_100 = 35 + + PL1_DC_BELOW_60 = 15 + PL2_DC_BELOW_60 = 25 + + PL1_DC_BELOW_20 = 15 + PL2_DC_BELOW_20 = 15 + + PL1_AC_ONLY = 15 + PL2_AC_ONLY = 25 +} + +/* Power Saving */ +enum power_saving_tdp { + PL1_AC_AND_DC = 15 + PL2_AC_AND_DC = 35 + + PL1_DC_BELOW_100 = 15 + PL2_DC_BELOW_100 = 35 + + PL1_DC_BELOW_60 = 15 + PL2_DC_BELOW_60 = 25 + + PL1_DC_BELOW_20 = 15 + PL2_DC_BELOW_20 = 15 + + PL1_AC_ONLY = 15 + PL2_AC_ONLY = 25 +} -- To view, visit https://review.coreboot.org/c/coreboot/+/59707 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I149e7a5a48b6b4a3e5607c4399681602b04a097f Gerrit-Change-Number: 59707 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <admin(a)starlabs.systems> Gerrit-MessageType: newchange

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Change in coreboot[master]: security/intel/txt: Fix HEAP_ACM format depending on number of ACMs i...
by Angel Pons (Code Review) 28 Nov '21

28 Nov '21

Attention is currently required from: Michał Żygowski, Arthur Heymans, Patrick Rudolph. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59519 ) Change subject: security/intel/txt: Fix HEAP_ACM format depending on number of ACMs in CBFS ...................................................................... Patch Set 11: Code-Review+1 (1 comment) File src/security/intel/txt/ramstage.c: https://review.coreboot.org/c/coreboot/+/59519/comment/7d485e18_20a06eb6 PS11, Line 273: nit: drop one blank line -- To view, visit https://review.coreboot.org/c/coreboot/+/59519 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib0c37a66d96e1ca3fb4d3f665e3ad35c6f1c5c1e Gerrit-Change-Number: 59519 Gerrit-PatchSet: 11 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Sun, 28 Nov 2021 11:43:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: nb/intel/sandybridge/romstage.c: Configure DPR and initialize TXT
by Angel Pons (Code Review) 28 Nov '21

28 Nov '21

Attention is currently required from: Michał Żygowski, Patrick Rudolph. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59523 ) Change subject: nb/intel/sandybridge/romstage.c: Configure DPR and initialize TXT ...................................................................... Patch Set 11: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59523 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4b912f121593fa55c11813262f09be1a1055e950 Gerrit-Change-Number: 59523 Gerrit-PatchSet: 11 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Sun, 28 Nov 2021 11:37:41 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mainboard/starlabs/labtop: Change logic for CMOS handling
by Sean Rhodes (Code Review) 28 Nov '21

28 Nov '21

Sean Rhodes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59706 ) Change subject: mainboard/starlabs/labtop: Change logic for CMOS handling ...................................................................... mainboard/starlabs/labtop: Change logic for CMOS handling Remove if statement for devices that are disabled or enabled via CMOS settings. Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: Ie4c479bad027598751209929514f2a2643090178 --- M src/mainboard/starlabs/labtop/variants/tgl/devtree.c 1 file changed, 2 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/59706/1 diff --git a/src/mainboard/starlabs/labtop/variants/tgl/devtree.c b/src/mainboard/starlabs/labtop/variants/tgl/devtree.c index 1d35189..ee5fdd3 100644 --- a/src/mainboard/starlabs/labtop/variants/tgl/devtree.c +++ b/src/mainboard/starlabs/labtop/variants/tgl/devtree.c @@ -44,12 +44,10 @@ } /* Enable/Disable Wireless based on CMOS settings */ - if (get_uint_option("wireless", 1) == 0) - nic_dev->enabled = 0; + nic_dev->enabled = get_uint_option("wireless", 1); /* Enable/Disable Webcam based on CMOS settings */ - if (get_uint_option("webcam", 1) == 0) - cfg->usb2_ports[3].enable = 0; + cfg->usb2_ports[3].enable = get_uint_option("webcam", 1); /* Enable/Disable Thunderbolt based on CMOS settings */ cfg->UsbTcPortEn = get_uint_option("thunderbolt", 1); -- To view, visit https://review.coreboot.org/c/coreboot/+/59706 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie4c479bad027598751209929514f2a2643090178 Gerrit-Change-Number: 59706 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <admin(a)starlabs.systems> Gerrit-MessageType: newchange

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Change in coreboot[master]: device/pci_device.c: Scan only one device for PCIe
by Yu-Ping Wu (Code Review) 28 Nov '21

28 Nov '21

Attention is currently required from: Shelley Chen, Furquan Shaikh, Paul Menzel, Jianjun Wang. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56788 ) Change subject: device/pci_device.c: Scan only one device for PCIe ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/56788 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id184d03b33e1742b18efb3f11aa9b2f81fa03806 Gerrit-Change-Number: 56788 Gerrit-PatchSet: 4 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Comment-Date: Sun, 28 Nov 2021 10:20:25 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mainboard/starlabs/labtop: Enable/disable Thunderbolt based on CMOS
by Sean Rhodes (Code Review) 28 Nov '21

28 Nov '21

Sean Rhodes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59705 ) Change subject: mainboard/starlabs/labtop: Enable/disable Thunderbolt based on CMOS ...................................................................... mainboard/starlabs/labtop: Enable/disable Thunderbolt based on CMOS Enable or disable Thunderbolt and related settings based on CMOS value of `thunderbolt`. Changes TcssD3ColdDisable, TcssXhciEn, and UsbTcPortEn. Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: Ibadc7464831242ae51982610b410ccf0a6811edd --- M src/mainboard/starlabs/labtop/cmos.default M src/mainboard/starlabs/labtop/cmos.layout M src/mainboard/starlabs/labtop/variants/tgl/devicetree.cb M src/mainboard/starlabs/labtop/variants/tgl/devtree.c 4 files changed, 7 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/59705/1 diff --git a/src/mainboard/starlabs/labtop/cmos.default b/src/mainboard/starlabs/labtop/cmos.default index b4b2d26..589189f 100644 --- a/src/mainboard/starlabs/labtop/cmos.default +++ b/src/mainboard/starlabs/labtop/cmos.default @@ -14,6 +14,7 @@ microphone=Enable legacy_8254_timer=Enable usb_always_on=Disable +thunderbolt=Disable # EC kbl_timeout=30 seconds fn_ctrl_swap=Disable diff --git a/src/mainboard/starlabs/labtop/cmos.layout b/src/mainboard/starlabs/labtop/cmos.layout index 2601e98..f9caa18 100644 --- a/src/mainboard/starlabs/labtop/cmos.layout +++ b/src/mainboard/starlabs/labtop/cmos.layout @@ -30,6 +30,7 @@ 520 1 e 1 microphone 528 1 e 1 legacy_8254_timer 536 1 e 1 usb_always_on +542 1 e 1 thunderbolt # coreboot config options: EC 600 3 e 4 kbl_timeout diff --git a/src/mainboard/starlabs/labtop/variants/tgl/devicetree.cb b/src/mainboard/starlabs/labtop/variants/tgl/devicetree.cb index 5c55dce..40982a5 100644 --- a/src/mainboard/starlabs/labtop/variants/tgl/devicetree.cb +++ b/src/mainboard/starlabs/labtop/variants/tgl/devicetree.cb @@ -22,7 +22,6 @@ register "enable_c6dram" = "1" register "HeciEnabled" = "1" register "SaGv" = "SaGv_Enabled" - register "TcssD3ColdDisable" = "1" # FSP Silicon # Serial I/O @@ -89,8 +88,6 @@ device pci 09.0 off end # NPK device pci 0a.0 off end # Crash-log SRAM device pci 0d.0 on # USB xHCI - register "UsbTcPortEn" = "1" - register "TcssXhciEn" = "1" register "TcssAuxOri" = "0" end device pci 0d.1 off end # USB xDCI (OTG) diff --git a/src/mainboard/starlabs/labtop/variants/tgl/devtree.c b/src/mainboard/starlabs/labtop/variants/tgl/devtree.c index 034877c..1d35189 100644 --- a/src/mainboard/starlabs/labtop/variants/tgl/devtree.c +++ b/src/mainboard/starlabs/labtop/variants/tgl/devtree.c @@ -50,4 +50,9 @@ /* Enable/Disable Webcam based on CMOS settings */ if (get_uint_option("webcam", 1) == 0) cfg->usb2_ports[3].enable = 0; + + /* Enable/Disable Thunderbolt based on CMOS settings */ + cfg->UsbTcPortEn = get_uint_option("thunderbolt", 1); + cfg->TcssXhciEn = get_uint_option("thunderbolt", 1); + cfg->TcssD3ColdDisable = get_uint_option("thunderbolt", 1); } -- To view, visit https://review.coreboot.org/c/coreboot/+/59705 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibadc7464831242ae51982610b410ccf0a6811edd Gerrit-Change-Number: 59705 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <admin(a)starlabs.systems> Gerrit-MessageType: newchange

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Change in coreboot[master]: pci_mmio_cfg: Rename pcicfg to pci_map_bus
by Yu-Ping Wu (Code Review) 28 Nov '21

28 Nov '21

Attention is currently required from: Hung-Te Lin, Shelley Chen, Jianjun Wang. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59702 ) Change subject: pci_mmio_cfg: Rename pcicfg to pci_map_bus ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59702 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id9517c5ec4fa6b7c7a34552bfdc6d509927f6730 Gerrit-Change-Number: 59702 Gerrit-PatchSet: 1 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Comment-Date: Sun, 28 Nov 2021 06:57:20 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/smmstore: Remove SMMSTORE_IN_CBFS
by Patrick Georgi (Code Review) 27 Nov '21

27 Nov '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59680 ) Change subject: drivers/smmstore: Remove SMMSTORE_IN_CBFS ...................................................................... drivers/smmstore: Remove SMMSTORE_IN_CBFS The SMMSTORE_IN_CBFS option was just meant as a workaround for an attempt to backport SMMSTORE into older Chromebooks that never actually happened. All current and future users of coreboot should be using SMMSTORE in an FMAP region. The APIs needed for SMMSTORE_IN_CBFS clash with the CBFS rdev isolation needed for CBFS_VERIFICATION, so let's just get rid of it. Signed-off-by: Julius Werner <jwerner(a)chromium.org> Change-Id: Ia0604a4ffd20b46774631d585925311b65d5a0e9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59680 Reviewed-by: Patrick Georgi <patrick(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/drivers/smmstore/Kconfig M src/drivers/smmstore/store.c 2 files changed, 7 insertions(+), 38 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, approved Arthur Heymans: Looks good to me, approved Angel Pons: Looks good to me, approved diff --git a/src/drivers/smmstore/Kconfig b/src/drivers/smmstore/Kconfig index 13b7312..3e20e3e 100644 --- a/src/drivers/smmstore/Kconfig +++ b/src/drivers/smmstore/Kconfig @@ -19,27 +19,10 @@ By using version 2 you cannot make use of software that expects a version 1 SMMSTORE. -config SMMSTORE_IN_CBFS - bool - default n - help - Select this if you want to add an SMMSTORE region to a - cbfsfile in a cbfs FMAP region - if SMMSTORE -config SMMSTORE_REGION - string "fmap region in which SMM store file is kept" if SMMSTORE_IN_CBFS - default "RW_LEGACY" if CHROMEOS && SMMSTORE_IN_CBFS - default "COREBOOT" if SMMSTORE_IN_CBFS - default "SMMSTORE" - -config SMMSTORE_FILENAME - string "SMM store file name" if SMMSTORE_IN_CBFS - default "smm_store" config SMMSTORE_SIZE hex "size of the SMMSTORE FMAP region" - depends on !SMMSTORE_IN_CBFS default 0x40000 help Sets the size of the default SMMSTORE FMAP region. diff --git a/src/drivers/smmstore/store.c b/src/drivers/smmstore/store.c index a12cd58..24e8a88 100644 --- a/src/drivers/smmstore/store.c +++ b/src/drivers/smmstore/store.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <boot_device.h> -#include <cbfs.h> #include <fmap.h> #include <commonlib/helpers.h> #include <commonlib/region.h> @@ -9,6 +8,8 @@ #include <smmstore.h> #include <types.h> +#define SMMSTORE_REGION "SMMSTORE" + /* * The region format is still not finalized, but so far it looks like this: * ( @@ -33,26 +34,11 @@ static enum cb_err lookup_store_region(struct region *region) { - if (CONFIG(SMMSTORE_IN_CBFS)) { - struct cbfsf file; - if (cbfs_locate_file_in_region(&file, - CONFIG_SMMSTORE_REGION, - CONFIG_SMMSTORE_FILENAME, NULL) < 0) { - printk(BIOS_WARNING, - "smm store: Unable to find SMM store file in region '%s'\n", - CONFIG_SMMSTORE_REGION); - return CB_ERR; - } - struct region_device rdev; - cbfs_file_data(&rdev, &file); - *region = *region_device_region(&rdev); - } else { - if (fmap_locate_area(CONFIG_SMMSTORE_REGION, region)) { - printk(BIOS_WARNING, - "smm store: Unable to find SMM store FMAP region '%s'\n", - CONFIG_SMMSTORE_REGION); - return CB_ERR; - } + if (fmap_locate_area(SMMSTORE_REGION, region)) { + printk(BIOS_WARNING, + "smm store: Unable to find SMM store FMAP region '%s'\n", + SMMSTORE_REGION); + return CB_ERR; } return CB_SUCCESS; -- To view, visit https://review.coreboot.org/c/coreboot/+/59680 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia0604a4ffd20b46774631d585925311b65d5a0e9 Gerrit-Change-Number: 59680 Gerrit-PatchSet: 3 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/common Add support for CSE IOM/NPHY sub-parition update
by Krishna P Bhat D (Code Review) 27 Nov '21

27 Nov '21

Attention is currently required from: Tim Wawrzynczak, Rizwan Qureshi, Sridhar Siricilla, Nick Vaccaro, Kane Chen. Krishna P Bhat D has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59685 ) Change subject: soc/intel/common Add support for CSE IOM/NPHY sub-parition update ...................................................................... Patch Set 9: (1 comment) This change is ready for review. File src/soc/intel/common/block/cse/cse_lite.c: https://review.coreboot.org/c/coreboot/+/59685/comment/2364df02_ed13561c PS4, Line 970: cpu_get_cpuid > Should SoC API determine IOM/NPHY Update ? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/59685 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7c0cda51314c4f722f5432486a43e19b46f4b240 Gerrit-Change-Number: 59685 Gerrit-PatchSet: 9 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Kane Chen <kane.chen(a)intel.com> Gerrit-Comment-Date: Sat, 27 Nov 2021 18:12:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: comment

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coreboot-gerrit November 2021