coreboot-gerrit November 2021

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Change in coreboot[master]: soc/amd/stoneyridge/psp: use PSP_MAILBOX_BAR define
by Paul Menzel (Code Review) 27 Nov '21

27 Nov '21

Attention is currently required from: Marshall Dawson, Felix Held. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59700 ) Change subject: soc/amd/stoneyridge/psp: use PSP_MAILBOX_BAR define ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/59700 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8658b674b9adea85dfc71d7036ccf3ae17464b58 Gerrit-Change-Number: 59700 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Sat, 27 Nov 2021 14:55:05 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/stoneyridge/psp: move soc_get_mbox_address to common psp_gen1
by Paul Menzel (Code Review) 27 Nov '21

27 Nov '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Felix Held. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59701 ) Change subject: soc/amd/stoneyridge/psp: move soc_get_mbox_address to common psp_gen1 ...................................................................... Patch Set 1: Code-Review+1 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/59701/comment/b33a91b2_08f70f95 PS1, Line 9: one only the only? -- To view, visit https://review.coreboot.org/c/coreboot/+/59701 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I78126cb710a6ee674b58b35c8294685a5965ecd6 Gerrit-Change-Number: 59701 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Sat, 27 Nov 2021 14:54:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: [WIP] mb/lippert/frontrunner-af: Use common cimx/sb800 fch.asl
by Kyösti Mälkki (Code Review) 27 Nov '21

27 Nov '21

Kyösti Mälkki has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/59181 ) Change subject: [WIP] mb/lippert/frontrunner-af: Use common cimx/sb800 fch.asl ...................................................................... [WIP] mb/lippert/frontrunner-af: Use common cimx/sb800 fch.asl Change-Id: I0516d50b079c8f60312329eef36ca17ea3c94468 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/lippert/frontrunner-af/dsdt.asl M src/southbridge/amd/cimx/sb800/acpi/fch.asl 2 files changed, 8 insertions(+), 133 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/59181/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59181 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0516d50b079c8f60312329eef36ca17ea3c94468 Gerrit-Change-Number: 59181 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/lippert/frontrunner-af: Use common cpu/ and nb/ ASL files
by Kyösti Mälkki (Code Review) 27 Nov '21

27 Nov '21

Attention is currently required from: Kyösti Mälkki. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/50658 to look at the new patch set (#4). Change subject: mb/lippert/frontrunner-af: Use common cpu/ and nb/ ASL files ...................................................................... mb/lippert/frontrunner-af: Use common cpu/ and nb/ ASL files There are no quad-core CPU models with fam4, \_SB.C002 and .C003 get removed from ASL. Change-Id: I96df5b3f93c2dd6a05d5693069b991ca01f71d73 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/lippert/frontrunner-af/dsdt.asl 1 file changed, 4 insertions(+), 112 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/50658/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/50658 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I96df5b3f93c2dd6a05d5693069b991ca01f71d73 Gerrit-Change-Number: 50658 Gerrit-PatchSet: 4 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: lippert/frontrunner-af: Use common cimx/sb800 ASL
by Kyösti Mälkki (Code Review) 27 Nov '21

27 Nov '21

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/50657 to look at the new patch set (#4). Change subject: lippert/frontrunner-af: Use common cimx/sb800 ASL ...................................................................... lippert/frontrunner-af: Use common cimx/sb800 ASL Change-Id: Ia65b1873f1d184b8b8c64a61a26820ae0900437d Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/lippert/frontrunner-af/dsdt.asl M src/southbridge/amd/cimx/sb800/acpi/lpc.asl 2 files changed, 3 insertions(+), 125 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/50657/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/50657 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia65b1873f1d184b8b8c64a61a26820ae0900437d Gerrit-Change-Number: 50657 Gerrit-PatchSet: 4 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: lippert/frontrunner-af: Fix PCI devices ASL
by Kyösti Mälkki (Code Review) 27 Nov '21

27 Nov '21

Kyösti Mälkki has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/59179 ) Change subject: lippert/frontrunner-af: Fix PCI devices ASL ...................................................................... lippert/frontrunner-af: Fix PCI devices ASL There was a duplicate PCI 0:14.4 device in ASL. Only keep one. There are no PCI devices 0:2.0 or 0:3.0 on fam14 northbridge for graphics. There are no PCIe root ports 0:9.0 or 0:a.0. Change-Id: Ifa8abb851f8ae4863b2c6d52224d287fd272048d Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/lippert/frontrunner-af/acpi/gpe.asl M src/mainboard/lippert/frontrunner-af/dsdt.asl 2 files changed, 11 insertions(+), 43 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/59179/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59179 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifa8abb851f8ae4863b2c6d52224d287fd272048d Gerrit-Change-Number: 59179 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/dell/optiplex_9010/romstage.c: Add interrupt routing map
by Michał Żygowski (Code Review) 27 Nov '21

27 Nov '21

Michał Żygowski has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59525 ) Change subject: mb/dell/optiplex_9010/romstage.c: Add interrupt routing map ...................................................................... mb/dell/optiplex_9010/romstage.c: Add interrupt routing map Dumped using inteltool from the Dell BIOS version A30. Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: Ifdc41a1e6627b68813fb264aed7e30df58fc6d54 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59525 Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/dell/optiplex_9010/romstage.c 1 file changed, 13 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Angel Pons: Looks good to me, approved diff --git a/src/mainboard/dell/optiplex_9010/romstage.c b/src/mainboard/dell/optiplex_9010/romstage.c index 36af6e4..889b06d 100644 --- a/src/mainboard/dell/optiplex_9010/romstage.c +++ b/src/mainboard/dell/optiplex_9010/romstage.c @@ -5,12 +5,25 @@ #include <console/console.h> #include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/raminit_native.h> +#include <southbridge/intel/common/rcba.h> #include <southbridge/intel/bd82x6x/pch.h> #include <superio/smsc/sch5545/sch5545.h> #include <superio/smsc/sch5545/sch5545_emi.h> #include "sch5545_ec.h" +void mainboard_late_rcba_config(void) +{ + DIR_ROUTE(D31IR, PIRQA, PIRQD, PIRQC, PIRQA); + DIR_ROUTE(D29IR, PIRQH, PIRQD, PIRQA, PIRQC); + DIR_ROUTE(D28IR, PIRQA, PIRQB, PIRQC, PIRQD); + DIR_ROUTE(D27IR, PIRQG, PIRQB, PIRQC, PIRQD); + DIR_ROUTE(D26IR, PIRQA, PIRQF, PIRQC, PIRQD); + DIR_ROUTE(D25IR, PIRQE, PIRQF, PIRQG, PIRQH); + DIR_ROUTE(D22IR, PIRQA, PIRQD, PIRQC, PIRQB); + DIR_ROUTE(D20IR, PIRQA, PIRQB, PIRQC, PIRQD); +} + void mainboard_early_init(int s3resume) { uint16_t ec_fw_version; -- To view, visit https://review.coreboot.org/c/coreboot/+/59525 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifdc41a1e6627b68813fb264aed7e30df58fc6d54 Gerrit-Change-Number: 59525 Gerrit-PatchSet: 5 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: superio/smsc/sch5545: Disable PS/2 lines isolation during init
by Michał Żygowski (Code Review) 27 Nov '21

27 Nov '21

Michał Żygowski has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59673 ) Change subject: superio/smsc/sch5545: Disable PS/2 lines isolation during init ...................................................................... superio/smsc/sch5545: Disable PS/2 lines isolation during init Disable PS/2 data and clock isolation in order to properly initialize the PS/2 keyboard and mouse in payload/OS. These bits are set by OS via ACPI and can survive S5 state. It is necessary to clear them after an ungraceful shutdown in order to perform PS/2 controller initialization e.g. in SeaBIOS. TEST=PS/2 keyboard can always be successfully initialized in SeaBIOS on Dell OptiPlex 9010 Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: Iac6be095c996b357b5d4e8d75199f94a89bf73e9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59673 Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/superio/smsc/sch5545/superio.c 1 file changed, 6 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/superio/smsc/sch5545/superio.c b/src/superio/smsc/sch5545/superio.c index b6e5308..2fe5d03 100644 --- a/src/superio/smsc/sch5545/superio.c +++ b/src/superio/smsc/sch5545/superio.c @@ -62,6 +62,12 @@ switch (dev->path.pnp.device) { case SCH5545_LDN_KBC: + pnp_enter_conf_mode(dev); + pnp_set_logical_device(dev); + /* Disable PS/2 clock and data isolation */ + pnp_unset_and_set_config(dev, 0xf0, + SCH5545_KBD_ISOLATION | SCH5545_MOUSE_ISOLATION, 0); + pnp_exit_conf_mode(dev); pc_keyboard_init(NO_AUX_DEVICE); break; case SCH5545_LDN_LPC: -- To view, visit https://review.coreboot.org/c/coreboot/+/59673 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iac6be095c996b357b5d4e8d75199f94a89bf73e9 Gerrit-Change-Number: 59673 Gerrit-PatchSet: 3 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: superio/smsc/sch5545: Clear PMEs in the early init
by Michał Żygowski (Code Review) 27 Nov '21

27 Nov '21

Michał Żygowski has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59524 ) Change subject: superio/smsc/sch5545: Clear PMEs in the early init ...................................................................... superio/smsc/sch5545: Clear PMEs in the early init Disable PMEs and clear global PME status to avoid undesired wakeups or hangs in later stages. These bits are set by OS via ACPI can survive S5 state so it is necessary to set them back to defaults after an ungraceful shutdown. TEST=Dell OptiPlex 9010 does not hang anymore after ungraceful shutdown when configuring GPE0_EN register in southbridge LPC init Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I790cac3ce1101565b64ed54d9c6b50f5e9aa4cf6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59524 Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/superio/smsc/sch5545/sch5545_early_init.c 1 file changed, 7 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/superio/smsc/sch5545/sch5545_early_init.c b/src/superio/smsc/sch5545/sch5545_early_init.c index ed4fa53..d77ed0d 100644 --- a/src/superio/smsc/sch5545/sch5545_early_init.c +++ b/src/superio/smsc/sch5545/sch5545_early_init.c @@ -100,6 +100,13 @@ sch5545_set_led(SCH5545_RUNTIME_REG_BASE, SCH5545_LED_COLOR_GREEN, SCH5545_LED_BLINK_ON); + /* + * Clear global PME status and disable PME generation to avoid + * unexpected wakeups or hangs. OS will re-enable it via ACPI. + */ + outb(0, SCH5545_RUNTIME_REG_BASE + SCH5545_RR_PME_EN); + outb(1, SCH5545_RUNTIME_REG_BASE + SCH5545_RR_PME_STS); + /* Configure EMI */ dev = PNP_DEV(port, SCH5545_LDN_LPC); pnp_set_logical_device(dev); -- To view, visit https://review.coreboot.org/c/coreboot/+/59524 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I790cac3ce1101565b64ed54d9c6b50f5e9aa4cf6 Gerrit-Change-Number: 59524 Gerrit-PatchSet: 6 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: security/intel/txt: Fix GETSEC checks in romstage
by Michał Żygowski (Code Review) 27 Nov '21

27 Nov '21

Michał Żygowski has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59520 ) Change subject: security/intel/txt: Fix GETSEC checks in romstage ...................................................................... security/intel/txt: Fix GETSEC checks in romstage IA32_FEATURE_CONTROL does not need to be checked by BIOS, in fact these bits are needed only by SENTER and SINIT ACM. ACM ENTERACCS does not check these bits according to Intel SDM. Also noticed that the lock bit of IA32_FEATURE_CONTROL cannot be cleared by issuing neither global reset nor full reset on Sandybridge/Ivybridge platforms which results in a reset loop. However, check the IA32_FEATURE_CONTROL SENTER bits in ramstage where the register is properly set on all cores already. TEST=Run ACM SCLEAN on Dell OptiPlex 9010 with i7-3770/Q77 Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: Ie9103041498f557b85019a56e1252090a4fcd0c9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59520 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/security/intel/txt/getsec.c M src/security/intel/txt/romstage.c 2 files changed, 31 insertions(+), 11 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Rudolph: Looks good to me, approved diff --git a/src/security/intel/txt/getsec.c b/src/security/intel/txt/getsec.c index af9b7bb..cd22927 100644 --- a/src/security/intel/txt/getsec.c +++ b/src/security/intel/txt/getsec.c @@ -9,6 +9,7 @@ #include <cpu/x86/mp.h> #include <cpu/x86/msr.h> #include <types.h> +#include <rules.h> #include "txt_register.h" #include "txt_getsec.h" @@ -24,16 +25,26 @@ /* * Check if SMX and VMX is supported by CPU. */ - if (!(ecx & CPUID_SMX) || !(ecx & CPUID_VMX)) + if (!(ecx & CPUID_SMX) || !(ecx & CPUID_VMX)) { + printk(BIOS_ERR, "SMX/VMX not supported by CPU\n"); return false; - + } /* - * Check if SMX, VMX and GetSec instructions haven't been disabled. + * This requirement is not needed for ENTERACCS, but for SENTER (see SDM). + * Skip check in romstage because IA32_FEATURE_CONTROL cannot be unlocked + * even after a global reset e.g. on Sandy/IvyBridge. However the register + * gets set properly in ramstage where all CPUs are already initialized. */ - msr_t msr = rdmsr(IA32_FEATURE_CONTROL); - if ((msr.lo & 0xff06) != 0xff06) - return false; - + if (!ENV_ROMSTAGE_OR_BEFORE) { + /* + * Check if SMX, VMX and GetSec instructions haven't been disabled. + */ + msr_t msr = rdmsr(IA32_FEATURE_CONTROL); + if ((msr.lo & 0xff06) != 0xff06) { + printk(BIOS_ERR, "GETSEC not enabled in IA32_FEATURE_CONTROL MSR\n"); + return false; + } + } /* * Enable SMX. Required to execute GetSec instruction. * Chapter 2.2.4.3 diff --git a/src/security/intel/txt/romstage.c b/src/security/intel/txt/romstage.c index 63db10f..98308b7 100644 --- a/src/security/intel/txt/romstage.c +++ b/src/security/intel/txt/romstage.c @@ -5,6 +5,7 @@ #include <cf9_reset.h> #include <console/console.h> #include <cpu/intel/common/common.h> +#include <cpu/x86/cr.h> #include <cpu/x86/msr.h> #include <southbridge/intel/common/pmbase.h> #include <timer.h> @@ -83,14 +84,22 @@ void intel_txt_romstage_init(void) { /* Bail early if the CPU doesn't support TXT */ - if (!is_txt_cpu()) + if (!is_txt_cpu()) { + printk(BIOS_ERR, "TEE-TXT: CPU not TXT capable.\n"); return; + } - /* We need to use GETSEC here, so enable it */ - enable_getsec_or_reset(); + /* + * We need to use GETSEC here, so enable it. + * CR4_SMXE is all we need to be able to call GETSEC[CAPABILITIES] + * or GETSEC[ENTERACCS] for SCLEAN. + */ + write_cr4(read_cr4() | CR4_SMXE); - if (!is_txt_chipset()) + if (!is_txt_chipset()) { + printk(BIOS_ERR, "TEE-TXT: Chipset not TXT capable.\n"); return; + } const uint8_t txt_ests = read8((void *)TXT_ESTS); 2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/59520 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie9103041498f557b85019a56e1252090a4fcd0c9 Gerrit-Change-Number: 59520 Gerrit-PatchSet: 11 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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coreboot-gerrit November 2021