coreboot-gerrit November 2021

coreboot-gerrit@coreboot.org

1 participants
6394 discussions

Change in coreboot[master]: src/arch/ppc64/*: pass FDT address to payload
by Sergii Dmytruk (Code Review) 27 Nov '21

27 Nov '21

Attention is currently required from: Sergii Dmytruk, Timothy Pearson, Ron Minnich. Hello build bot (Jenkins), Arthur Heymans, Krystian Hebel, Timothy Pearson, Ron Minnich, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/57084 to look at the new patch set (#22). Change subject: src/arch/ppc64/*: pass FDT address to payload ...................................................................... src/arch/ppc64/*: pass FDT address to payload It's available in %r3 in bootblock and needs to be passed to payload in %r27. We use one of two hypervisor's special registers as a buffer, which aren't used for anything by the code. Change-Id: I0911f4b534c6f8cacfa057a5bad7576fec711637 Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> --- M src/arch/ppc64/bootblock_crt0.S M src/include/cpu/power/spr.h M src/mainboard/emulation/qemu-power9/Makefile.inc A src/mainboard/emulation/qemu-power9/ramstage.c 4 files changed, 32 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/57084/22 -- To view, visit https://review.coreboot.org/c/coreboot/+/57084 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0911f4b534c6f8cacfa057a5bad7576fec711637 Gerrit-Change-Number: 57084 Gerrit-PatchSet: 22 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Ron Minnich <rminnich(a)gmail.com> Gerrit-Reviewer: Timothy Pearson <tpearson(a)raptorengineering.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Attention: Timothy Pearson <tpearson(a)raptorengineering.com> Gerrit-Attention: Ron Minnich <rminnich(a)gmail.com> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: src/arch/ppc64/*: pass FDT address to payload
by Krystian Hebel (Code Review) 27 Nov '21

27 Nov '21

Attention is currently required from: Sergii Dmytruk, Timothy Pearson, Ron Minnich. Krystian Hebel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57084 ) Change subject: src/arch/ppc64/*: pass FDT address to payload ...................................................................... Patch Set 21: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/57084/comment/920f9cfb_95c89556 PS21, Line 10: %r17. We use one of two hypervisor's special registers as a buffer, %r27? -- To view, visit https://review.coreboot.org/c/coreboot/+/57084 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0911f4b534c6f8cacfa057a5bad7576fec711637 Gerrit-Change-Number: 57084 Gerrit-PatchSet: 21 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Ron Minnich <rminnich(a)gmail.com> Gerrit-Reviewer: Timothy Pearson <tpearson(a)raptorengineering.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Attention: Timothy Pearson <tpearson(a)raptorengineering.com> Gerrit-Attention: Ron Minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Sat, 27 Nov 2021 09:39:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/mediatek: Add PCIe support
by Jianjun Wang (Code Review) 27 Nov '21

27 Nov '21

Attention is currently required from: Shelley Chen, Hung-Te Lin, Furquan Shaikh, Paul Menzel, Yu-Ping Wu. Jianjun Wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56791 ) Change subject: soc/mediatek: Add PCIe support ...................................................................... Patch Set 4: (1 comment) File src/soc/mediatek/common/pcie.c: https://review.coreboot.org/c/coreboot/+/56791/comment/e124c385_898f275e PS2, Line 329: mtk_pcie_gen3_probe > A lot of this code seems redundant as the common drivers in coreboot already provide support for: […] Thanks for your suggestion, I removed most of these redundant functions, but there are still some resource allocation functions that I need to add in this code: 1. Use mtk_pcie_dev_assign_resource to maintain the usage of the MMIO space, in this platform, we have a 64MBytes MMIO space starting from 0x2000_0000; 2. Use mtk_pcie_bridge_assign_resources to update the resource base/size information of the bridge, let the config space of the root port can get the correct memory/io base/limit. -- To view, visit https://review.coreboot.org/c/coreboot/+/56791 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib9b6adaafa20aeee136372ec9564273f86776da0 Gerrit-Change-Number: 56791 Gerrit-PatchSet: 4 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Sat, 27 Nov 2021 07:39:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/mediatek: Add PCIe support
by Jianjun Wang (Code Review) 27 Nov '21

27 Nov '21

1 0

Change in coreboot[master]: soc/mediatek: Add PCIe support
by Jianjun Wang (Code Review) 27 Nov '21

27 Nov '21

Attention is currently required from: Shelley Chen, Hung-Te Lin, Paul Menzel, Yu-Ping Wu. Jianjun Wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56791 ) Change subject: soc/mediatek: Add PCIe support ...................................................................... Patch Set 4: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/56791/comment/ef72d5c5_5d5ed60c PS3, Line 11: > 1. What datasheets (name, revision and section) were used to implement this? […] >> 1. What datasheets (name, revision and section) were used to implement this? MT8195 Register Map V0.3-2, Chapter 3.18 PCIe controller (Page 1250). Should I add this information in commit message? >> 2. How has this been tested? Build pass and boot up to kernel successfully via SSD. File src/include/device/pci_mmio_cfg.h: https://review.coreboot.org/c/coreboot/+/56791/comment/e2ecd297_6e5f6ed0 PS3, Line 50: pcicfg > Okay, but please do it in a separate patch. Please also move the change in this file to that patch. Done File src/soc/mediatek/common/pcie.c: https://review.coreboot.org/c/coreboot/+/56791/comment/1981ba29_cd30cdf8 PS3, Line 85: static inline int mtk_fls(int x) > Should this be a common function? Agree, do you have any suggestions on which file this function should be added to? -- To view, visit https://review.coreboot.org/c/coreboot/+/56791 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib9b6adaafa20aeee136372ec9564273f86776da0 Gerrit-Change-Number: 56791 Gerrit-PatchSet: 4 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Sat, 27 Nov 2021 07:12:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Comment-In-Reply-To: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: device/pci_device.c: Scan only one device for PCIe
by Jianjun Wang (Code Review) 27 Nov '21

27 Nov '21

Attention is currently required from: Shelley Chen, Furquan Shaikh, Paul Menzel, Yu-Ping Wu. Jianjun Wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56788 ) Change subject: device/pci_device.c: Scan only one device for PCIe ...................................................................... Patch Set 4: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/56788/comment/51c07311_b7f2b461 PS3, Line 11: A PCIe downstream port normally leads to a link with : only device 0 on it. As an optimization, scan only for : device 0 in that case. > Please reflow the text to match line length limit (72 chars). Done File src/device/pci_device.c: https://review.coreboot.org/c/coreboot/+/56788/comment/2080e08e_cf2248ed PS3, Line 1207: A PCIe Downstream Port normally leads to a Link with only Device : * 0 on it (PCIe spec r5.0, sec 7.3.1). As an optimization, scan : * only for Device 0 in that situation. > Please reflow the text. Done https://review.coreboot.org/c/coreboot/+/56788/comment/291fa4b5_d26d0a3d PS3, Line 1260: 0x07 > MIN(max_devfn, 0x07), as the passed max_devfn might be smaller than 0x07. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/56788 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id184d03b33e1742b18efb3f11aa9b2f81fa03806 Gerrit-Change-Number: 56788 Gerrit-PatchSet: 4 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Sat, 27 Nov 2021 07:00:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: pci_mmio_cfg: Rename pcicfg to pci_map_bus
by Jianjun Wang (Code Review) 27 Nov '21

27 Nov '21

Jianjun Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59702 ) Change subject: pci_mmio_cfg: Rename pcicfg to pci_map_bus ...................................................................... pci_mmio_cfg: Rename pcicfg to pci_map_bus Rename pcicfg to pci_map_bus and add prototype for the platforms not supporting ECAM. Signed-off-by: Jianjun Wang <jianjun.wang(a)mediatek.com> Change-Id: Id9517c5ec4fa6b7c7a34552bfdc6d509927f6730 --- M src/include/device/pci_mmio_cfg.h 1 file changed, 16 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/59702/1 diff --git a/src/include/device/pci_mmio_cfg.h b/src/include/device/pci_mmio_cfg.h index cabf5b7..89c9906 100644 --- a/src/include/device/pci_mmio_cfg.h +++ b/src/include/device/pci_mmio_cfg.h @@ -40,11 +40,17 @@ extern u8 *const pci_mmconf; static __always_inline -volatile union pci_bank *pcicfg(pci_devfn_t dev) +volatile union pci_bank *pci_map_bus(pci_devfn_t dev) { return (void *)&pci_mmconf[PCI_DEVFN_OFFSET(dev)]; } +#else + +/* For platforms not supporting ECAM, they need to define pci_map_bus function + * in their platform-specific code */ +volatile union pci_bank *pci_map_bus(pci_devfn_t dev); + #endif /* @@ -56,37 +62,37 @@ static __always_inline uint8_t pci_s_read_config8(pci_devfn_t dev, uint16_t reg) { - return pcicfg(dev)->reg8[reg]; + return pci_map_bus(dev)->reg8[reg]; } static __always_inline uint16_t pci_s_read_config16(pci_devfn_t dev, uint16_t reg) { - return pcicfg(dev)->reg16[reg / sizeof(uint16_t)]; + return pci_map_bus(dev)->reg16[reg / sizeof(uint16_t)]; } static __always_inline uint32_t pci_s_read_config32(pci_devfn_t dev, uint16_t reg) { - return pcicfg(dev)->reg32[reg / sizeof(uint32_t)]; + return pci_map_bus(dev)->reg32[reg / sizeof(uint32_t)]; } static __always_inline void pci_s_write_config8(pci_devfn_t dev, uint16_t reg, uint8_t value) { - pcicfg(dev)->reg8[reg] = value; + pci_map_bus(dev)->reg8[reg] = value; } static __always_inline void pci_s_write_config16(pci_devfn_t dev, uint16_t reg, uint16_t value) { - pcicfg(dev)->reg16[reg / sizeof(uint16_t)] = value; + pci_map_bus(dev)->reg16[reg / sizeof(uint16_t)] = value; } static __always_inline void pci_s_write_config32(pci_devfn_t dev, uint16_t reg, uint32_t value) { - pcicfg(dev)->reg32[reg / sizeof(uint32_t)] = value; + pci_map_bus(dev)->reg32[reg / sizeof(uint32_t)] = value; } /* @@ -98,19 +104,19 @@ static __always_inline uint8_t *pci_mmio_config8_addr(pci_devfn_t dev, uint16_t reg) { - return (uint8_t *)&pcicfg(dev)->reg8[reg]; + return (uint8_t *)&pci_map_bus(dev)->reg8[reg]; } static __always_inline uint16_t *pci_mmio_config16_addr(pci_devfn_t dev, uint16_t reg) { - return (uint16_t *)&pcicfg(dev)->reg16[reg / sizeof(uint16_t)]; + return (uint16_t *)&pci_map_bus(dev)->reg16[reg / sizeof(uint16_t)]; } static __always_inline uint32_t *pci_mmio_config32_addr(pci_devfn_t dev, uint16_t reg) { - return (uint32_t *)&pcicfg(dev)->reg32[reg / sizeof(uint32_t)]; + return (uint32_t *)&pci_map_bus(dev)->reg32[reg / sizeof(uint32_t)]; } #endif /* _PCI_MMIO_CFG_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/59702 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id9517c5ec4fa6b7c7a34552bfdc6d509927f6730 Gerrit-Change-Number: 59702 Gerrit-PatchSet: 1 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: soc/mediatek: Add PCIe support
by Jianjun Wang (Code Review) 27 Nov '21

27 Nov '21

Attention is currently required from: Shelley Chen, Hung-Te Lin. Hello Shelley Chen, Hung-Te Lin, build bot (Jenkins), Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56791 to look at the new patch set (#4). Change subject: soc/mediatek: Add PCIe support ...................................................................... soc/mediatek: Add PCIe support Add PCIe support for MediaTek platform. Signed-off-by: Jianjun Wang <jianjun.wang(a)mediatek.com> Change-Id: Ib9b6adaafa20aeee136372ec9564273f86776da0 --- A src/soc/mediatek/common/include/soc/pcie_common.h A src/soc/mediatek/common/pcie.c 2 files changed, 372 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/56791/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/56791 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib9b6adaafa20aeee136372ec9564273f86776da0 Gerrit-Change-Number: 56791 Gerrit-PatchSet: 4 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: device/pci_device.c: Scan only one device for PCIe
by Jianjun Wang (Code Review) 27 Nov '21

27 Nov '21

Attention is currently required from: Shelley Chen, Furquan Shaikh, Paul Menzel, Jianjun Wang. Hello Shelley Chen, Hung-Te Lin, build bot (Jenkins), Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56788 to look at the new patch set (#4). Change subject: device/pci_device.c: Scan only one device for PCIe ...................................................................... device/pci_device.c: Scan only one device for PCIe Only scan one device if it's a PCIe downstream port. A PCIe downstream port normally leads to a link with only device 0 on it. As an optimization, scan only for device 0 in that case. Signed-off-by: Jianjun Wang <jianjun.wang(a)mediatek.com> Change-Id: Id184d03b33e1742b18efb3f11aa9b2f81fa03806 --- M src/device/pci_device.c M src/include/device/pci_def.h M src/include/device/pciexp.h 3 files changed, 36 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/56788/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/56788 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id184d03b33e1742b18efb3f11aa9b2f81fa03806 Gerrit-Change-Number: 56788 Gerrit-PatchSet: 4 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: soc/intel/elkhartlake: Introduce Intel PSE
by Lean Sheng Tan (Code Review) 27 Nov '21

27 Nov '21

Attention is currently required from: Arthur Heymans, Nico Huber, Martin Roth, Maulik V Vaghela, Mario Scheithauer, Angel Pons, Subrata Banik, Michael Niewöhner, Werner Zeh, Patrick Rudolph, Felix Held. Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55367 ) Change subject: soc/intel/elkhartlake: Introduce Intel PSE ...................................................................... Patch Set 58: (1 comment) Patchset: PS58: something wrong with the verify build.. the white space was removed but still failed… -- To view, visit https://review.coreboot.org/c/coreboot/+/55367 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifea08fb82fea18ef66bab04b3ce378e79a0afbf7 Gerrit-Change-Number: 55367 Gerrit-PatchSet: 58 Gerrit-Owner: Lean Sheng Tan Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Sat, 27 Nov 2021 00:13:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit November 2021