coreboot-gerrit November 2021

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Change in coreboot[master]: soc/amd/stoneyridge/psp: move soc_get_mbox_address to common psp_gen1
by Felix Held (Code Review) 26 Nov '21

26 Nov '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson. Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59701 ) Change subject: soc/amd/stoneyridge/psp: move soc_get_mbox_address to common psp_gen1 ...................................................................... soc/amd/stoneyridge/psp: move soc_get_mbox_address to common psp_gen1 Despite Stoneyridge being one only SoC in soc/amd that uses the first generation of the PSP mailblox interface, this code is common for all SoCs that use the first PSP mailbox interface generation, so move it to the common PSP generation 1 code. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I78126cb710a6ee674b58b35c8294685a5965ecd6 --- M src/soc/amd/common/block/include/amdblocks/psp.h M src/soc/amd/common/block/psp/psp_gen1.c M src/soc/amd/stoneyridge/include/soc/southbridge.h M src/soc/amd/stoneyridge/psp.c 4 files changed, 35 insertions(+), 33 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/59701/1 diff --git a/src/soc/amd/common/block/include/amdblocks/psp.h b/src/soc/amd/common/block/include/amdblocks/psp.h index 2aa000e..e749d75 100644 --- a/src/soc/amd/common/block/include/amdblocks/psp.h +++ b/src/soc/amd/common/block/include/amdblocks/psp.h @@ -5,9 +5,6 @@ #include <stdint.h> -/* Get the mailbox base address - specific to family of device. */ -void *soc_get_mbox_address(void); - #define SMM_TRIGGER_IO 0 #define SMM_TRIGGER_MEM 1 diff --git a/src/soc/amd/common/block/psp/psp_gen1.c b/src/soc/amd/common/block/psp/psp_gen1.c index 076d354..55070f2 100644 --- a/src/soc/amd/common/block/psp/psp_gen1.c +++ b/src/soc/amd/common/block/psp/psp_gen1.c @@ -1,6 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <cpu/amd/msr.h> +#include <cpu/x86/msr.h> #include <device/mmio.h> +#include <device/pci_ops.h> +#include <device/pci_def.h> #include <cbfs.h> #include <region_file.h> #include <timer.h> @@ -8,8 +12,39 @@ #include <amdblocks/psp.h> #include <soc/iomap.h> #include <soc/northbridge.h> +#include <soc/pci_devs.h> +#include <soc/southbridge.h> #include "psp_def.h" +#define PSP_MAILBOX_OFFSET 0x70 + +static void *soc_get_mbox_address(void) +{ + uintptr_t psp_mmio; + + /* Check for presence of the PSP */ + if (pci_read_config32(SOC_PSP_DEV, PCI_VENDOR_ID) == 0xffffffff) { + printk(BIOS_WARNING, "PSP: No SOC_PSP_DEV found at D%xF%x\n", + PSP_DEV, PSP_FUNC); + return 0; + } + + /* Determine if Bar3Hide has been set, and if hidden get the base from + * the MSR instead. */ + if (pci_read_config32(SOC_PSP_DEV, PSP_BAR_ENABLES) & BAR3HIDE) { + psp_mmio = rdmsr(PSP_ADDR_MSR).lo; + if (!psp_mmio) { + printk(BIOS_WARNING, "PSP: BAR hidden, PSP_ADDR_MSR uninitialized\n"); + return 0; + } + } else { + psp_mmio = pci_read_config32(SOC_PSP_DEV, PSP_MAILBOX_BAR) & + ~PCI_BASE_ADDRESS_MEM_ATTR_MASK; + } + + return (void *)(psp_mmio + PSP_MAILBOX_OFFSET); +} + static u32 rd_mbox_sts(struct pspv1_mbox *mbox) { return read32(&mbox->mbox_status); diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index 97eb806..74e9498 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -181,7 +181,6 @@ void soc_enable_psp_early(void); #define PSP_MAILBOX_BAR PCI_BASE_ADDRESS_4 /* BKDG: "BAR3" */ -#define PSP_MAILBOX_OFFSET 0x70 /* offset from BAR3 value */ #define PSP_BAR_ENABLES 0x48 #define BAR3HIDE BIT(12) /* Bit to hide BAR3 addr */ diff --git a/src/soc/amd/stoneyridge/psp.c b/src/soc/amd/stoneyridge/psp.c index b001d5f..e2a74bd 100644 --- a/src/soc/amd/stoneyridge/psp.c +++ b/src/soc/amd/stoneyridge/psp.c @@ -3,8 +3,6 @@ #include <console/console.h> #include <device/pci_ops.h> #include <device/pci_def.h> -#include <cpu/amd/msr.h> -#include <cpu/x86/msr.h> #include <soc/pci_devs.h> #include <soc/northbridge.h> #include <soc/southbridge.h> @@ -30,30 +28,3 @@ cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; pci_write_config16(SOC_PSP_DEV, PCI_COMMAND, cmd); }; - -void *soc_get_mbox_address(void) -{ - uintptr_t psp_mmio; - - /* Check for presence of the PSP */ - if (pci_read_config32(SOC_PSP_DEV, PCI_VENDOR_ID) == 0xffffffff) { - printk(BIOS_WARNING, "PSP: No SOC_PSP_DEV found at D%xF%x\n", - PSP_DEV, PSP_FUNC); - return 0; - } - - /* Determine if Bar3Hide has been set, and if hidden get the base from - * the MSR instead. */ - if (pci_read_config32(SOC_PSP_DEV, PSP_BAR_ENABLES) & BAR3HIDE) { - psp_mmio = rdmsr(PSP_ADDR_MSR).lo; - if (!psp_mmio) { - printk(BIOS_WARNING, "PSP: BAR hidden, PSP_ADDR_MSR uninitialized\n"); - return 0; - } - } else { - psp_mmio = pci_read_config32(SOC_PSP_DEV, PSP_MAILBOX_BAR) & - ~PCI_BASE_ADDRESS_MEM_ATTR_MASK; - } - - return (void *)(psp_mmio + PSP_MAILBOX_OFFSET); -} -- To view, visit https://review.coreboot.org/c/coreboot/+/59701 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I78126cb710a6ee674b58b35c8294685a5965ecd6 Gerrit-Change-Number: 59701 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/stoneyridge/psp: use PSP_MAILBOX_BAR define
by Felix Held (Code Review) 26 Nov '21

26 Nov '21

Attention is currently required from: Marshall Dawson. Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59700 ) Change subject: soc/amd/stoneyridge/psp: use PSP_MAILBOX_BAR define ...................................................................... soc/amd/stoneyridge/psp: use PSP_MAILBOX_BAR define PSP_MAILBOX_BAR is defined as PCI_BASE_ADDRESS_4, so use it instead of PCI_BASE_ADDRESS_4 in the code. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I8658b674b9adea85dfc71d7036ccf3ae17464b58 --- M src/soc/amd/stoneyridge/psp.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/59700/1 diff --git a/src/soc/amd/stoneyridge/psp.c b/src/soc/amd/stoneyridge/psp.c index 8d6290f..b001d5f 100644 --- a/src/soc/amd/stoneyridge/psp.c +++ b/src/soc/amd/stoneyridge/psp.c @@ -51,7 +51,7 @@ return 0; } } else { - psp_mmio = pci_read_config32(SOC_PSP_DEV, PCI_BASE_ADDRESS_4) & + psp_mmio = pci_read_config32(SOC_PSP_DEV, PSP_MAILBOX_BAR) & ~PCI_BASE_ADDRESS_MEM_ATTR_MASK; } -- To view, visit https://review.coreboot.org/c/coreboot/+/59700 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8658b674b9adea85dfc71d7036ccf3ae17464b58 Gerrit-Change-Number: 59700 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/common/block/psp/psp_def: drop PSPV2_STATUS_* defines
by Felix Held (Code Review) 26 Nov '21

26 Nov '21

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59699 ) Change subject: soc/amd/common/block/psp/psp_def: drop PSPV2_STATUS_* defines ...................................................................... soc/amd/common/block/psp/psp_def: drop PSPV2_STATUS_* defines PSPV2_STATUS_ERROR and PSPV2_STATUS_RECOVERY aren't used and the bit definitions are also wrong, so drop those defines. For the PSP mailbox interface version 2, struct pspv2_mbox is used to access the correct status bits. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I8e2aadfde00e2f7b0f99b462b8e3d6954959a584 --- M src/soc/amd/common/block/psp/psp_def.h 1 file changed, 0 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/59699/1 diff --git a/src/soc/amd/common/block/psp/psp_def.h b/src/soc/amd/common/block/psp/psp_def.h index 38d6206..4d3aca5 100644 --- a/src/soc/amd/common/block/psp/psp_def.h +++ b/src/soc/amd/common/block/psp/psp_def.h @@ -30,10 +30,6 @@ #define PSPV1_STATUS_HALT BIT(3) #define PSPV1_STATUS_RECOVERY BIT(4) -/* generic PSP interface status, v2 */ -#define PSPV2_STATUS_ERROR BIT(30) -#define PSPV2_STATUS_RECOVERY BIT(31) - /* psp_mbox consists of hardware registers beginning at PSPx000070 * mbox_command: BIOS->PSP command, cleared by PSP when complete * mbox_status: BIOS->PSP interface status -- To view, visit https://review.coreboot.org/c/coreboot/+/59699 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8e2aadfde00e2f7b0f99b462b8e3d6954959a584 Gerrit-Change-Number: 59699 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: src/mainboard/emulation/qemu-power9: require hb-mode=on
by Sergii Dmytruk (Code Review) 26 Nov '21

26 Nov '21

Attention is currently required from: Paul Menzel, Krystian Hebel, Timothy Pearson, Ron Minnich. Sergii Dmytruk has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57082 ) Change subject: src/mainboard/emulation/qemu-power9: require hb-mode=on ...................................................................... Patch Set 16: (1 comment) File src/arch/ppc64/rom_media.c: https://review.coreboot.org/c/coreboot/+/57082/comment/856d14e3_7af110f4 PS16, Line 6: MEM_REGION_DEV_RO_INIT(0x8000000, CONFIG_ROM_SIZE); > To get more hardware-like experience, this should be at 0x00060300FC000000 (note that LPC base is de […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/57082 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1bdc97a095bd46fccc862985b3bd24f4fa5bc054 Gerrit-Change-Number: 57082 Gerrit-PatchSet: 16 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Ron Minnich <rminnich(a)gmail.com> Gerrit-Reviewer: Timothy Pearson <tpearson(a)raptorengineering.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-CC: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Attention: Timothy Pearson <tpearson(a)raptorengineering.com> Gerrit-Attention: Ron Minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Fri, 26 Nov 2021 21:41:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-MessageType: comment

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Change in coreboot[master]: src/arch/ppc64/*: pass FDT address to payload
by Sergii Dmytruk (Code Review) 26 Nov '21

26 Nov '21

Attention is currently required from: Krystian Hebel, Timothy Pearson, Ron Minnich. Sergii Dmytruk has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57084 ) Change subject: src/arch/ppc64/*: pass FDT address to payload ...................................................................... Patch Set 20: (2 comments) File src/arch/ppc64/boot.c: https://review.coreboot.org/c/coreboot/+/57084/comment/e833b518_d54f5103 PS20, Line 42: asm("ld 27,%0" :: "m"(fdt) : "27"); > Only QEMU prepares FDT in advance, real hardware doesn't, so all of the new code should be moved to […] Done File src/arch/ppc64/bootblock_crt0.S: https://review.coreboot.org/c/coreboot/+/57084/comment/da1b7dc5_2e7a3ca1 PS20, Line 40: /* Store FDT address that's available in %r3 to pass to payload */ > Maybe use one of SPRs for holding this value so it won't have to be moved around in RAM? HSPRG0 or H […] Used HSPRG0. This significantly simplified this change. -- To view, visit https://review.coreboot.org/c/coreboot/+/57084 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0911f4b534c6f8cacfa057a5bad7576fec711637 Gerrit-Change-Number: 57084 Gerrit-PatchSet: 20 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Ron Minnich <rminnich(a)gmail.com> Gerrit-Reviewer: Timothy Pearson <tpearson(a)raptorengineering.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Attention: Timothy Pearson <tpearson(a)raptorengineering.com> Gerrit-Attention: Ron Minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Fri, 26 Nov 2021 21:41:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-MessageType: comment

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Change in coreboot[master]: payloads/external: add skiboot (for QEMU/Power9)
by Sergii Dmytruk (Code Review) 26 Nov '21

26 Nov '21

Attention is currently required from: Martin Roth, Igor Bagnucki, Stefan Reinauer, Krystian Hebel, Timothy Pearson. Hello build bot (Jenkins), Martin Roth, Igor Bagnucki, Stefan Reinauer, Krystian Hebel, Timothy Pearson, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/58656 to look at the new patch set (#11). Change subject: payloads/external: add skiboot (for QEMU/Power9) ...................................................................... payloads/external: add skiboot (for QEMU/Power9) Add an option to build skiboot as a payload. This makes QEMU Power9 board simpler to use as skiboot is necessary anyway. Change-Id: I0b49ea7464c97cc2ff0d5030629deed549851372 Signed-off-by: Igor Bagnucki <igor.bagnucki(a)3mdeb.com> Signed-off-by: Krystian Hebel <krystian.hebel(a)3mdeb.com> Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> --- M Documentation/mainboard/emulation/qemu-power9.md M payloads/Makefile.inc M payloads/external/.gitignore M payloads/external/Makefile.inc A payloads/external/skiboot/Kconfig A payloads/external/skiboot/Kconfig.name A payloads/external/skiboot/Makefile M src/mainboard/emulation/qemu-power9/Kconfig 8 files changed, 105 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/58656/11 -- To view, visit https://review.coreboot.org/c/coreboot/+/58656 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0b49ea7464c97cc2ff0d5030629deed549851372 Gerrit-Change-Number: 58656 Gerrit-PatchSet: 11 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Igor Bagnucki <igor.bagnucki(a)3mdeb.com> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Timothy Pearson <tpearson(a)raptorengineering.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Igor Bagnucki <igor.bagnucki(a)3mdeb.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Attention: Timothy Pearson <tpearson(a)raptorengineering.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: src/arch/ppc64/*: pass FDT address to payload
by Sergii Dmytruk (Code Review) 26 Nov '21

26 Nov '21

Attention is currently required from: Timothy Pearson, Ron Minnich. Hello build bot (Jenkins), Arthur Heymans, Krystian Hebel, Timothy Pearson, Ron Minnich, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/57084 to look at the new patch set (#21). Change subject: src/arch/ppc64/*: pass FDT address to payload ...................................................................... src/arch/ppc64/*: pass FDT address to payload It's available in %r3 in bootblock and needs to be passed to payload in %r17. We use one of two hypervisor's special registers as a buffer, which aren't used for anything by the code. Change-Id: I0911f4b534c6f8cacfa057a5bad7576fec711637 Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> --- M src/arch/ppc64/bootblock_crt0.S M src/include/cpu/power/spr.h M src/mainboard/emulation/qemu-power9/Makefile.inc A src/mainboard/emulation/qemu-power9/ramstage.c 4 files changed, 32 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/57084/21 -- To view, visit https://review.coreboot.org/c/coreboot/+/57084 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0911f4b534c6f8cacfa057a5bad7576fec711637 Gerrit-Change-Number: 57084 Gerrit-PatchSet: 21 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Ron Minnich <rminnich(a)gmail.com> Gerrit-Reviewer: Timothy Pearson <tpearson(a)raptorengineering.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Timothy Pearson <tpearson(a)raptorengineering.com> Gerrit-Attention: Ron Minnich <rminnich(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: src/mainboard/emulation/qemu-power9: require hb-mode=on
by Sergii Dmytruk (Code Review) 26 Nov '21

26 Nov '21

Attention is currently required from: Paul Menzel, Timothy Pearson, Ron Minnich. Hello build bot (Jenkins), Arthur Heymans, Timothy Pearson, Ron Minnich, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/57082 to look at the new patch set (#17). Change subject: src/mainboard/emulation/qemu-power9: require hb-mode=on ...................................................................... src/mainboard/emulation/qemu-power9: require hb-mode=on "hb-mode" is a -machine flag for QEMU. "hb" stands for Hostboot, which is OpenPower firmware created by IBM. QEMU for PPC64 can run initial program in two different modes: * hb-mode=off with load address 0x00000000 * hb-mode=on with load address 0x08000000 Real hardware always loads firmware at 0x08000000 and coreboot shouldn't require a special build to be run on QEMU. Memory layout is updated to reflect change of load address. Change-Id: I1bdc97a095bd46fccc862985b3bd24f4fa5bc054 Signed-off-by: Yaroslav Kurlaev <yaroslav.kurlaev(a)3mdeb.com> Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> --- M src/arch/ppc64/include/arch/io.h M src/arch/ppc64/rom_media.c M src/arch/ppc64/stages.c M src/mainboard/emulation/qemu-power9/memlayout.ld 4 files changed, 36 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/57082/17 -- To view, visit https://review.coreboot.org/c/coreboot/+/57082 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1bdc97a095bd46fccc862985b3bd24f4fa5bc054 Gerrit-Change-Number: 57082 Gerrit-PatchSet: 17 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Ron Minnich <rminnich(a)gmail.com> Gerrit-Reviewer: Timothy Pearson <tpearson(a)raptorengineering.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-CC: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Timothy Pearson <tpearson(a)raptorengineering.com> Gerrit-Attention: Ron Minnich <rminnich(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: src/mainboard/emulation/qemu-power9/*: add QEMU POWER9 mainboard
by Sergii Dmytruk (Code Review) 26 Nov '21

26 Nov '21

Attention is currently required from: Arthur Heymans, Ron Minnich, Timothy Pearson. Hello build bot (Jenkins), Arthur Heymans, Ron Minnich, Timothy Pearson, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/57079 to look at the new patch set (#15). Change subject: src/mainboard/emulation/qemu-power9/*: add QEMU POWER9 mainboard ...................................................................... src/mainboard/emulation/qemu-power9/*: add QEMU POWER9 mainboard Add initial implementation for booting on QEMU POWER9 emulation. Change-Id: I079c5b9ad564024dd13296ef75c263bdc40c9d39 Signed-off-by: Yaroslav Kurlaev <yaroslav.kurlaev(a)3mdeb.com> Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> --- A Documentation/mainboard/emulation/qemu-power9.md A configs/config.emulation_qemu_power9 A src/mainboard/emulation/qemu-power9/Kconfig A src/mainboard/emulation/qemu-power9/Kconfig.name A src/mainboard/emulation/qemu-power9/Makefile.inc A src/mainboard/emulation/qemu-power9/board_info.txt A src/mainboard/emulation/qemu-power9/cbmem.c A src/mainboard/emulation/qemu-power9/devicetree.cb A src/mainboard/emulation/qemu-power9/mainboard.c A src/mainboard/emulation/qemu-power9/memlayout.ld A src/mainboard/emulation/qemu-power9/romstage.c 11 files changed, 146 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/57079/15 -- To view, visit https://review.coreboot.org/c/coreboot/+/57079 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I079c5b9ad564024dd13296ef75c263bdc40c9d39 Gerrit-Change-Number: 57079 Gerrit-PatchSet: 15 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Ron Minnich <rminnich(a)gmail.com> Gerrit-Reviewer: Timothy Pearson <tpearson(a)raptorengineering.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Ron Minnich <rminnich(a)gmail.com> Gerrit-Attention: Timothy Pearson <tpearson(a)raptorengineering.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common: Add check before sending HMRFPO_ENABLE command
by Sridhar Siricilla (Code Review) 26 Nov '21

26 Nov '21

Sridhar Siricilla has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59698 ) Change subject: soc/intel/common: Add check before sending HMRFPO_ENABLE command ...................................................................... soc/intel/common: Add check before sending HMRFPO_ENABLE command The patch add check if CSE's current operation mode ME_HFS1_COM_SECOVER_MEI_MSG or not before sending HMRFPO_ENABLE command to CSE. If CSE is already in the ME_HFS1_COM_SECOVER_MEI_MSG, coreboot skips sending HMRFPO_ENABLE command to CSE to unlock the CSE RW partition. TEST=Verify sending HMRFPO_ENABLE command on Brya system. Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: I387ac7c7296ab06b9bb440d5d40c3286bf879d3b --- M src/soc/intel/common/block/cse/cse.c 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/59698/1 diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index b46d3e4..a80ab48 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -744,6 +744,12 @@ struct hmrfpo_enable_resp resp; size_t resp_size = sizeof(struct hmrfpo_enable_resp); + if (cse_is_hfs1_com_secover_mei_msg()) { + printk(BIOS_DEBUG, "HECI: CSE is already in security override mode, " + "skip sending HMRFPO_ENABLE command to CSE\n"); + return 1; + } + printk(BIOS_DEBUG, "HECI: Send HMRFPO Enable Command\n"); if (!cse_is_hmrfpo_enable_allowed()) { -- To view, visit https://review.coreboot.org/c/coreboot/+/59698 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I387ac7c7296ab06b9bb440d5d40c3286bf879d3b Gerrit-Change-Number: 59698 Gerrit-PatchSet: 1 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: newchange

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coreboot-gerrit November 2021