coreboot-gerrit November 2021

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Change in coreboot[master]: acpi/acpigen, drivers/tpm: Move definition of set_package_element_op
by Sridhar Siricilla (Code Review) 29 Nov '21

29 Nov '21

Attention is currently required from: Lance Zhao, Tim Wawrzynczak. Sridhar Siricilla has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59729 ) Change subject: acpi/acpigen, drivers/tpm: Move definition of set_package_element_op ...................................................................... acpi/acpigen, drivers/tpm: Move definition of set_package_element_op The patch moves set_package_element_op() function from drivers/tpm/ppi.c to acpi/acpigen.c, renames the function to acpigen_set_package_element_op() and make changas to all references. The function definition is moved to acpi/acpigen.c so that soc/intel/common/acpi/cpu_hybrid.c can use the function. TEST=Build and boot Brya Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: I4fe70a1f369c97c67bbc1717e6adc7c5f4ba5839 --- M src/acpi/acpigen.c M src/drivers/tpm/ppi.c M src/include/acpi/acpigen.h 3 files changed, 20 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/59729/1 diff --git a/src/acpi/acpigen.c b/src/acpi/acpigen.c index ff04d0f..a1bbf24 100644 --- a/src/acpi/acpigen.c +++ b/src/acpi/acpigen.c @@ -63,6 +63,17 @@ (*gencurrent++) = b; } +void acpigen_set_package_element_op(const char *package_name, unsigned int element, + uint8_t src_op) +{ + acpigen_write_store(); + acpigen_emit_byte(src_op); + acpigen_emit_byte(INDEX_OP); + acpigen_emit_namestring(package_name); + acpigen_write_integer(element); + acpigen_emit_byte(ZERO_OP); /* Ignore Index() Destination */ +} + void acpigen_emit_ext_op(uint8_t op) { acpigen_emit_byte(EXT_OP_PREFIX); diff --git a/src/drivers/tpm/ppi.c b/src/drivers/tpm/ppi.c index 88dd649..134aafe 100644 --- a/src/drivers/tpm/ppi.c +++ b/src/drivers/tpm/ppi.c @@ -12,17 +12,6 @@ #define BCD(x, y) (((x) << 4) | ((y) << 0)) -static void set_package_element_op(const char *package_name, unsigned int element, - uint8_t src_op) -{ - acpigen_write_store(); - acpigen_emit_byte(src_op); - acpigen_emit_byte(INDEX_OP); - acpigen_emit_namestring(package_name); - acpigen_write_integer(element); - acpigen_emit_byte(ZERO_OP); /* Ignore Index() Destination */ -} - static void set_package_element_name(const char *package_name, unsigned int element, const char *src) { @@ -182,10 +171,10 @@ acpigen_emit_byte(LOCAL0_OP); /* ^TPM3 [0] = PPI3_RET_GENERAL_FAILURE */ - set_package_element_op("^TPM3", 0, LOCAL0_OP); + acpigen_set_package_element_op("^TPM3", 0, LOCAL0_OP); /* ^TPM2 [0] = PPI3_RET_GENERAL_FAILURE */ - set_package_element_op("^TPM2", 0, LOCAL0_OP); + acpigen_set_package_element_op("^TPM2", 0, LOCAL0_OP); acpigen_write_to_integer(ARG1_OP, LOCAL0_OP); @@ -196,7 +185,7 @@ acpigen_write_store(); acpigen_write_integer(PPI3_RET_SUCCESS); acpigen_emit_byte(LOCAL1_OP); - set_package_element_op("^TPM2", 0, LOCAL1_OP); + acpigen_set_package_element_op("^TPM2", 0, LOCAL1_OP); /* ^TPM2 [1] = ^CMDR */ set_package_element_name("^TPM2", 1, "^CMDR"); @@ -217,7 +206,7 @@ acpigen_write_store(); acpigen_write_integer(PPI3_RET_SUCCESS); acpigen_emit_byte(LOCAL1_OP); - set_package_element_op("^TPM3", 0, LOCAL1_OP); + acpigen_set_package_element_op("^TPM3", 0, LOCAL1_OP); /* ^TPM3 [1] = ^CMDR */ set_package_element_name("^TPM3", 1, "^CMDR"); @@ -275,7 +264,7 @@ acpigen_write_store(); acpigen_write_integer(PPI5_RET_GENERAL_FAILURE); acpigen_emit_byte(LOCAL1_OP); - set_package_element_op("^TPM3", 0, LOCAL1_OP); + acpigen_set_package_element_op("^TPM3", 0, LOCAL1_OP); acpigen_write_to_integer(ARG1_OP, LOCAL0_OP); @@ -286,7 +275,7 @@ acpigen_write_store(); acpigen_write_integer(PPI5_RET_SUCCESS); acpigen_emit_byte(LOCAL1_OP); - set_package_element_op("^TPM3", 0, LOCAL1_OP); + acpigen_set_package_element_op("^TPM3", 0, LOCAL1_OP); /* ^TPM3 [1] = ^LCMD */ set_package_element_name("^TPM3", 1, "^LCMD"); diff --git a/src/include/acpi/acpigen.h b/src/include/acpi/acpigen.h index 027a0e3..c6e0862 100644 --- a/src/include/acpi/acpigen.h +++ b/src/include/acpi/acpigen.h @@ -526,6 +526,9 @@ */ void acpigen_get_package_op_element(uint8_t package_op, unsigned int element, uint8_t dest_op); +/* Set element of package to speicified op: <package>[<element>] = <src_op> */ +void acpigen_set_package_element_op(const char *package_name, unsigned int element, uint8_t src_op); + /* Set element of package op to specified op: DeRefOf (<package>[<element>]) = <src> */ void acpigen_set_package_op_element_int(uint8_t package_op, unsigned int element, uint64_t src); -- To view, visit https://review.coreboot.org/c/coreboot/+/59729 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4fe70a1f369c97c67bbc1717e6adc7c5f4ba5839 Gerrit-Change-Number: 59729 Gerrit-PatchSet: 1 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Lance Zhao Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/alderlake: Enable CPPCv3 for Intel Alderlake
by Sridhar Siricilla (Code Review) 29 Nov '21

29 Nov '21

Attention is currently required from: Tim Wawrzynczak, Patrick Rudolph. Hello build bot (Jenkins), Tim Wawrzynczak, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59363 to look at the new patch set (#4). Change subject: soc/intel/alderlake: Enable CPPCv3 for Intel Alderlake ...................................................................... soc/intel/alderlake: Enable CPPCv3 for Intel Alderlake The patch enables CPPCv3 support for Intel Alderlake which is based on hybrid core architecture. Dependency= OS patches TEST=Verified Nominal Frequency and Nominal Performance are getting updated for ADL-P small and big cores correctly. Signed-off-by: Sridahr Siricilla <sridhar.siricilla(a)intel.com> Change-Id: Icaacd4a4ba953d8337f557903ed2ea9da4a60fb9 --- M src/soc/intel/alderlake/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/59363/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/59363 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icaacd4a4ba953d8337f557903ed2ea9da4a60fb9 Gerrit-Change-Number: 59363 Gerrit-PatchSet: 4 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/alderlake: Define the helper functions
by Sridhar Siricilla (Code Review) 29 Nov '21

29 Nov '21

Attention is currently required from: Tim Wawrzynczak, Patrick Rudolph. Hello build bot (Jenkins), Tim Wawrzynczak, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59362 to look at the new patch set (#4). Change subject: soc/intel/alderlake: Define the helper functions ...................................................................... soc/intel/alderlake: Define the helper functions The patch defines following helper functions: get_cpu_scaling_factor(): Returns scaling factors of big and small core. cpu_is_nominal_freq_supported(): Returns TRUE if cpu supports Nominal Frequency, otherwise FASLE. cpu_is_nominal_freq_supported(): Check CPU supports nominal frequency or not. TEST=Verified OS updating the Nominal Performance and Nominal Frequency for big and small cores. Signed-off-by: Sridahr Siricilla <sridhar.siricilla(a)intel.com> Change-Id: I963690a4fadad322095d202bcc08c92dcd845360 --- M src/soc/intel/alderlake/cpu.c 1 file changed, 11 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/59362/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/59362 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I963690a4fadad322095d202bcc08c92dcd845360 Gerrit-Change-Number: 59362 Gerrit-PatchSet: 4 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common: Implement ACPI CPPCv3 package to support hybrid core
by Sridhar Siricilla (Code Review) 29 Nov '21

29 Nov '21

Attention is currently required from: Arthur Heymans, Nico Huber, Paul Menzel, Tim Wawrzynczak, Ravindra, Michael Niewöhner, Patrick Rudolph. Hello Arthur Heymans, build bot (Jenkins), Nico Huber, Tim Wawrzynczak, Ravindra, Michael Niewöhner, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59359 to look at the new patch set (#4). Change subject: soc/intel/common: Implement ACPI CPPCv3 package to support hybrid core ...................................................................... soc/intel/common: Implement ACPI CPPCv3 package to support hybrid core The patch implements ACPI CPPCv3 package. It implements and updates the following methods: generate_cppc_entries(): Updates method to support CPPCv3 package acpigen_write_CPPC_hybrid_method(): It generates ACPI code to implement _CPC method and calls XPPPC method. acpi_write_xppc_method(): It generates ACPI code if cpu supports Nominal Frequency. It generates ACPI code which sets Nominal Frequency and updates Nominal Performance. It uses below calculation to update the Nominal Frequency and Nominal Performance: Nominal Frequency = Max non-turbo ratio * cpu_bus_frequency Nominal Performance = Max non-turn ratio * cpu scaling factor CPU scaling factor varies in the hybrid core environment. So, the generated ACPI code updates Nominal Performance based on the CPU's scaling factor. TEST=Verified CPPCv3 package and XPP3 method are getting created in the SSDT table. Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Signed-off-by: ravindr1 <ravindra(a)intel.com> Change-Id: Icd5ea9e70bebd1e66d3cea2bcf8a6678e5cc95ca --- M src/soc/intel/common/block/acpi/acpi.c M src/soc/intel/common/block/acpi/cpu_hybrid.c M src/soc/intel/common/block/include/intelblocks/acpi.h 3 files changed, 116 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/59359/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/59359 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icd5ea9e70bebd1e66d3cea2bcf8a6678e5cc95ca Gerrit-Change-Number: 59359 Gerrit-PatchSet: 4 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Ravindra <ravindra(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.corp-partner.google.com> Gerrit-CC: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Ravindra <ravindra(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/alderlake, soc/common: Add method to determine the cpu type
by Sridhar Siricilla (Code Review) 29 Nov '21

29 Nov '21

Attention is currently required from: Tim Wawrzynczak, Arthur Heymans, Patrick Rudolph. Hello build bot (Jenkins), Tim Wawrzynczak, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59360 to look at the new patch set (#4). Change subject: soc/intel/alderlake, soc/common: Add method to determine the cpu type ...................................................................... soc/intel/alderlake, soc/common: Add method to determine the cpu type set_cpu_type(): It determines the cpu type (big or small) that is executing the function, and marks the global_cpu_type's array slot which is corresponds to the executing cpu's index if the cpu type is big. get_cpu_index(): It determines the index from LAPIC Ids. This is required to expose CPPC3 package in ascending order of CPUs' LAPIC ids. So, the function returns CPU's position from the ascending order list of LAPIC ids. get_cpu_type(): It returns the type of CPU that executing the function. Also, it calls the set_cpu_type() from soc/alderlake/cpu.c file. TEST=Tested CPU index calculation, core type determination on Brya Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: If4ceb24d9bb1e808750bf618c29b2b9ea6d4191b --- M src/soc/intel/alderlake/cpu.c M src/soc/intel/common/block/acpi/Kconfig M src/soc/intel/common/block/acpi/Makefile.inc A src/soc/intel/common/block/acpi/cpu_hybrid.c M src/soc/intel/common/block/include/intelblocks/acpi.h 5 files changed, 93 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/59360/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/59360 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If4ceb24d9bb1e808750bf618c29b2b9ea6d4191b Gerrit-Change-Number: 59360 Gerrit-PatchSet: 4 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common: Add CPU related APIs
by Sridhar Siricilla (Code Review) 29 Nov '21

29 Nov '21

Attention is currently required from: Nico Huber, Maulik V Vaghela, Tim Wawrzynczak, Sugnan Prabhu S, Sridhar Siricilla, Subrata Banik, Patrick Rudolph. Hello build bot (Jenkins), Nico Huber, Maulik V Vaghela, Sugnan Prabhu S, Tim Wawrzynczak, Subrata Banik, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59124 to look at the new patch set (#5). Change subject: soc/intel/common: Add CPU related APIs ...................................................................... soc/intel/common: Add CPU related APIs The patch defines below APIs : cpu_is_hybrid_supported() : Check whether CPU is hybrid CPU or not. cpu_get_bus_frequency() : Get CPU's bus frequency cpu_get_max_non_turbo_ratio() : Get CPU's max non-turbo ratio cpu_get_cpu_typ() : Get CPU type. The function must be called if executing CPU is hybrid. TEST=Verified the APIs on the Brya board Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: I680f43952ab4abce6e342206688ad32814970a91 --- M src/soc/intel/common/block/cpu/cpulib.c M src/soc/intel/common/block/include/intelblocks/cpulib.h 2 files changed, 68 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/59124/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/59124 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I680f43952ab4abce6e342206688ad32814970a91 Gerrit-Change-Number: 59124 Gerrit-PatchSet: 5 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.corp-partner.google.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: brya: add various ES variants
by YH Lin (Code Review) 29 Nov '21

29 Nov '21

Attention is currently required from: Tim Wawrzynczak, Nick Vaccaro, Zhuohao Lee. YH Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59728 ) Change subject: brya: add various ES variants ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: Failure due to symlinks? Is it allowed? Thanks. -- To view, visit https://review.coreboot.org/c/coreboot/+/59728 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic9516fec591429238bde1478eca2522d8ed10127 Gerrit-Change-Number: 59728 Gerrit-PatchSet: 1 Gerrit-Owner: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Comment-Date: Mon, 29 Nov 2021 17:57:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/vell: update memory settings
by Tim Wawrzynczak (Code Review) 29 Nov '21

29 Nov '21

Attention is currently required from: Kevin Chiu, YH Lin, Paul Menzel, Nick Vaccaro, Shon Wang, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59334 ) Change subject: mb/google/brya/var/vell: update memory settings ...................................................................... Patch Set 12: (1 comment) File src/mainboard/google/brya/variants/vell/memory.c: https://review.coreboot.org/c/coreboot/+/59334/comment/3802f25d_0d071865 PS12, Line 67: 1 `true` -- To view, visit https://review.coreboot.org/c/coreboot/+/59334 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic0bbac5eaebc77639be6c1bc399658ac90e72fbb Gerrit-Change-Number: 59334 Gerrit-PatchSet: 12 Gerrit-Owner: Shon Wang <shon.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Gerrit-CC: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Gerrit-CC: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Attention: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Shon Wang <shon.wang(a)quanta.corp-partner.google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 29 Nov 2021 17:57:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/vell: update memory settings
by Tim Wawrzynczak (Code Review) 29 Nov '21

29 Nov '21

Attention is currently required from: Kevin Chiu, YH Lin, Paul Menzel, Nick Vaccaro, Shon Wang, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59334 ) Change subject: mb/google/brya/var/vell: update memory settings ...................................................................... Patch Set 12: (1 comment) File src/mainboard/google/brya/variants/vell/memory.c: https://review.coreboot.org/c/coreboot/+/59334/comment/20b5148a_6bd82d60 PS12, Line 68: is `.LpDdrDqDqsReTraining = 1` required? -- To view, visit https://review.coreboot.org/c/coreboot/+/59334 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic0bbac5eaebc77639be6c1bc399658ac90e72fbb Gerrit-Change-Number: 59334 Gerrit-PatchSet: 12 Gerrit-Owner: Shon Wang <shon.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Gerrit-CC: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Gerrit-CC: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Attention: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Shon Wang <shon.wang(a)quanta.corp-partner.google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 29 Nov 2021 17:55:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: utils: Add initial version of "remove_unused_code" script
by Raul Rangel (Code Review) 29 Nov '21

29 Nov '21

Attention is currently required from: Martin Roth, Piotr Król. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59169 ) Change subject: utils: Add initial version of "remove_unused_code" script ...................................................................... Patch Set 2: (10 comments) File util/scripts/rm_unused_code: https://review.coreboot.org/c/coreboot/+/59169/comment/ba1cfa39_c4b8b98d PS1, Line 115: ${dir} > Done Looks like it's still missing https://review.coreboot.org/c/coreboot/+/59169/comment/7f8ac73d_854131bb PS1, Line 125: ${dir} > Done Still missing https://review.coreboot.org/c/coreboot/+/59169/comment/b195f3a5_39919820 PS1, Line 214: ${CONFIG_FILE} > Done Quotes missing https://review.coreboot.org/c/coreboot/+/59169/comment/23380721_e5d2ba20 PS1, Line 221: || exit 1 > Right. This is left over from before I had the -e. Removed. Still here File util/scripts/rm_unused_code: https://review.coreboot.org/c/coreboot/+/59169/comment/cfb70387_07557a0d PS2, Line 20: ${CLEAN_DIR_LIST} What's this for? https://review.coreboot.org/c/coreboot/+/59169/comment/d361a03e_995f11c0 PS2, Line 120: exit Do you really want to exit the whole script? https://review.coreboot.org/c/coreboot/+/59169/comment/8c70a84a_215d10bb PS2, Line 120: then Why the single line? https://review.coreboot.org/c/coreboot/+/59169/comment/093afb48_5b60b774 PS2, Line 120: && I think you can remove this https://review.coreboot.org/c/coreboot/+/59169/comment/29bfac40_50320d42 PS2, Line 121: cd "${file} Is this expected to have a side effect? https://review.coreboot.org/c/coreboot/+/59169/comment/469e7577_f7399193 PS2, Line 121: find . -maxdepth 1 Can this line be simplified `if [[ -e "${file}/Makefile" ]]`? -- To view, visit https://review.coreboot.org/c/coreboot/+/59169 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iec69db2ad1358846d649db627b6d60ac8c2204e4 Gerrit-Change-Number: 59169 Gerrit-PatchSet: 2 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Comment-Date: Mon, 29 Nov 2021 17:48:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: comment

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coreboot-gerrit November 2021