coreboot-gerrit November 2021

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Change in coreboot[master]: soc/amd/stoneyridge/psp: move soc_get_mbox_address to common psp_gen1
by Raul Rangel (Code Review) 29 Nov '21

29 Nov '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Paul Menzel, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59701 ) Change subject: soc/amd/stoneyridge/psp: move soc_get_mbox_address to common psp_gen1 ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59701 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I78126cb710a6ee674b58b35c8294685a5965ecd6 Gerrit-Change-Number: 59701 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 29 Nov 2021 20:41:41 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/cezanne: Preload uCode
by Karthik Ramasubramanian (Code Review) 29 Nov '21

29 Nov '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Felix Held. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59506 ) Change subject: soc/amd/cezanne: Preload uCode ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59506 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3bde5bd36489818b1a19b30490d7bb202c26ee34 Gerrit-Change-Number: 59506 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 29 Nov 2021 20:40:13 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: src/cpu,soc/amd/common/block/cpu: Add preload_microcode
by Raul Rangel (Code Review) 29 Nov '21

29 Nov '21

Raul Rangel has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58963 ) Change subject: src/cpu,soc/amd/common/block/cpu: Add preload_microcode ...................................................................... src/cpu,soc/amd/common/block/cpu: Add preload_microcode This will enable preloading the microcode. By preloading the file, into cbfs_cache we reduce boot time. BUG=b:179699789 TEST=Boot guybrush with CL chain and see microcode preloading and a reduction of 1 ms. | 112 - started reading uCode | 1.041 | 1.204 Δ( 0.16, 0.01%) | | 113 - finished reading uCode | 1.365 | 0.011 Δ( -1.35, -0.10%) | Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: If0c634c692c97769e71acd1175fc464dc592c356 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58963 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> --- M src/cpu/Makefile.inc M src/include/cpu/amd/microcode.h M src/soc/amd/common/block/cpu/update_microcode.c 3 files changed, 20 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Karthik Ramasubramanian: Looks good to me, approved diff --git a/src/cpu/Makefile.inc b/src/cpu/Makefile.inc index ec2f19f..9f1e6c4 100644 --- a/src/cpu/Makefile.inc +++ b/src/cpu/Makefile.inc @@ -56,7 +56,12 @@ cpu_microcode_blob.bin-file ?= $(obj)/cpu_microcode_blob.bin cpu_microcode_blob.bin-type := microcode +# The AMD LPC SPI DMA controller requires source files to be 64 byte aligned. +ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA),y) +cpu_microcode_blob.bin-align := 64 +else cpu_microcode_blob.bin-align := 16 +endif ifneq ($(CONFIG_CPU_MICROCODE_CBFS_LOC),) cpu_microcode_blob.bin-COREBOOT-position := $(CONFIG_CPU_MICROCODE_CBFS_LOC) diff --git a/src/include/cpu/amd/microcode.h b/src/include/cpu/amd/microcode.h index 800661b..7407594 100644 --- a/src/include/cpu/amd/microcode.h +++ b/src/include/cpu/amd/microcode.h @@ -2,5 +2,6 @@ #define CPU_AMD_MICROCODE_H void amd_update_microcode_from_cbfs(void); +void preload_microcode(void); #endif /* CPU_AMD_MICROCODE_H */ diff --git a/src/soc/amd/common/block/cpu/update_microcode.c b/src/soc/amd/common/block/cpu/update_microcode.c index e6a57f5..33b244d 100644 --- a/src/soc/amd/common/block/cpu/update_microcode.c +++ b/src/soc/amd/common/block/cpu/update_microcode.c @@ -10,6 +10,8 @@ #include <cbfs.h> #include <timestamp.h> +#define CPU_MICROCODE_BLOB_NAME "cpu_microcode_blob.bin" + _Static_assert(CONFIG_SOC_AMD_COMMON_BLOCK_UCODE_SIZE > 0, "SOC_AMD_COMMON_BLOCK_UCODE_SIZE is not set"); @@ -97,9 +99,10 @@ /* Cache the buffer so each CPU doesn't need to read the uCode from flash */ if (!cache_valid) { timestamp_add_now(TS_READ_UCODE_START); - ucode_list = cbfs_map("cpu_microcode_blob.bin", &ucode_len); + ucode_list = cbfs_map(CPU_MICROCODE_BLOB_NAME, &ucode_len); if (!ucode_list) { - printk(BIOS_WARNING, "cpu_microcode_blob.bin not found. Skipping updates.\n"); + printk(BIOS_WARNING, + CPU_MICROCODE_BLOB_NAME " not found. Skipping updates.\n"); return; } @@ -120,3 +123,12 @@ apply_microcode_patch(&ucode_cache); } + +void preload_microcode(void) +{ + if (!CONFIG(CBFS_PRELOAD)) + return; + + printk(BIOS_DEBUG, "Preloading microcode %s\n", CPU_MICROCODE_BLOB_NAME); + cbfs_preload(CPU_MICROCODE_BLOB_NAME); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/58963 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If0c634c692c97769e71acd1175fc464dc592c356 Gerrit-Change-Number: 58963 Gerrit-PatchSet: 5 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: intel: cse_lite: Use cbfs_unverified_area API
by Raul Rangel (Code Review) 29 Nov '21

29 Nov '21

Attention is currently required from: Julius Werner, Patrick Rudolph. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59679 ) Change subject: intel: cse_lite: Use cbfs_unverified_area API ...................................................................... Patch Set 2: (1 comment) File src/soc/intel/common/block/cse/cse_lite.c: https://review.coreboot.org/c/coreboot/+/59679/comment/49b31603_4af54462 PS2, Line 676: cbfs_unverified_area_map > Yes, the vboot loading/hashing time penalty was too much to bear on every boot, so as you noticed, t […] Just curious, is the FW compressed in CBFS? If it's not, could we switch to using a raw FMAP region instead? -- To view, visit https://review.coreboot.org/c/coreboot/+/59679 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If4855280d6d06cf1aa646fded916fd830b287b30 Gerrit-Change-Number: 59679 Gerrit-PatchSet: 2 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 29 Nov 2021 20:38:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/stoneyridge/psp: move soc_get_mbox_address to common psp_gen1
by Felix Held (Code Review) 29 Nov '21

29 Nov '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Paul Menzel. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59701 ) Change subject: soc/amd/stoneyridge/psp: move soc_get_mbox_address to common psp_gen1 ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: soc_get_mbox_address needs to be a static function in the psp_gen2 code too after the prototype got removed. pushed a fix -- To view, visit https://review.coreboot.org/c/coreboot/+/59701 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I78126cb710a6ee674b58b35c8294685a5965ecd6 Gerrit-Change-Number: 59701 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Mon, 29 Nov 2021 20:38:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: src/cpu,soc/amd/common/block/cpu: Add preload_microcode
by Karthik Ramasubramanian (Code Review) 29 Nov '21

29 Nov '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Paul Menzel, Rob Barnes, Felix Held. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58963 ) Change subject: src/cpu,soc/amd/common/block/cpu: Add preload_microcode ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/58963 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If0c634c692c97769e71acd1175fc464dc592c356 Gerrit-Change-Number: 58963 Gerrit-PatchSet: 4 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 29 Nov 2021 20:38:06 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/stoneyridge/psp: move soc_get_mbox_address to common psp_gen1
by Felix Held (Code Review) 29 Nov '21

29 Nov '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Paul Menzel, Felix Held. Hello Jason Glenesk, Raul Rangel, Marshall Dawson, Paul Menzel, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59701 to look at the new patch set (#3). Change subject: soc/amd/stoneyridge/psp: move soc_get_mbox_address to common psp_gen1 ...................................................................... soc/amd/stoneyridge/psp: move soc_get_mbox_address to common psp_gen1 Despite Stoneyridge being one only SoC in soc/amd that uses the first generation of the PSP mailblox interface, this code is common for all SoCs that use the first PSP mailbox interface generation, so move it to the common PSP generation 1 code. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I78126cb710a6ee674b58b35c8294685a5965ecd6 --- M src/soc/amd/common/block/include/amdblocks/psp.h M src/soc/amd/common/block/psp/psp_gen1.c M src/soc/amd/common/block/psp/psp_gen2.c M src/soc/amd/stoneyridge/include/soc/southbridge.h M src/soc/amd/stoneyridge/psp.c 5 files changed, 36 insertions(+), 34 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/59701/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/59701 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I78126cb710a6ee674b58b35c8294685a5965ecd6 Gerrit-Change-Number: 59701 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: drivers/gfx/generic: Add optional _HID for gfx devices
by Nick Vaccaro (Code Review) 29 Nov '21

29 Nov '21

Attention is currently required from: Tim Wawrzynczak, Rajat Jain. Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59730 ) Change subject: drivers/gfx/generic: Add optional _HID for gfx devices ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59730 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I32be4abf5c60be1f94aabaa2e9c734215c4e291e Gerrit-Change-Number: 59730 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Rajat Jain <rajatja(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Rajat Jain <rajatja(a)google.com> Gerrit-Comment-Date: Mon, 29 Nov 2021 20:36:29 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: intel: cse_lite: Use cbfs_unverified_area API
by Tim Wawrzynczak (Code Review) 29 Nov '21

29 Nov '21

Attention is currently required from: Raul Rangel, Julius Werner, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59679 ) Change subject: intel: cse_lite: Use cbfs_unverified_area API ...................................................................... Patch Set 2: Code-Review+2 (2 comments) Patchset: PS2: FYI there is more incoming..... https://review.coreboot.org/c/coreboot/+/59685/9 File src/soc/intel/common/block/cse/cse_lite.c: https://review.coreboot.org/c/coreboot/+/59679/comment/7e2de894_3160442b PS2, Line 676: cbfs_unverified_area_map > Ah, I think you wanted to avoid the vboot penalty on always hashing the firmware? It looks like the […] Yes, the vboot loading/hashing time penalty was too much to bear on every boot, so as you noticed, the hash is stored in FW_MAIN_A or _B and thus the root of trust is extended to the new region by verifying the hash matches the region (only when it is required to be accessed). Once verification is moved to access-time only, then yes we can move the file back into FW_MAIN_X and drop the extra hash file. -- To view, visit https://review.coreboot.org/c/coreboot/+/59679 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If4855280d6d06cf1aa646fded916fd830b287b30 Gerrit-Change-Number: 59679 Gerrit-PatchSet: 2 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 29 Nov 2021 20:35:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: acpi,Makefile: Add preload_acpi_dsdt
by Raul Rangel (Code Review) 29 Nov '21

29 Nov '21

Raul Rangel has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59504 ) Change subject: acpi,Makefile: Add preload_acpi_dsdt ...................................................................... acpi,Makefile: Add preload_acpi_dsdt This will allow us to preload the dsdt.aml file. BUG=b:179699789 TEST=Build guybrush | 80 - write tables | 1.564 | 1.08 Δ( -0.48, -0.03%) | | 85 - finalize chips | 15.483 | 13.543 Δ( -1.94, -0.14%) | Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: Ibf69ecb947811a2eec861018e3ba5f858155f1c3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59504 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M Makefile.inc M src/acpi/acpi.c M src/include/acpi/acpi.h 3 files changed, 15 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/Makefile.inc b/Makefile.inc index 1b1e973..090505e 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -280,6 +280,9 @@ $(CONFIG_CBFS_PREFIX)/$(1).aml-file = $(obj)/$(1).aml $(CONFIG_CBFS_PREFIX)/$(1).aml-type = raw $(CONFIG_CBFS_PREFIX)/$(1).aml-compression = none +ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA),y) +$(CONFIG_CBFS_PREFIX)/$(1).aml-align = 64 +endif cbfs-files-$(if $(2),$(2),y) += $(CONFIG_CBFS_PREFIX)/$(1).aml -include $(obj)/$(1).d $(obj)/$(1).aml: $(src)/mainboard/$(MAINBOARDDIR)/$(1).asl $(obj)/config.h diff --git a/src/acpi/acpi.c b/src/acpi/acpi.c index 78c3fd3..3bf57c6 100644 --- a/src/acpi/acpi.c +++ b/src/acpi/acpi.c @@ -1577,6 +1577,17 @@ return 0; } +void preload_acpi_dsdt(void) +{ + const char *file = CONFIG_CBFS_PREFIX "/dsdt.aml"; + + if (!CONFIG(CBFS_PRELOAD)) + return; + + printk(BIOS_DEBUG, "Preloading %s\n", file); + cbfs_preload(file); +} + unsigned long write_acpi_tables(unsigned long start) { unsigned long current; diff --git a/src/include/acpi/acpi.h b/src/include/acpi/acpi.h index 4f059bb..4a95855 100644 --- a/src/include/acpi/acpi.h +++ b/src/include/acpi/acpi.h @@ -1215,6 +1215,7 @@ unsigned long fw_cfg_acpi_tables(unsigned long start); /* These are implemented by the target port or north/southbridge. */ +void preload_acpi_dsdt(void); unsigned long write_acpi_tables(unsigned long addr); unsigned long acpi_fill_madt(unsigned long current); unsigned long acpi_fill_ivrs_ioapic(acpi_ivrs_t *ivrs, unsigned long current); -- To view, visit https://review.coreboot.org/c/coreboot/+/59504 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibf69ecb947811a2eec861018e3ba5f858155f1c3 Gerrit-Change-Number: 59504 Gerrit-PatchSet: 3 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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coreboot-gerrit November 2021