coreboot-gerrit November 2021

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/amd/*: PSP verstage minbuild
by Felix Held (Code Review) 29 Nov '21

29 Nov '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Martin Roth, Marshall Dawson. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59585 ) Change subject: soc/amd/*: PSP verstage minbuild ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/59585/comment/b048bf27_d7c1d46f PS2, Line 9: The PSP that is supplied for Picasso AMD-based chromebooks currently : requires a psp_verstage to boot > :( this seems unfortunate. […] i have a non-chromebook picasso apu on my mandolin board and it doesn't require (or support) verstage on psp. definitely boots without verstage -- To view, visit https://review.coreboot.org/c/coreboot/+/59585 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie506193d21207ecabe65158e84dc02eec1cf5b26 Gerrit-Change-Number: 59585 Gerrit-PatchSet: 2 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Comment-Date: Mon, 29 Nov 2021 22:03:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc: Add dram information to cbmem
by mturney mturney (Code Review) 29 Nov '21

29 Nov '21

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Change in coreboot[master]: soc: Add dram information to cbmem
by mturney mturney (Code Review) 29 Nov '21

29 Nov '21

Attention is currently required from: Ravi kumar, Shelley Chen, mturney mturney, Julius Werner. mturney mturney has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59195 ) Change subject: soc: Add dram information to cbmem ...................................................................... Patch Set 6: (1 comment) File src/soc/qualcomm/common/qclib.c: https://review.coreboot.org/c/coreboot/+/59195/comment/825f60ff_9bb107ac PS5, Line 174: mem_chip_info > This pointer is still NULL here, how is this supposed to work? The global variable needs to be an ac […] Julius, This is correct as we have written it, though it may not be what you are expecting. The call to qclib_add_if_table_entry() is required to add the MEM_CHIP_INFO table entry, which is important so QcLib can actually fill in the address/size and mark the entry as dirty so it gets written back after the QcLib call. Note that what is important here is the table entry, not the data in the table entry. Each table entry contains an address and a size, as well as the flag field that indicates the buffer is dirty and needs to be saved. If CB was passing data to QcLib, you are correct that this would be a problem as written. The buffer used is allocated by QcLib in a region that is visible to CB (SMEM) and the DDR code performing the initialization. A buffer allocated by CB and passed to QcLib may not be accessible by the DDR code. In this case QcLib does not use the data passed in for this entry and uses the table entry to provide valid data back to CB. If you look at the write-back function I think you will see it is using the address/size passed back from QcLib to allocate the CBMEM buffer and then copy actual data to the CBMEM buffer. -- To view, visit https://review.coreboot.org/c/coreboot/+/59195 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0f1dd05ee224bf8284661c0afaa01d0a9d71daa7 Gerrit-Change-Number: 59195 Gerrit-PatchSet: 6 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-Reviewer: mturney mturney <quic_mturney(a)quicinc.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Mon, 29 Nov 2021 21:58:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: Documentation: Add template for deprecation notices
by Felix Singer (Code Review) 29 Nov '21

29 Nov '21

Attention is currently required from: Mike Banon, Patrick Georgi, Branden Waldner, Martin Roth, awokd(a)danwin1210.me, Paul Menzel, Angel Pons, Arthur Heymans. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59677 ) Change subject: Documentation: Add template for deprecation notices ...................................................................... Patch Set 2: Code-Review+1 (4 comments) File Documentation/releases/templates.md: https://review.coreboot.org/c/coreboot/+/59677/comment/450d48d4_a9f8d490 PS2, Line 6: down the road (must cover at least 6 months from : the release that comes with the notice) some part of coreboot I feel like there is missing something before/after the brackets. https://review.coreboot.org/c/coreboot/+/59677/comment/32ee2d0c_7dbefda3 PS2, Line 10: helps keep helps *to* keep https://review.coreboot.org/c/coreboot/+/59677/comment/1b1885fd_1f61e4ce PS2, Line 11: improving improve https://review.coreboot.org/c/coreboot/+/59677/comment/d7d8affa_310f3239 PS2, Line 47: #### Call to action Add new line here -- To view, visit https://review.coreboot.org/c/coreboot/+/59677 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia2cc4f799804c7d56db572823246c487cd19a726 Gerrit-Change-Number: 59677 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Mike Banon <mikebdp2(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: awokd(a)danwin1210.me Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Branden Waldner <scruffy99(a)gmail.com> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Mike Banon <mikebdp2(a)gmail.com> Gerrit-Attention: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Attention: Branden Waldner <scruffy99(a)gmail.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: awokd(a)danwin1210.me Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Mike Banon <mikebdp2(a)gmail.com> Gerrit-Comment-Date: Mon, 29 Nov 2021 21:54:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: src/security/vboot: Set up secure counter space in TPM NVRAM
by Raul Rangel (Code Review) 29 Nov '21

29 Nov '21

Attention is currently required from: Andrey Pronin, Paul Menzel, Julius Werner, Yu-Ping Wu, Karthik Ramasubramanian. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59476 ) Change subject: src/security/vboot: Set up secure counter space in TPM NVRAM ...................................................................... Patch Set 6: Code-Review+1 (1 comment) File src/security/vboot/Kconfig: https://review.coreboot.org/c/coreboot/+/59476/comment/b1fe1b70_81c41950 PS6, Line 289: Entities that : use these counters increment them in the first use-case "first use-case"? I think I would remove the sentence. -- To view, visit https://review.coreboot.org/c/coreboot/+/59476 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I915fbdada60e242d911b748ad5dc28028de9b657 Gerrit-Change-Number: 59476 Gerrit-PatchSet: 6 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Andrey Pronin <apronin(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Andrey Pronin <apronin(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Andrey Pronin <apronin(a)google.com> Gerrit-Attention: Andrey Pronin <apronin(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Mon, 29 Nov 2021 21:43:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: src/security/vboot: Set up secure counter space in TPM NVRAM
by Karthik Ramasubramanian (Code Review) 29 Nov '21

29 Nov '21

Attention is currently required from: Andrey Pronin, Raul Rangel, Paul Menzel, Julius Werner, Yu-Ping Wu. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59476 ) Change subject: src/security/vboot: Set up secure counter space in TPM NVRAM ...................................................................... Patch Set 6: (1 comment) File src/security/vboot/secure_counter.h: https://review.coreboot.org/c/coreboot/+/59476/comment/b5fdf012_1af07c01 PS1, Line 11: 0x100f > Is this a google specific or cr50 specific number? Should we pass these in via a Kconfig instead? Defined the indices in a use-case specific way. Also a config item has been defined to configure the use-case. -- To view, visit https://review.coreboot.org/c/coreboot/+/59476 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I915fbdada60e242d911b748ad5dc28028de9b657 Gerrit-Change-Number: 59476 Gerrit-PatchSet: 6 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Andrey Pronin <apronin(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Andrey Pronin <apronin(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Andrey Pronin <apronin(a)google.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Andrey Pronin <apronin(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Mon, 29 Nov 2021 21:20:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: rules.h, thread.h, lib/cbfs: Add ENV_STAGE_SUPPORTS_COOP
by Raul Rangel (Code Review) 29 Nov '21

29 Nov '21

Attention is currently required from: Julius Werner. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59550 ) Change subject: rules.h, thread.h, lib/cbfs: Add ENV_STAGE_SUPPORTS_COOP ...................................................................... Patch Set 1: (2 comments) File src/include/rules.h: https://review.coreboot.org/c/coreboot/+/59550/comment/a5ba2858_9369d4bd PS1, Line 306: ENV_X86 > Why check this explicitly? It currently only works on x86 but that's already modeled by the Kconfig, […] My goal is to remove `(ENV_RAMSTAGE || ENV_ROMSTAGE)` eventually. I need to do some analysis on why the threading code isn't getting garbage collected when nothing calls it. But once I get rid of the stage requirement this means we can use threading in verstage, so I need the ENV_X86 guard to account for PSP verstage. https://review.coreboot.org/c/coreboot/+/59550/comment/101ea79a_512fb94a PS1, Line 306: ENV_ROMSTAGE > I just realized there may be a bit of an issue with preloading in romstage in combination with VBOOT […] When cbfs_preload executes it stores a copy of the rdev. This should in theory be the "RO" rdev. Once _cbfs_alloc gets called it will get the "RW" rdev. Is there metadata in the rdevs we can compare? We could then just throw out the preload if it didn't match. -- To view, visit https://review.coreboot.org/c/coreboot/+/59550 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1197406d1d36391998b08e3076146bb2fff59d00 Gerrit-Change-Number: 59550 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Mon, 29 Nov 2021 21:19:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: src/security/vboot: Set up secure counter space in TPM NVRAM
by Karthik Ramasubramanian (Code Review) 29 Nov '21

29 Nov '21

Attention is currently required from: Andrey Pronin, Raul Rangel, Paul Menzel, Julius Werner, Yu-Ping Wu. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59476 ) Change subject: src/security/vboot: Set up secure counter space in TPM NVRAM ...................................................................... Patch Set 6: (4 comments) File src/security/vboot/Kconfig: https://review.coreboot.org/c/coreboot/+/59476/comment/c9d6286f_0e47ca15 PS4, Line 289: Setup > Set up Done File src/security/vboot/antirollback.h: https://review.coreboot.org/c/coreboot/+/59476/comment/6dac73fa_26334582 PS3, Line 32: 0x100f > What about moving this a bit away from the other indices so it can grow on its own when necessary? M […] Done File src/security/vboot/antirollback.h: https://review.coreboot.org/c/coreboot/+/59476/comment/3d966f86_744b578e PS2, Line 39: SECURE_COUNTER1_NV_INDEX > Well, they aren't really (I think?), counters are part of the TPM 2.0 standard. Please refer below discussion. Marking it as resolved for now. https://review.coreboot.org/c/coreboot/+/59476/comment/85c27d55_f78e9c77 PS2, Line 42: #define SECURE_COUNTER4_NV_INDEX 0x1012 > Not really sure what you mean by cr50 specific. […] Since any index can be picked, this is not Cr50 specific. -- To view, visit https://review.coreboot.org/c/coreboot/+/59476 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I915fbdada60e242d911b748ad5dc28028de9b657 Gerrit-Change-Number: 59476 Gerrit-PatchSet: 6 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Andrey Pronin <apronin(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Andrey Pronin <apronin(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Andrey Pronin <apronin(a)google.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Andrey Pronin <apronin(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Mon, 29 Nov 2021 21:18:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: Documentation: Add template for deprecation notices
by Patrick Georgi (Code Review) 29 Nov '21

29 Nov '21

Attention is currently required from: Mike Banon, Branden Waldner, Martin Roth, awokd(a)danwin1210.me, Paul Menzel, Angel Pons, Arthur Heymans. Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59677 ) Change subject: Documentation: Add template for deprecation notices ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/59677 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia2cc4f799804c7d56db572823246c487cd19a726 Gerrit-Change-Number: 59677 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Mike Banon <mikebdp2(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: awokd(a)danwin1210.me Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Branden Waldner <scruffy99(a)gmail.com> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Mike Banon <mikebdp2(a)gmail.com> Gerrit-Attention: Branden Waldner <scruffy99(a)gmail.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: awokd(a)danwin1210.me Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Mike Banon <mikebdp2(a)gmail.com> Gerrit-Comment-Date: Mon, 29 Nov 2021 21:18:23 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: src/security/vboot: Set up secure counter space in TPM NVRAM
by Karthik Ramasubramanian (Code Review) 29 Nov '21

29 Nov '21

Attention is currently required from: Andrey Pronin, Raul Rangel, Paul Menzel, Julius Werner, Yu-Ping Wu. Hello build bot (Jenkins), Andrey Pronin, Raul Rangel, Julius Werner, Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59476 to look at the new patch set (#6). Change subject: src/security/vboot: Set up secure counter space in TPM NVRAM ...................................................................... src/security/vboot: Set up secure counter space in TPM NVRAM High Definition (HD) protected content playback requires secure counters that are updated at regular interval while the protected content is playing. To support similar use-cases, define space for secure counters in TPM NVRAM and initialize them. These counters are defined once during the factory initialization stage. Also add VBOOT_DEFINE_WIDEVINE_COUNTERS config item to enable these secure counters only on the mainboard where they are required/used. BUG=b:205261728 TEST=Build and boot to OS in guybrush. Ensure that the secure counters are defined successfully in TPM NVRAM space. tlcl_define_space: response is 0 tlcl_define_space: response is 0 tlcl_define_space: response is 0 tlcl_define_space: response is 0 On reboot if forced to redefine the space, it is identified as already defined. tlcl_define_space: response is 14c define_space():219: define_space: Secure Counter space already exists tlcl_define_space: response is 14c define_space():219: define_space: Secure Counter space already exists tlcl_define_space: response is 14c define_space():219: define_space: Secure Counter space already exists tlcl_define_space: response is 14c define_space():219: define_space: Secure Counter space already exists Change-Id: I915fbdada60e242d911b748ad5dc28028de9b657 Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> --- M src/security/vboot/Kconfig M src/security/vboot/antirollback.h M src/security/vboot/secdata_tpm.c 3 files changed, 42 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/59476/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/59476 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I915fbdada60e242d911b748ad5dc28028de9b657 Gerrit-Change-Number: 59476 Gerrit-PatchSet: 6 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Andrey Pronin <apronin(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Andrey Pronin <apronin(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Andrey Pronin <apronin(a)google.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Andrey Pronin <apronin(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: newpatchset

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coreboot-gerrit November 2021