coreboot-gerrit November 2021

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Change in coreboot[master]: sc7280: Add support for USB
by Shelley Chen (Code Review) 30 Nov '21

30 Nov '21

Shelley Chen has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56092 ) Change subject: sc7280: Add support for USB ...................................................................... sc7280: Add support for USB Adding USB addressmap for sc7280. Use common USB driver for sc7280. BUG=b:182963902 TEST=Validated USB enumeration on qcom sc7280 development board Signed-off-by: Sandeep Maheswaram <sanm(a)codeaurora.org> Change-Id: Ib92b74c8035a8c0148a9aa48e7870b261b832a33 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56092 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- M src/soc/qualcomm/sc7280/Makefile.inc M src/soc/qualcomm/sc7280/include/soc/addressmap.h 2 files changed, 14 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Julius Werner: Looks good to me, approved diff --git a/src/soc/qualcomm/sc7280/Makefile.inc b/src/soc/qualcomm/sc7280/Makefile.inc index 72fb57f..6a02bdb 100644 --- a/src/soc/qualcomm/sc7280/Makefile.inc +++ b/src/soc/qualcomm/sc7280/Makefile.inc @@ -30,12 +30,16 @@ romstage-y += ../common/qclib.c romstage-y += ../common/mmu.c romstage-y += mmu.c +romstage-y += ../common/usb/usb.c romstage-$(CONFIG_DRIVERS_UART) += ../common/qupv3_uart.c ################################################################################ ramstage-y += soc.c ramstage-y += cbmem.c ramstage-$(CONFIG_DRIVERS_UART) += ../common/qupv3_uart.c +ramstage-y += ../common/usb/usb.c +ramstage-y += ../common/usb/snps_usb_phy.c +ramstage-y += ../common/usb/qmpv4_usb_phy.c ramstage-y += ../common/aop_load_reset.c ramstage-y += cpucp_load_reset.c diff --git a/src/soc/qualcomm/sc7280/include/soc/addressmap.h b/src/soc/qualcomm/sc7280/include/soc/addressmap.h index 8515a04..31f409f 100644 --- a/src/soc/qualcomm/sc7280/include/soc/addressmap.h +++ b/src/soc/qualcomm/sc7280/include/soc/addressmap.h @@ -58,4 +58,14 @@ #define EPSSTOP_EPSS_TOP 0x18598000 #define EPSSFAST_BASE_ADDR 0x18580000 +/* + * USB BASE ADDRESSES + */ +#define HS_USB_PRIM_PHY_BASE 0x088e3000 +#define QMP_PHY_QSERDES_COM_REG_BASE 0x088e9000 +#define QMP_PHY_QSERDES_TX_REG_BASE 0x088e9200 +#define QMP_PHY_QSERDES_RX_REG_BASE 0x088e9400 +#define QMP_PHY_PCS_REG_BASE 0x088e9c00 +#define USB_HOST_DWC3_BASE 0x0a60c100 + #endif /* __SOC_QUALCOMM_SC7280_ADDRESS_MAP_H__ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/56092 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib92b74c8035a8c0148a9aa48e7870b261b832a33 Gerrit-Change-Number: 56092 Gerrit-PatchSet: 42 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Sandeep Maheswaram <sanm(a)codeaurora.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: WIP: arch/{x86,riscv},smp: Delete spinlock.h
by Raul Rangel (Code Review) 30 Nov '21

30 Nov '21

Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59732 ) Change subject: WIP: arch/{x86,riscv},smp: Delete spinlock.h ...................................................................... WIP: arch/{x86,riscv},smp: Delete spinlock.h spinlock.h has been replaced with mutex.h. BUG=b:179699789 TEST=Boot guybrush to OS Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I0d204ea96cc843f1f10d152559a9ee06735623ef --- D src/arch/riscv/include/arch/smp/spinlock.h M src/arch/riscv/smp.c M src/arch/x86/cpu.c D src/arch/x86/include/arch/smp/spinlock.h D src/include/smp/spinlock.h 5 files changed, 0 insertions(+), 115 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/59732/1 diff --git a/src/arch/riscv/include/arch/smp/spinlock.h b/src/arch/riscv/include/arch/smp/spinlock.h deleted file mode 100644 index b316ff0..0000000 --- a/src/arch/riscv/include/arch/smp/spinlock.h +++ /dev/null @@ -1,28 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef ARCH_SMP_SPINLOCK_H -#define ARCH_SMP_SPINLOCK_H - -#include <arch/encoding.h> -#include <arch/smp/atomic.h> - -#define barrier() { asm volatile ("fence" ::: "memory"); } - -typedef struct { - atomic_t lock; -} spinlock_t; - -static inline void spinlock_lock(spinlock_t *lock) -{ - while (atomic_swap(&lock->lock, -1)) - ; - barrier(); -} - -static inline void spinlock_unlock(spinlock_t *lock) -{ - barrier(); - atomic_set(&lock->lock, 0); -} - -#endif // ARCH_SMP_SPINLOCK_H diff --git a/src/arch/riscv/smp.c b/src/arch/riscv/smp.c index 1d58602..3ffca44 100644 --- a/src/arch/riscv/smp.c +++ b/src/arch/riscv/smp.c @@ -2,7 +2,6 @@ #include <arch/encoding.h> #include <arch/smp/smp.h> -#include <arch/smp/spinlock.h> #include <mcall.h> #include <console/console.h> diff --git a/src/arch/x86/cpu.c b/src/arch/x86/cpu.c index f4cb83a..554aa2f 100644 --- a/src/arch/x86/cpu.c +++ b/src/arch/x86/cpu.c @@ -11,7 +11,6 @@ #include <cpu/x86/tsc.h> #include <device/path.h> #include <device/device.h> -#include <smp/spinlock.h> #if ENV_X86_32 /* Standard macro to see if a specific flag is changeable */ diff --git a/src/arch/x86/include/arch/smp/spinlock.h b/src/arch/x86/include/arch/smp/spinlock.h deleted file mode 100644 index c7008c1..0000000 --- a/src/arch/x86/include/arch/smp/spinlock.h +++ /dev/null @@ -1,70 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef ARCH_SMP_SPINLOCK_H -#define ARCH_SMP_SPINLOCK_H - -#include <thread.h> - -/* - * Your basic SMP spinlocks, allowing only a single CPU anywhere - */ - -typedef struct { - volatile unsigned int lock; -} spinlock_t; - -#define SPIN_LOCK_UNLOCKED { 1 } - -#define DECLARE_SPIN_LOCK(x) \ - static spinlock_t x = SPIN_LOCK_UNLOCKED; - -/* - * Simple spin lock operations. There are two variants, one clears IRQ's - * on the local processor, one does not. - * - * We make no fairness assumptions. They have a cost. - */ -#define barrier() __asm__ __volatile__("" : : : "memory") -#define spin_is_locked(x) (*(volatile char *)(&(x)->lock) <= 0) -#define spin_unlock_wait(x) do { barrier(); } while (spin_is_locked(x)) -#undef barrier - -#define spin_lock_string \ - "\n1:\t" \ - "lock ; decb %0\n\t" \ - "js 2f\n" \ - ".section .text.lock,\"ax\"\n" \ - "2:\t" \ - "cmpb $0,%0\n\t" \ - "rep;nop\n\t" \ - "jle 2b\n\t" \ - "jmp 1b\n" \ - ".previous" - -/* - * This works. Despite all the confusion. - */ -#define spin_unlock_string \ - "movb $1,%0" - -static __always_inline void spin_lock(spinlock_t *lock) -{ - __asm__ __volatile__( - spin_lock_string - : "=m" (lock->lock) : : "memory"); - - /* Switching contexts while holding a spinlock will lead to deadlocks */ - thread_coop_disable(); - -} - -static __always_inline void spin_unlock(spinlock_t *lock) -{ - thread_coop_enable(); - - __asm__ __volatile__( - spin_unlock_string - : "=m" (lock->lock) : : "memory"); -} - -#endif /* ARCH_SMP_SPINLOCK_H */ diff --git a/src/include/smp/spinlock.h b/src/include/smp/spinlock.h deleted file mode 100644 index 116830c..0000000 --- a/src/include/smp/spinlock.h +++ /dev/null @@ -1,15 +0,0 @@ -#ifndef SMP_SPINLOCK_H -#define SMP_SPINLOCK_H - -#if ENV_STAGE_SUPPORTS_SMP -#include <arch/smp/spinlock.h> -#else /* !CONFIG_SMP */ - -#define DECLARE_SPIN_LOCK(x) -#define spin_is_locked(lock) 0 -#define spin_unlock_wait(lock) do {} while (0) -#define spin_lock(lock) do {} while (0) -#define spin_unlock(lock) do {} while (0) -#endif - -#endif /* SMP_SPINLOCK_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/59732 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0d204ea96cc843f1f10d152559a9ee06735623ef Gerrit-Change-Number: 59732 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/qualcomm/common/usb: Add support for common USB driver
by Shelley Chen (Code Review) 30 Nov '21

30 Nov '21

Shelley Chen has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56091 ) Change subject: soc/qualcomm/common/usb: Add support for common USB driver ...................................................................... soc/qualcomm/common/usb: Add support for common USB driver Add common USB driver for qualcomm soc sc7180 and sc7280. This includes dwc3 controller, qmp ss phy, qusb hs phy and snsp hs phy. BUG=b:182963902 TEST=Validated USB enumeration on qcom sc7180 and sc7280 development board Signed-off-by: Sandeep Maheswaram <sanm(a)codeaurora.org> Change-Id: I1013ded22855286220cfa747cb25418070fe85a7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56091 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- M src/mainboard/google/trogdor/mainboard.c M src/mainboard/google/trogdor/romstage.c A src/soc/qualcomm/common/include/soc/usb/qmp_usb_phy.h A src/soc/qualcomm/common/include/soc/usb/qusb_phy.h A src/soc/qualcomm/common/include/soc/usb/snps_usb_phy.h A src/soc/qualcomm/common/include/soc/usb/usb_common.h R src/soc/qualcomm/common/usb/qmpv3_usb_phy.c A src/soc/qualcomm/common/usb/qmpv4_usb_phy.c A src/soc/qualcomm/common/usb/qusb_phy.c A src/soc/qualcomm/common/usb/snps_usb_phy.c A src/soc/qualcomm/common/usb/usb.c M src/soc/qualcomm/sc7180/Makefile.inc D src/soc/qualcomm/sc7180/include/soc/usb.h 13 files changed, 1,005 insertions(+), 417 deletions(-) Approvals: build bot (Jenkins): Verified Julius Werner: Looks good to me, approved diff --git a/src/mainboard/google/trogdor/mainboard.c b/src/mainboard/google/trogdor/mainboard.c index cfc811d..ea180a8 100644 --- a/src/mainboard/google/trogdor/mainboard.c +++ b/src/mainboard/google/trogdor/mainboard.c @@ -18,9 +18,8 @@ #include <soc/qup_se_handlers_common.h> #include <soc/qupv3_i2c_common.h> #include <soc/qcom_qup_se.h> -#include <soc/usb.h> -#include <types.h> - +#include <soc/usb/usb_common.h> +#include <soc/usb/qusb_phy.h> #include "board.h" #include <soc/addressmap.h> diff --git a/src/mainboard/google/trogdor/romstage.c b/src/mainboard/google/trogdor/romstage.c index e110460..01bd530 100644 --- a/src/mainboard/google/trogdor/romstage.c +++ b/src/mainboard/google/trogdor/romstage.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <arch/stages.h> -#include <soc/usb.h> +#include <soc/usb/usb_common.h> #include <soc/qclib_common.h> #include <soc/watchdog.h> diff --git a/src/soc/qualcomm/common/include/soc/usb/qmp_usb_phy.h b/src/soc/qualcomm/common/include/soc/usb/qmp_usb_phy.h new file mode 100644 index 0000000..fc1721a --- /dev/null +++ b/src/soc/qualcomm/common/include/soc/usb/qmp_usb_phy.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/mmio.h> +#include <console/console.h> + +/* USB3PHY_PCIE_USB3_PCS_PCS_STATUS bit */ +#define USB3_PCS_PHYSTATUS BIT(6) + +struct qmp_phy_init_tbl { + u32 *address; + u32 val; +}; + +struct ss_usb_phy_reg { + /* Init sequence for QMP PHY blocks - serdes, tx, rx, pcs */ + const struct qmp_phy_init_tbl *serdes_tbl; + int serdes_tbl_num; + + const struct qmp_phy_init_tbl *tx_tbl; + int tx_tbl_num; + + const struct qmp_phy_init_tbl *rx_tbl; + int rx_tbl_num; + + const struct qmp_phy_init_tbl *pcs_tbl; + int pcs_tbl_num; + + struct usb3_phy_pcs_reg_layout *qmp_pcs_reg; +}; + +void ss_qmp_phy_init(void); diff --git a/src/soc/qualcomm/common/include/soc/usb/qusb_phy.h b/src/soc/qualcomm/common/include/soc/usb/qusb_phy.h new file mode 100644 index 0000000..dd4a736 --- /dev/null +++ b/src/soc/qualcomm/common/include/soc/usb/qusb_phy.h @@ -0,0 +1,96 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/mmio.h> +#include <console/console.h> + +#define PORT_TUNE1_MASK 0xf0 + +/* QUSB2PHY_PWR_CTRL1 register related bits */ +#define POWER_DOWN BIT(0) + +/* DEBUG_CTRL2 register value to program VSTATUS MUX for PHY status */ +#define DEBUG_CTRL2_MUX_PLL_LOCK_STATUS 0x4 + +/* STAT5 register bits */ +#define VSTATUS_PLL_LOCK_STATUS_MASK BIT(0) + +/* QUSB PHY register values */ +#define QUSB2PHY_PLL_ANALOG_CONTROLS_TWO 0x03 +#define QUSB2PHY_PLL_CLOCK_INVERTERS 0x7c +#define QUSB2PHY_PLL_CMODE 0x80 +#define QUSB2PHY_PLL_LOCK_DELAY 0x0a +#define QUSB2PHY_PLL_DIGITAL_TIMERS_TWO 0x19 +#define QUSB2PHY_PLL_BIAS_CONTROL_1 0x40 +#define QUSB2PHY_PLL_BIAS_CONTROL_2 0x22 +#define QUSB2PHY_PWR_CTRL2 0x21 +#define QUSB2PHY_IMP_CTRL1 0x08 +#define QUSB2PHY_IMP_CTRL2 0x58 +#define QUSB2PHY_PORT_TUNE1 0xc5 +#define QUSB2PHY_PORT_TUNE2 0x29 +#define QUSB2PHY_PORT_TUNE3 0xca +#define QUSB2PHY_PORT_TUNE4 0x04 +#define QUSB2PHY_PORT_TUNE5 0x03 +#define QUSB2PHY_CHG_CTRL2 0x30 + + +#define QFPROM_BASE 0x00780000 +#define QUSB_PRIM_PHY_BASE 0x088e3000 +#define QUSB_PRIM_PHY_DIG_BASE 0x088e3200 + +#define HS_USB_PRIM_PHY_BASE QUSB_PRIM_PHY_BASE + +struct usb_board_data { + /* Register values going to override from the boardfile */ + u32 pll_bias_control_2; + u32 imp_ctrl1; + u32 port_tune1; +}; + +struct usb_qusb_phy_dig { + u8 rsvd1[16]; + u32 pwr_ctrl1; + u32 pwr_ctrl2; + u8 rsvd2[8]; + u32 imp_ctrl1; + u32 imp_ctrl2; + u8 rsvd3[20]; + u32 chg_ctrl2; + u32 tune1; + u32 tune2; + u32 tune3; + u32 tune4; + u32 tune5; + u8 rsvd4[44]; + u32 debug_ctrl2; + u8 rsvd5[28]; + u32 debug_stat5; +}; +check_member(usb_qusb_phy_dig, tune5, 0x50); +check_member(usb_qusb_phy_dig, debug_ctrl2, 0x80); +check_member(usb_qusb_phy_dig, debug_stat5, 0xA0); + +struct usb_qusb_phy_pll { + u8 rsvd0[4]; + u32 analog_controls_two; + u8 rsvd1[36]; + u32 cmode; + u8 rsvd2[132]; + u32 dig_tim; + u8 rsvd3[204]; + u32 lock_delay; + u8 rsvd4[4]; + u32 clock_inverters; + u8 rsvd5[4]; + u32 bias_ctrl_1; + u32 bias_ctrl_2; +}; +check_member(usb_qusb_phy_pll, cmode, 0x2C); +check_member(usb_qusb_phy_pll, bias_ctrl_2, 0x198); +check_member(usb_qusb_phy_pll, dig_tim, 0xB4); + +struct hs_usb_phy_reg { + struct usb_qusb_phy_pll *phy_pll; + struct usb_qusb_phy_dig *phy_dig; + struct usb_board_data *board_data; + u32 efuse_offset; +}; diff --git a/src/soc/qualcomm/common/include/soc/usb/snps_usb_phy.h b/src/soc/qualcomm/common/include/soc/usb/snps_usb_phy.h new file mode 100644 index 0000000..de0b385 --- /dev/null +++ b/src/soc/qualcomm/common/include/soc/usb/snps_usb_phy.h @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/mmio.h> +#include <console/console.h> + +struct usb_board_data { + /*Register values going to override from the boardfile*/ + u8 parameter_override_x0; + u8 parameter_override_x1; + u8 parameter_override_x2; + u8 parameter_override_x3; +}; + +struct hs_usb_phy_reg { + u8 rsvd1[60]; + u32 utmi_ctrl0; + u32 utmi_ctrl1; + u8 rsvd2[12]; + u32 utmi_ctrl5; + u32 hs_phy_ctrl_common0; + u32 hs_phy_ctrl_common1; + u32 hs_phy_ctrl_common2; + u32 hs_phy_ctrl1; + u32 hs_phy_ctrl2; + u8 rsvd3[4]; + u32 hs_phy_override_x0; + u32 hs_phy_override_x1; + u32 hs_phy_override_x2; + u32 hs_phy_override_x3; + u8 rsvd4[24]; + u32 cfg0; + u8 rsvd5[8]; + u32 refclk_ctrl; +}; +check_member(hs_usb_phy_reg, utmi_ctrl0, 0x03c); +check_member(hs_usb_phy_reg, utmi_ctrl1, 0x040); +check_member(hs_usb_phy_reg, utmi_ctrl5, 0x050); +check_member(hs_usb_phy_reg, hs_phy_ctrl2, 0x064); +check_member(hs_usb_phy_reg, hs_phy_override_x0, 0x06c); +check_member(hs_usb_phy_reg, hs_phy_override_x3, 0x078); +check_member(hs_usb_phy_reg, cfg0, 0x094); +check_member(hs_usb_phy_reg, refclk_ctrl, 0x0a0); diff --git a/src/soc/qualcomm/common/include/soc/usb/usb_common.h b/src/soc/qualcomm/common/include/soc/usb/usb_common.h new file mode 100644 index 0000000..662d488 --- /dev/null +++ b/src/soc/qualcomm/common/include/soc/usb/usb_common.h @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include "qmp_usb_phy.h" + +/* QSCRATCH_GENERAL_CFG register bit offset */ +#define PIPE_UTMI_CLK_SEL BIT(0) +#define PIPE3_PHYSTATUS_SW BIT(3) +#define PIPE_UTMI_CLK_DIS BIT(8) + +/* Global USB3 Control Registers */ +#define DWC3_GUSB3PIPECTL_DELAYP1TRANS BIT(18) +#define DWC3_GUSB3PIPECTL_UX_EXIT_IN_PX BIT(27) +#define DWC3_GCTL_PRTCAPDIR(n) ((n) << 12) +#define DWC3_GCTL_PRTCAP_OTG 3 +#define DWC3_GCTL_PRTCAP_HOST 1 + +/* Global USB2 PHY Configuration Register */ +#define DWC3_GUSB2PHYCFG_USBTRDTIM(n) ((n) << 10) +#define DWC3_GUSB2PHYCFG_USB2TRDTIM_MASK DWC3_GUSB2PHYCFG_USBTRDTIM(0xf) +#define DWC3_GUSB2PHYCFG_PHYIF(n) ((n) << 3) +#define DWC3_GUSB2PHYCFG_PHYIF_MASK DWC3_GUSB2PHYCFG_PHYIF(1) +#define USBTRDTIM_UTMI_8_BIT 9 +#define UTMI_PHYIF_8_BIT 0 + +#define DWC3_GCTL_SCALEDOWN(n) ((n) << 4) +#define DWC3_GCTL_SCALEDOWN_MASK DWC3_GCTL_SCALEDOWN(3) +#define DWC3_GCTL_DISSCRAMBLE (1 << 3) +#define DWC3_GCTL_U2EXIT_LFPS (1 << 2) +#define DWC3_GCTL_DSBLCLKGTNG (1 << 0) + +void hs_usb_phy_init(void *board_data); +void setup_usb_host0(void *board_data); + +/* Call reset_ before setup_ */ +void reset_usb0(void); diff --git a/src/soc/qualcomm/sc7180/usb.c b/src/soc/qualcomm/common/usb/qmpv3_usb_phy.c similarity index 63% rename from src/soc/qualcomm/sc7180/usb.c rename to src/soc/qualcomm/common/usb/qmpv3_usb_phy.c index 370fa66..fc560ff 100644 --- a/src/soc/qualcomm/sc7180/usb.c +++ b/src/soc/qualcomm/common/usb/qmpv3_usb_phy.c @@ -1,54 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <console/console.h> -#include <device/mmio.h> -#include <soc/usb.h> -#include <soc/clock.h> -#include <soc/addressmap.h> -#include <soc/efuse.h> #include <timer.h> - -struct usb_qusb_phy_dig { - u8 rsvd1[16]; - u32 pwr_ctrl1; - u32 pwr_ctrl2; - u8 rsvd2[8]; - u32 imp_ctrl1; - u32 imp_ctrl2; - u8 rsvd3[20]; - u32 chg_ctrl2; - u32 tune1; - u32 tune2; - u32 tune3; - u32 tune4; - u32 tune5; - u8 rsvd4[44]; - u32 debug_ctrl2; - u8 rsvd5[28]; - u32 debug_stat5; -}; -check_member(usb_qusb_phy_dig, tune5, 0x50); -check_member(usb_qusb_phy_dig, debug_ctrl2, 0x80); -check_member(usb_qusb_phy_dig, debug_stat5, 0xA0); - -struct usb_qusb_phy_pll { - u8 rsvd0[4]; - u32 analog_controls_two; - u8 rsvd1[36]; - u32 cmode; - u8 rsvd2[132]; - u32 dig_tim; - u8 rsvd3[204]; - u32 lock_delay; - u8 rsvd4[4]; - u32 clock_inverters; - u8 rsvd5[4]; - u32 bias_ctrl_1; - u32 bias_ctrl_2; -}; -check_member(usb_qusb_phy_pll, cmode, 0x2C); -check_member(usb_qusb_phy_pll, bias_ctrl_2, 0x198); -check_member(usb_qusb_phy_pll, dig_tim, 0xB4); +#include <soc/usb/qmp_usb_phy.h> +#include <soc/addressmap.h> /* Only for QMP V3 PHY - QSERDES COM registers */ struct usb3_phy_qserdes_com_reg_layout { @@ -290,41 +244,6 @@ static struct usb3_phy_pcs_reg_layout *const pcs_reg_layout = (void *)QMP_PHY_PCS_REG_BASE; -struct usb_dwc3 { - u32 sbuscfg0; - u32 sbuscfg1; - u32 txthrcfg; - u32 rxthrcfg; - u32 ctl; - u32 pmsts; - u32 sts; - u32 uctl1; - u32 snpsid; - u32 gpio; - u32 uid; - u32 uctl; - u64 buserraddr; - u64 prtbimap; - u8 reserved1[32]; - u32 dbgfifospace; - u32 dbgltssm; - u32 dbglnmcc; - u32 dbgbmu; - u32 dbglspmux; - u32 dbglsp; - u32 dbgepinfo0; - u32 dbgepinfo1; - u64 prtbimap_hs; - u64 prtbimap_fs; - u8 reserved2[112]; - u32 usb2phycfg; - u8 reserved3[124]; - u32 usb2phyacc; - u8 reserved4[60]; - u32 usb3pipectl; - u8 reserved5[60]; -}; -check_member(usb_dwc3, usb3pipectl, 0x1c0); static const struct qmp_phy_init_tbl qmp_v3_usb3_serdes_tbl[] = { {&qserdes_com_reg_layout->com_pll_ivco, 0x07}, @@ -434,33 +353,7 @@ {&pcs_reg_layout->pcs_rxeqtraining_run_time, 0x13}, }; -struct usb_dwc3_cfg { - struct usb_dwc3 *usb_host_dwc3; - struct usb_qusb_phy_pll *qusb_phy_pll; - struct usb_qusb_phy_dig *qusb_phy_dig; - /* Init sequence for QMP PHY blocks - serdes, tx, rx, pcs */ - const struct qmp_phy_init_tbl *serdes_tbl; - int serdes_tbl_num; - const struct qmp_phy_init_tbl *tx_tbl; - int tx_tbl_num; - const struct qmp_phy_init_tbl *rx_tbl; - int rx_tbl_num; - const struct qmp_phy_init_tbl *pcs_tbl; - int pcs_tbl_num; - struct usb3_phy_pcs_reg_layout *qmp_pcs_reg; - - u32 *usb3_bcr; - u32 *qusb2phy_bcr; - u32 *gcc_usb3phy_bcr_reg; - u32 *gcc_qmpphy_bcr_reg; - struct usb_board_data *board_data; - u32 efuse_offset; -}; - -static struct usb_dwc3_cfg usb_port0 = { - .usb_host_dwc3 = (void *)USB_HOST_DWC3_BASE, - .qusb_phy_pll = (void *)QUSB_PRIM_PHY_BASE, - .qusb_phy_dig = (void *)QUSB_PRIM_PHY_DIG_BASE, +struct ss_usb_phy_reg qmp_v3_usb_phy = { .serdes_tbl = qmp_v3_usb3_serdes_tbl, .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl), .tx_tbl = qmp_v3_usb3_tx_tbl, @@ -470,155 +363,8 @@ .pcs_tbl = qmp_v3_usb3_pcs_tbl, .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl), .qmp_pcs_reg = (void *)QMP_PHY_PCS_REG_BASE, - .usb3_bcr = &gcc->usb30_prim_bcr, - .qusb2phy_bcr = &gcc->qusb2phy_prim_bcr, - .gcc_usb3phy_bcr_reg = &gcc->usb3_dp_phy_prim_bcr, - .gcc_qmpphy_bcr_reg = &gcc->usb3_phy_prim_bcr, - .efuse_offset = 25, }; -static struct qfprom_corr * const qfprom_corr_efuse = (void *)QFPROM_BASE; - -static void reset_usb(struct usb_dwc3_cfg *dwc3) -{ - /* Assert Core reset */ - clock_reset_bcr(dwc3->usb3_bcr, 1); - - /* Assert QUSB PHY reset */ - clock_reset_bcr(dwc3->qusb2phy_bcr, 1); - - /* Assert QMP PHY reset */ - clock_reset_bcr(dwc3->gcc_usb3phy_bcr_reg, 1); - clock_reset_bcr(dwc3->gcc_qmpphy_bcr_reg, 1); -} - -void reset_usb0(void) -{ - /* Before Resetting PHY, put Core in Reset */ - printk(BIOS_INFO, "Starting DWC3 and PHY resets for USB(0)\n"); - - reset_usb(&usb_port0); -} - -/* - * Update board specific PHY tuning override values that specified from - * board file. - */ -static void qusb2_phy_override_phy_params(struct usb_dwc3_cfg *dwc3) -{ - /* Override preemphasis value */ - write32(&dwc3->qusb_phy_dig->tune1, - dwc3->board_data->port_tune1); - - /* Override BIAS_CTRL_2 to reduce the TX swing overshooting. */ - write32(&dwc3->qusb_phy_pll->bias_ctrl_2, - dwc3->board_data->pll_bias_control_2); - - /* Override IMP_RES_OFFSET value */ - write32(&dwc3->qusb_phy_dig->imp_ctrl1, - dwc3->board_data->imp_ctrl1); -} - -/* - * Fetches HS Tx tuning value from efuse register and sets the - * QUSB2PHY_PORT_TUNE1/2 register. - * For error case, skip setting the value and use the default value. - */ -static void qusb2_phy_set_tune_param(struct usb_dwc3_cfg *dwc3) -{ - /* - * Efuse registers 3 bit value specifies tuning for HSTX - * output current in TUNE1 Register. Hence Extract 3 bits from - * EFUSE at correct position. - */ - - const int efuse_bits = 3; - int bit_pos = dwc3->efuse_offset; - - u32 bit_mask = (1 << efuse_bits) - 1; - u32 tune_val = - (read32(&qfprom_corr_efuse->qusb_hstx_trim_lsb) >> bit_pos) - & bit_mask; - /* - * if efuse reg is updated (i.e non-zero) then use it to program - * tune parameters. - */ - if (tune_val) - clrsetbits32(&dwc3->qusb_phy_dig->tune1, - PORT_TUNE1_MASK, tune_val << 4); -} - -static void tune_phy(struct usb_dwc3_cfg *dwc3, struct usb_qusb_phy_dig *phy) -{ - write32(&phy->pwr_ctrl2, QUSB2PHY_PWR_CTRL2); - /* IMP_CTRL1: Control the impedance reduction */ - write32(&phy->imp_ctrl1, QUSB2PHY_IMP_CTRL1); - /* IMP_CTRL2: Impedance offset/mapping slope */ - write32(&phy->imp_ctrl2, QUSB2PHY_IMP_CTRL1); - write32(&phy->chg_ctrl2, QUSB2PHY_IMP_CTRL2); - /* - * TUNE1: Sets HS Impedance to approx 45 ohms - * then override with efuse value. - */ - write32(&phy->tune1, QUSB2PHY_PORT_TUNE1); - /* TUNE2: Tuning for HS Disconnect Level */ - write32(&phy->tune2, QUSB2PHY_PORT_TUNE2); - /* TUNE3: Tune squelch range */ - write32(&phy->tune3, QUSB2PHY_PORT_TUNE3); - /* TUNE4: Sets EOP_DLY(Squelch rising edge to linestate falling edge) */ - write32(&phy->tune4, QUSB2PHY_PORT_TUNE4); - write32(&phy->tune5, QUSB2PHY_PORT_TUNE5); - - if (dwc3->board_data) { - /* Override board specific PHY tuning values */ - qusb2_phy_override_phy_params(dwc3); - - /* Set efuse value for tuning the PHY */ - qusb2_phy_set_tune_param(dwc3); - } -} - -static void hs_qusb_phy_init(struct usb_dwc3_cfg *dwc3) -{ - /* PWR_CTRL: set the power down bit to disable the PHY */ - setbits32(&dwc3->qusb_phy_dig->pwr_ctrl1, POWER_DOWN); - - write32(&dwc3->qusb_phy_pll->analog_controls_two, - QUSB2PHY_PLL_ANALOG_CONTROLS_TWO); - write32(&dwc3->qusb_phy_pll->clock_inverters, - QUSB2PHY_PLL_CLOCK_INVERTERS); - write32(&dwc3->qusb_phy_pll->cmode, - QUSB2PHY_PLL_CMODE); - write32(&dwc3->qusb_phy_pll->lock_delay, - QUSB2PHY_PLL_LOCK_DELAY); - write32(&dwc3->qusb_phy_pll->dig_tim, - QUSB2PHY_PLL_DIGITAL_TIMERS_TWO); - write32(&dwc3->qusb_phy_pll->bias_ctrl_1, - QUSB2PHY_PLL_BIAS_CONTROL_1); - write32(&dwc3->qusb_phy_pll->bias_ctrl_2, - QUSB2PHY_PLL_BIAS_CONTROL_2); - - tune_phy(dwc3, dwc3->qusb_phy_dig); - - /* PWR_CTRL1: Clear the power down bit to enable the PHY */ - clrbits32(&dwc3->qusb_phy_dig->pwr_ctrl1, POWER_DOWN); - - write32(&dwc3->qusb_phy_dig->debug_ctrl2, - DEBUG_CTRL2_MUX_PLL_LOCK_STATUS); - - /* - * DEBUG_STAT5: wait for 160uS for PLL lock; - * vstatus[0] changes from 0 to 1. - */ - long lock_us = wait_us(160, read32(&dwc3->qusb_phy_dig->debug_stat5) & - VSTATUS_PLL_LOCK_STATUS_MASK); - if (!lock_us) - printk(BIOS_ERR, "ERROR: QUSB PHY PLL LOCK fails\n"); - else - printk(BIOS_DEBUG, "QUSB PHY initialized and locked in %ldus\n", - lock_us); -} - static void qcom_qmp_phy_configure(const struct qmp_phy_init_tbl tbl[], int num) { @@ -632,30 +378,34 @@ write32(t->address, t->val); } -static void ss_qmp_phy_init(struct usb_dwc3_cfg *dwc3) +void ss_qmp_phy_init(void) { + struct ss_usb_phy_reg *ss_phy_reg; + + ss_phy_reg = &qmp_v3_usb_phy; /* power up USB3 PHY */ - write32(&dwc3->qmp_pcs_reg->pcs_power_down_control, 0x01); + write32(&ss_phy_reg->qmp_pcs_reg->pcs_power_down_control, 0x01); /* Serdes configuration */ - qcom_qmp_phy_configure(dwc3->serdes_tbl, dwc3->serdes_tbl_num); + qcom_qmp_phy_configure(ss_phy_reg->serdes_tbl, + ss_phy_reg->serdes_tbl_num); /* Tx, Rx, and PCS configurations */ - qcom_qmp_phy_configure(dwc3->tx_tbl, dwc3->tx_tbl_num); - qcom_qmp_phy_configure(dwc3->rx_tbl, dwc3->rx_tbl_num); - qcom_qmp_phy_configure(dwc3->pcs_tbl, dwc3->pcs_tbl_num); + qcom_qmp_phy_configure(ss_phy_reg->tx_tbl, ss_phy_reg->tx_tbl_num); + qcom_qmp_phy_configure(ss_phy_reg->rx_tbl, ss_phy_reg->rx_tbl_num); + qcom_qmp_phy_configure(ss_phy_reg->pcs_tbl, ss_phy_reg->pcs_tbl_num); /* perform software reset of PCS/Serdes */ - write32(&dwc3->qmp_pcs_reg->pcs_sw_reset, 0x00); + write32(&ss_phy_reg->qmp_pcs_reg->pcs_sw_reset, 0x00); /* start PCS/Serdes to operation mode */ - write32(&dwc3->qmp_pcs_reg->pcs_start_control, 0x03); + write32(&ss_phy_reg->qmp_pcs_reg->pcs_start_control, 0x03); /* * Wait for PHY initialization to be done * PCS_STATUS: wait for 1ms for PHY STATUS; * SW can continuously check for PHYSTATUS = 1.b0. */ - long lock_us = wait_us(1000, - !(read32(&dwc3->qmp_pcs_reg->pcs_ready_status) & + long lock_us = wait_us(10000, + !(read32(&ss_phy_reg->qmp_pcs_reg->pcs_ready_status) & USB3_PCS_PHYSTATUS)); if (!lock_us) printk(BIOS_ERR, "ERROR: QMP PHY PLL LOCK fails:\n"); @@ -663,65 +413,3 @@ printk(BIOS_DEBUG, "QMP PHY initialized and locked in %ldus\n", lock_us); } - -static void setup_dwc3(struct usb_dwc3 *dwc3) -{ - /* core exits U1/U2/U3 only in PHY power state P1/P2/P3 respectively */ - clrsetbits32(&dwc3->usb3pipectl, - DWC3_GUSB3PIPECTL_DELAYP1TRANS, - DWC3_GUSB3PIPECTL_UX_EXIT_IN_PX); - - /* - * Configure USB phy interface of DWC3 core. - * 1. Select UTMI+ PHY with 16-bit interface. - * 2. Set USBTRDTIM to the corresponding value - * according to the UTMI+ PHY interface. - */ - clrsetbits32(&dwc3->usb2phycfg, - (DWC3_GUSB2PHYCFG_USB2TRDTIM_MASK | - DWC3_GUSB2PHYCFG_PHYIF_MASK), - (DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) | - DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT))); - - clrsetbits32(&dwc3->ctl, (DWC3_GCTL_SCALEDOWN_MASK | - DWC3_GCTL_DISSCRAMBLE), - DWC3_GCTL_U2EXIT_LFPS | DWC3_GCTL_DSBLCLKGTNG); - - /* configure controller in Host mode */ - clrsetbits32(&dwc3->ctl, (DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG)), - DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_HOST)); - printk(BIOS_SPEW, "Configure USB in Host mode\n"); -} - -/* Initialization of DWC3 Core and PHY */ -static void setup_usb_host(struct usb_dwc3_cfg *dwc3, - struct usb_board_data *board_data) -{ - dwc3->board_data = board_data; - - /* Clear core reset. */ - clock_reset_bcr(dwc3->usb3_bcr, 0); - - /* Clear QUSB PHY reset. */ - clock_reset_bcr(dwc3->qusb2phy_bcr, 0); - - /* Initialize QUSB PHY */ - hs_qusb_phy_init(dwc3); - - /* Clear QMP PHY resets. */ - clock_reset_bcr(dwc3->gcc_usb3phy_bcr_reg, 0); - clock_reset_bcr(dwc3->gcc_qmpphy_bcr_reg, 0); - - /* Initialize QMP PHY */ - ss_qmp_phy_init(dwc3); - - setup_dwc3(dwc3->usb_host_dwc3); - - printk(BIOS_INFO, "DWC3 and PHY setup finished\n"); -} - -void setup_usb_host0(struct usb_board_data *board_data) -{ - printk(BIOS_INFO, "Setting up USB HOST0 controller.\n"); - setup_usb_host(&usb_port0, board_data); -} diff --git a/src/soc/qualcomm/common/usb/qmpv4_usb_phy.c b/src/soc/qualcomm/common/usb/qmpv4_usb_phy.c new file mode 100644 index 0000000..031e2cf --- /dev/null +++ b/src/soc/qualcomm/common/usb/qmpv4_usb_phy.c @@ -0,0 +1,411 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <timer.h> +#include <soc/usb/qmp_usb_phy.h> +#include <soc/addressmap.h> + + +/* Only for QMP V4 PHY - QSERDES COM registers */ +struct usb3_phy_qserdes_com_reg_layout { + u8 _reserved1[16]; + u32 com_ssc_en_center; + u32 com_ssc_adj_per1; + u32 com_ssc_adj_per2; + u32 com_ssc_per1; + u32 com_ssc_per2; + u32 com_ssc_step_size1_mode0; + u32 com_ssc_step_size2_mode0; + u32 com_ssc_step_size3_mode0; + u32 com_ssc_step_size1_mode1; + u32 com_ssc_step_size2_mode1; + u32 com_ssc_step_size3_mode1; + u8 _reserved2[8]; + u32 com_bias_en_clkbuflr_en; + u32 com_sys_clk_enable1; + u32 com_sys_clk_ctrl; + u32 com_sysclk_buf_enable; + u32 com_pll_en; + u32 com_pll_ivco; + u8 _reserved3[4]; + u32 com_cmn_iptrim; + u8 _reserved4[16]; + u32 com_cp_ctrl_mode0; + u32 com_cp_ctrl_mode1; + u32 com_pll_rctrl_mode0; + u32 com_pll_rctrl_mode1; + u32 com_pll_cctrl_mode0; + u32 com_pll_cctrl_mode1; + u8 _reserved6[8]; + u32 com_sysclk_en_sel; + u8 _reserved7[8]; + u32 com_resetsm_ctrl2; + u32 com_lock_cmp_en; + u32 com_lock_cmp_cfg; + u32 com_lock_cmp1_mode0; + u32 com_lock_cmp2_mode0; + u32 com_lock_cmp1_mode1; + u32 com_lock_cmp2_mode1; + u32 com_dec_start_mode0; + u8 _reserved8[4]; + u32 com_dec_start_mode1; + u8 _reserved9[4]; + u32 com_div_frac_start1_mode0; + u32 com_div_frac_start2_mode0; + u32 com_div_frac_start3_mode0; + u32 com_div_frac_start1_mode1; + u32 com_div_frac_start2_mode1; + u32 com_div_frac_start3_mode1; + u8 _reserved10[8]; + u32 com_integloop_gain0_mode0; + u32 com_integloop_gain1_mode0; + u8 _reserved11[24]; + u32 com_vco_tune_map; + u32 com_vco_tune1_mode0; + u32 com_vco_tune2_mode0; + u32 com_vco_tune1_mode1; + u32 com_vco_tune2_mode1; + u8 _reserved12[52]; + u32 com_clk_select; + u32 com_hsclk_sel; + u8 _reserved13[12]; + u32 com_coreclk_div_mode0; + u32 com_coreclk_div_mode1; + u8 _reserved14[4]; + u32 com_core_clk_en; + u32 com_c_ready_status; + u32 com_cmn_config; + u32 com_cmn_rate_override; + u32 com_svs_mode_clk_sel; + u8 _reserved15[36]; + u32 com_bin_vcocal_cmp_code1_mode0; + u32 com_bin_vcocal_cmp_code2_mode0; + u32 com_bin_vcocal_cmp_code1_mode1; + u32 com_bin_vcocal_cmp_code2_mode1; + u32 com_bin_vcocal_hsclk_sel; +}; + +check_member(usb3_phy_qserdes_com_reg_layout, com_ssc_en_center, 0x010); +check_member(usb3_phy_qserdes_com_reg_layout, com_ssc_adj_per1, 0x014); +check_member(usb3_phy_qserdes_com_reg_layout, com_ssc_adj_per2, 0x018); +check_member(usb3_phy_qserdes_com_reg_layout, com_ssc_per1, 0x01c); +check_member(usb3_phy_qserdes_com_reg_layout, com_ssc_per2, 0x020); +check_member(usb3_phy_qserdes_com_reg_layout, com_bias_en_clkbuflr_en, 0x044); +check_member(usb3_phy_qserdes_com_reg_layout, com_pll_ivco, 0x058); +check_member(usb3_phy_qserdes_com_reg_layout, com_cp_ctrl_mode0, 0x074); +check_member(usb3_phy_qserdes_com_reg_layout, com_sysclk_en_sel, 0x094); +check_member(usb3_phy_qserdes_com_reg_layout, com_resetsm_ctrl2, 0x0a0); +check_member(usb3_phy_qserdes_com_reg_layout, com_dec_start_mode0, 0x0bc); +check_member(usb3_phy_qserdes_com_reg_layout, com_div_frac_start1_mode0, 0x0cc); +check_member(usb3_phy_qserdes_com_reg_layout, com_integloop_gain0_mode0, 0x0ec); +check_member(usb3_phy_qserdes_com_reg_layout, com_vco_tune_map, 0x010c); +check_member(usb3_phy_qserdes_com_reg_layout, com_clk_select, 0x154); +check_member(usb3_phy_qserdes_com_reg_layout, com_coreclk_div_mode0, 0x168); +check_member(usb3_phy_qserdes_com_reg_layout, com_core_clk_en, 0x174); +check_member(usb3_phy_qserdes_com_reg_layout, com_svs_mode_clk_sel, 0x184); +check_member(usb3_phy_qserdes_com_reg_layout, com_bin_vcocal_hsclk_sel, 0x1bc); + +/* Only for QMP V4 PHY - TX registers */ +struct usb3_phy_qserdes_tx_reg_layout { + u8 _reserved1[52]; + u32 tx_res_code_lane_tx; + u32 tx_res_code_lane_rx; + u32 tx_res_code_lane_offset_tx; + u32 tx_res_code_lane_offset_rx; + u8 _reserved2[64]; + u32 tx_lane_mode_1; + u8 _reserved3[20]; + u32 tx_rcv_detect_lvl_2; + u8 _reserved4[100]; + u32 tx_pi_qec_ctrl; +}; +check_member(usb3_phy_qserdes_tx_reg_layout, tx_res_code_lane_offset_tx, 0x03c); +check_member(usb3_phy_qserdes_tx_reg_layout, tx_res_code_lane_offset_rx, 0x040); +check_member(usb3_phy_qserdes_tx_reg_layout, tx_lane_mode_1, 0x084); +check_member(usb3_phy_qserdes_tx_reg_layout, tx_rcv_detect_lvl_2, 0x09c); +check_member(usb3_phy_qserdes_tx_reg_layout, tx_pi_qec_ctrl, 0x104); + +/* Only for QMP V4 PHY - RX registers */ +struct usb3_phy_qserdes_rx_reg_layout { + u8 _reserved1[20]; + u32 rx_ucdr_so_gain; + u8 _reserved2[24]; + u32 rx_ucdr_fastlock_fo_gain; + u32 rx_ucdr_so_saturation_and_enable; + u8 _reserved3[4]; + u32 rx_ucdr_fastlock_count_low; + u32 rx_ucdr_fastlock_count_high; + u32 rx_ucdr_pi_controls; + u8 _reserved4[4]; + u32 rx_ucdr_sb2_thresh1; + u32 rx_ucdr_sb2_thresh2; + u32 rx_ucdr_sb2_gain1; + u32 rx_ucdr_sb2_gain2; + u8 _reserved12[4]; + u32 rx_aux_data_tcoarse_tfine; + u8 _reserved5[112]; + u32 rx_vga_cal_cntrl1; + u32 rx_vga_cal_cntrl2; + u32 rx_gm_cal; + u8 _reserved6[12]; + u32 rx_rx_equ_adaptor_cntrl2; + u32 rx_rx_equ_adaptor_cntrl3; + u32 rx_rx_equ_adaptor_cntrl4; + u32 rx_rx_idac_tsettle_low; + u32 rx_rx_idac_tsettle_high; + u8 _reserved7[16]; + u32 rx_rx_eq_offset_adaptor_cntrl1; + u8 _reserved8[8]; + u32 rx_sigdet_cntrl; + u8 _reserved9[4]; + u32 rx_sigdet_deglitch_cntrl; + u8 _reserved10[72]; + u32 rx_rx_mode_00_low; + u32 rx_rx_mode_00_high; + u32 rx_rx_mode_00_high2; + u32 rx_rx_mode_00_high3; + u32 rx_rx_mode_00_high4; + u32 rx_rx_mode_01_low; + u32 rx_rx_mode_01_high; + u32 rx_rx_mode_01_high2; + u32 rx_rx_mode_01_high3; + u32 rx_rx_mode_01_high4; + u8 _reserved11[28]; + u32 rx_dfe_en_timer; + u32 rx_dfe_ctle_post_cal_offset; + u32 rx_dcc_ctrl1; + u8 _reserved13[4]; + u32 rx_vth_code; +}; + +check_member(usb3_phy_qserdes_rx_reg_layout, rx_ucdr_so_gain, 0x014); +check_member(usb3_phy_qserdes_rx_reg_layout, rx_ucdr_fastlock_fo_gain, 0x030); +check_member(usb3_phy_qserdes_rx_reg_layout, rx_vga_cal_cntrl1, 0x0d4); +check_member(usb3_phy_qserdes_rx_reg_layout, rx_rx_equ_adaptor_cntrl2, 0x0ec); +check_member(usb3_phy_qserdes_rx_reg_layout, rx_rx_equ_adaptor_cntrl3, 0x0f0); +check_member(usb3_phy_qserdes_rx_reg_layout, rx_rx_equ_adaptor_cntrl4, 0x0f4); +check_member(usb3_phy_qserdes_rx_reg_layout, rx_sigdet_cntrl, 0x11c); +check_member(usb3_phy_qserdes_rx_reg_layout, rx_dcc_ctrl1, 0x1bc); +check_member(usb3_phy_qserdes_rx_reg_layout, rx_vth_code, 0x1c4); + +/* Only for QMP V4 PHY - PCS registers */ +struct usb3_phy_pcs_reg_layout { + u32 pcs_sw_reset; + u8 _reserved0[16]; + u32 pcs_ready_status; + u8 _reserved1[40]; + u32 pcs_power_down_control; + u32 pcs_start_control; + u8 _reserved2[124]; + u32 pcs_lock_detect_config1; + u32 pcs_lock_detect_config2; + u32 pcs_lock_detect_config3; + u8 _reserved3[8]; + u32 pcs_lock_detect_config6; + u32 pcs_refgen_req_config1; + u8 _reserved4[168]; + u32 pcs_rx_sigdet_lvl; + u8 _reserved5[36]; + u32 pcs_cdr_reset_time; + u8 _reserved6[12]; + u32 pcs_align_detect_config1; + u32 pcs_align_detect_config2; + u8 _reserved7[8]; + u32 pcs_pcs_tx_rx_config; + u8 _reserved8[8]; + u32 pcs_eq_config1; + u8 _reserved9[12]; + u32 pcs_eq_config5; + u8 _reserved10[296]; + u32 pcs_usb3_lfps_det_high_count_val; + u8 _reserved11[28]; + u32 pcs_usb3_rxeqtraining_dfe_time_s2; +}; + +check_member(usb3_phy_pcs_reg_layout, pcs_lock_detect_config1, 0x0c4); +check_member(usb3_phy_pcs_reg_layout, pcs_lock_detect_config2, 0x0c8); +check_member(usb3_phy_pcs_reg_layout, pcs_lock_detect_config6, 0x0d8); +check_member(usb3_phy_pcs_reg_layout, pcs_pcs_tx_rx_config, 0x1d0); +check_member(usb3_phy_pcs_reg_layout, pcs_eq_config5, 0x1ec); +check_member(usb3_phy_pcs_reg_layout, pcs_usb3_lfps_det_high_count_val, 0x318); +check_member(usb3_phy_pcs_reg_layout, pcs_usb3_rxeqtraining_dfe_time_s2, 0x338); + +static struct usb3_phy_qserdes_com_reg_layout *const qserdes_com_reg_layout = + (void *)QMP_PHY_QSERDES_COM_REG_BASE; +static struct usb3_phy_qserdes_tx_reg_layout *const qserdes_tx_reg_layout = + (void *)QMP_PHY_QSERDES_TX_REG_BASE; +static struct usb3_phy_qserdes_rx_reg_layout *const qserdes_rx_reg_layout = + (void *)QMP_PHY_QSERDES_RX_REG_BASE; +static struct usb3_phy_pcs_reg_layout *const pcs_reg_layout = + (void *)QMP_PHY_PCS_REG_BASE; +static const struct qmp_phy_init_tbl qmp_v4_usb3_serdes_tbl[] = { + {&qserdes_com_reg_layout->com_ssc_en_center, 0x01}, + {&qserdes_com_reg_layout->com_ssc_per1, 0x31}, + {&qserdes_com_reg_layout->com_ssc_per2, 0x01}, + {&qserdes_com_reg_layout->com_ssc_step_size1_mode0, 0xde}, + {&qserdes_com_reg_layout->com_ssc_step_size2_mode0, 0x07}, + {&qserdes_com_reg_layout->com_ssc_step_size1_mode1, 0xde}, + {&qserdes_com_reg_layout->com_ssc_step_size2_mode1, 0x07}, + {&qserdes_com_reg_layout->com_sysclk_buf_enable, 0x0a}, + {&qserdes_com_reg_layout->com_cmn_iptrim, 0x20}, + {&qserdes_com_reg_layout->com_cp_ctrl_mode0, 0x06}, + {&qserdes_com_reg_layout->com_cp_ctrl_mode1, 0x06}, + {&qserdes_com_reg_layout->com_pll_rctrl_mode0, 0x16}, + {&qserdes_com_reg_layout->com_pll_rctrl_mode1, 0x16}, + {&qserdes_com_reg_layout->com_pll_cctrl_mode0, 0x36}, + {&qserdes_com_reg_layout->com_pll_cctrl_mode1, 0x36}, + {&qserdes_com_reg_layout->com_sysclk_en_sel, 0x1a}, + {&qserdes_com_reg_layout->com_lock_cmp_en, 0x04}, + {&qserdes_com_reg_layout->com_lock_cmp1_mode0, 0x14}, + {&qserdes_com_reg_layout->com_lock_cmp2_mode0, 0x34}, + {&qserdes_com_reg_layout->com_lock_cmp1_mode1, 0x34}, + {&qserdes_com_reg_layout->com_lock_cmp2_mode1, 0x82}, + {&qserdes_com_reg_layout->com_dec_start_mode0, 0x82}, + {&qserdes_com_reg_layout->com_dec_start_mode1, 0x82}, + {&qserdes_com_reg_layout->com_div_frac_start1_mode0, 0xab}, + {&qserdes_com_reg_layout->com_div_frac_start2_mode0, 0xea}, + {&qserdes_com_reg_layout->com_div_frac_start3_mode0, 0x02}, + {&qserdes_com_reg_layout->com_div_frac_start1_mode1, 0xab}, + {&qserdes_com_reg_layout->com_div_frac_start2_mode1, 0xea}, + {&qserdes_com_reg_layout->com_div_frac_start3_mode1, 0x02}, + {&qserdes_com_reg_layout->com_vco_tune_map, 0x02}, + {&qserdes_com_reg_layout->com_vco_tune1_mode0, 0x24}, + {&qserdes_com_reg_layout->com_vco_tune1_mode1, 0x24}, + {&qserdes_com_reg_layout->com_vco_tune2_mode1, 0x02}, + {&qserdes_com_reg_layout->com_hsclk_sel, 0x01}, + {&qserdes_com_reg_layout->com_coreclk_div_mode1, 0x08}, + {&qserdes_com_reg_layout->com_bin_vcocal_cmp_code1_mode0, 0xca}, + {&qserdes_com_reg_layout->com_bin_vcocal_cmp_code2_mode0, 0x1e}, + {&qserdes_com_reg_layout->com_bin_vcocal_cmp_code1_mode1, 0xca}, + {&qserdes_com_reg_layout->com_bin_vcocal_cmp_code2_mode1, 0x1e}, + {&qserdes_com_reg_layout->com_bin_vcocal_hsclk_sel, 0x11}, +}; + +static const struct qmp_phy_init_tbl qmp_v4_usb3_tx_tbl[] = { + {&qserdes_tx_reg_layout->tx_res_code_lane_tx, 0x60}, + {&qserdes_tx_reg_layout->tx_res_code_lane_rx, 0x60}, + {&qserdes_tx_reg_layout->tx_res_code_lane_offset_tx, 0x11}, + {&qserdes_tx_reg_layout->tx_res_code_lane_offset_rx, 0x02}, + {&qserdes_tx_reg_layout->tx_lane_mode_1, 0xd5}, + {&qserdes_tx_reg_layout->tx_rcv_detect_lvl_2, 0x12}, + {&qserdes_tx_reg_layout->tx_pi_qec_ctrl, 0x40}, +}; + +static const struct qmp_phy_init_tbl qmp_v4_usb3_rx_tbl[] = { + {&qserdes_rx_reg_layout->rx_ucdr_so_gain, 0x06}, + {&qserdes_rx_reg_layout->rx_ucdr_fastlock_fo_gain, 0x2f}, + {&qserdes_rx_reg_layout->rx_ucdr_so_saturation_and_enable, 0x7f}, + {&qserdes_rx_reg_layout->rx_ucdr_fastlock_count_low, 0xff}, + {&qserdes_rx_reg_layout->rx_ucdr_fastlock_count_high, 0x0f}, + {&qserdes_rx_reg_layout->rx_ucdr_pi_controls, 0x99}, + {&qserdes_rx_reg_layout->rx_ucdr_sb2_thresh1, 0x04}, + {&qserdes_rx_reg_layout->rx_ucdr_sb2_thresh2, 0x08}, + {&qserdes_rx_reg_layout->rx_ucdr_sb2_gain1, 0x05}, + {&qserdes_rx_reg_layout->rx_ucdr_sb2_gain2, 0x05}, + {&qserdes_rx_reg_layout->rx_vga_cal_cntrl1, 0x54}, + {&qserdes_rx_reg_layout->rx_vga_cal_cntrl2, 0x0c}, + {&qserdes_rx_reg_layout->rx_rx_equ_adaptor_cntrl2, 0x0f}, + {&qserdes_rx_reg_layout->rx_rx_equ_adaptor_cntrl3, 0x4a}, + {&qserdes_rx_reg_layout->rx_rx_equ_adaptor_cntrl4, 0x0a}, + {&qserdes_rx_reg_layout->rx_rx_idac_tsettle_low, 0xc0}, + {&qserdes_rx_reg_layout->rx_rx_idac_tsettle_high, 0x00}, + {&qserdes_rx_reg_layout->rx_rx_eq_offset_adaptor_cntrl1, 0x77}, + {&qserdes_rx_reg_layout->rx_sigdet_cntrl, 0x04}, + {&qserdes_rx_reg_layout->rx_sigdet_deglitch_cntrl, 0x0e}, + {&qserdes_rx_reg_layout->rx_rx_mode_00_low, 0xff}, + {&qserdes_rx_reg_layout->rx_rx_mode_00_low, 0x7f}, + {&qserdes_rx_reg_layout->rx_rx_mode_00_high, 0x7f}, + {&qserdes_rx_reg_layout->rx_rx_mode_00_high, 0xff}, + {&qserdes_rx_reg_layout->rx_rx_mode_00_high2, 0x7f}, + {&qserdes_rx_reg_layout->rx_rx_mode_00_high3, 0x7f}, + {&qserdes_rx_reg_layout->rx_rx_mode_00_high4, 0x97}, + {&qserdes_rx_reg_layout->rx_rx_mode_01_low, 0xdc}, + {&qserdes_rx_reg_layout->rx_rx_mode_01_high, 0xdc}, + {&qserdes_rx_reg_layout->rx_rx_mode_01_high2, 0x5c}, + {&qserdes_rx_reg_layout->rx_rx_mode_01_high3, 0x7b}, + {&qserdes_rx_reg_layout->rx_rx_mode_01_high4, 0xb4}, + {&qserdes_rx_reg_layout->rx_dfe_en_timer, 0x04}, + {&qserdes_rx_reg_layout->rx_dfe_ctle_post_cal_offset, 0x38}, + {&qserdes_rx_reg_layout->rx_aux_data_tcoarse_tfine, 0xa0}, + {&qserdes_rx_reg_layout->rx_dcc_ctrl1, 0x0c}, + {&qserdes_rx_reg_layout->rx_gm_cal, 0x1f}, + {&qserdes_rx_reg_layout->rx_vth_code, 0x10}, +}; + +static const struct qmp_phy_init_tbl qmp_v4_usb3_pcs_tbl[] = { + {&pcs_reg_layout->pcs_lock_detect_config1, 0xd0}, + {&pcs_reg_layout->pcs_lock_detect_config2, 0x07}, + {&pcs_reg_layout->pcs_lock_detect_config3, 0x20}, + {&pcs_reg_layout->pcs_lock_detect_config6, 0x13}, + {&pcs_reg_layout->pcs_refgen_req_config1, 0x21}, + {&pcs_reg_layout->pcs_rx_sigdet_lvl, 0xa9}, + {&pcs_reg_layout->pcs_cdr_reset_time, 0x0a}, + {&pcs_reg_layout->pcs_align_detect_config1, 0x88}, + {&pcs_reg_layout->pcs_align_detect_config2, 0x13}, + {&pcs_reg_layout->pcs_pcs_tx_rx_config, 0x0c}, + {&pcs_reg_layout->pcs_eq_config1, 0x4b}, + {&pcs_reg_layout->pcs_eq_config5, 0x10}, + {&pcs_reg_layout->pcs_usb3_lfps_det_high_count_val, 0xf8}, + {&pcs_reg_layout->pcs_usb3_rxeqtraining_dfe_time_s2, 0x07}, +}; + +struct ss_usb_phy_reg qmp_v4_usb_phy = { + .serdes_tbl = qmp_v4_usb3_serdes_tbl, + .serdes_tbl_num = ARRAY_SIZE(qmp_v4_usb3_serdes_tbl), + .tx_tbl = qmp_v4_usb3_tx_tbl, + .tx_tbl_num = ARRAY_SIZE(qmp_v4_usb3_tx_tbl), + .rx_tbl = qmp_v4_usb3_rx_tbl, + .rx_tbl_num = ARRAY_SIZE(qmp_v4_usb3_rx_tbl), + .pcs_tbl = qmp_v4_usb3_pcs_tbl, + .pcs_tbl_num = ARRAY_SIZE(qmp_v4_usb3_pcs_tbl), + .qmp_pcs_reg = (void *)QMP_PHY_PCS_REG_BASE, +}; + +static void qcom_qmp_phy_configure(const struct qmp_phy_init_tbl tbl[], + int num) +{ + int i; + const struct qmp_phy_init_tbl *t = tbl; + + if (!t) + return; + + for (i = 0; i < num; i++, t++) + write32(t->address, t->val); +} + +void ss_qmp_phy_init(void) +{ + struct ss_usb_phy_reg *ss_phy_reg; + + ss_phy_reg = &qmp_v4_usb_phy; + + /* power up USB3 PHY */ + write32(&ss_phy_reg->qmp_pcs_reg->pcs_power_down_control, 0x01); + + /* Serdes configuration */ + qcom_qmp_phy_configure(ss_phy_reg->serdes_tbl, + ss_phy_reg->serdes_tbl_num); + /* Tx, Rx, and PCS configurations */ + qcom_qmp_phy_configure(ss_phy_reg->tx_tbl, ss_phy_reg->tx_tbl_num); + qcom_qmp_phy_configure(ss_phy_reg->rx_tbl, ss_phy_reg->rx_tbl_num); + qcom_qmp_phy_configure(ss_phy_reg->pcs_tbl, ss_phy_reg->pcs_tbl_num); + + /* perform software reset of PCS/Serdes */ + write32(&ss_phy_reg->qmp_pcs_reg->pcs_sw_reset, 0x00); + /* start PCS/Serdes to operation mode */ + write32(&ss_phy_reg->qmp_pcs_reg->pcs_start_control, 0x03); + + /* + * Wait for PHY initialization to be done + * PCS_STATUS: wait for 1ms for PHY STATUS; + * SW can continuously check for PHYSTATUS = 1.b0. + */ + long lock_us = wait_us(10000, + !(read32(&ss_phy_reg->qmp_pcs_reg->pcs_ready_status) & + USB3_PCS_PHYSTATUS)); + if (!lock_us) + printk(BIOS_ERR, "ERROR: QMP PHY PLL LOCK fails:\n"); + else + printk(BIOS_DEBUG, "QMP PHY initialized and locked in %ldus\n", + lock_us); +} diff --git a/src/soc/qualcomm/common/usb/qusb_phy.c b/src/soc/qualcomm/common/usb/qusb_phy.c new file mode 100644 index 0000000..c8a56b0 --- /dev/null +++ b/src/soc/qualcomm/common/usb/qusb_phy.c @@ -0,0 +1,139 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/usb/qusb_phy.h> +#include <soc/efuse.h> +#include <timer.h> +#include <soc/usb/usb_common.h> + +static struct qfprom_corr * const qfprom_corr_efuse = (void *)QFPROM_BASE; + +struct hs_usb_phy_reg qusb_phy = { + .phy_pll = (void *)QUSB_PRIM_PHY_BASE, + + .phy_dig = (void *)QUSB_PRIM_PHY_DIG_BASE, + + .efuse_offset = 25, +}; + +static void qusb2_phy_override_phy_params(struct hs_usb_phy_reg *hs_phy_reg) +{ + /* Override preemphasis value */ + write32(&hs_phy_reg->phy_dig->tune1, + hs_phy_reg->board_data->port_tune1); + + /* Override BIAS_CTRL_2 to reduce the TX swing overshooting. */ + write32(&hs_phy_reg->phy_pll->bias_ctrl_2, + hs_phy_reg->board_data->pll_bias_control_2); + + /* Override IMP_RES_OFFSET value */ + write32(&hs_phy_reg->phy_dig->imp_ctrl1, + hs_phy_reg->board_data->imp_ctrl1); +} + +/* + * Fetches HS Tx tuning value from efuse register and sets the + * QUSB2PHY_PORT_TUNE1/2 register. + * For error case, skip setting the value and use the default value. + */ + +static void qusb2_phy_set_tune_param(struct hs_usb_phy_reg *hs_phy_reg) +{ + /* + * Efuse registers 3 bit value specifies tuning for HSTX + * output current in TUNE1 Register. Hence Extract 3 bits from + * EFUSE at correct position. + */ + + const int efuse_bits = 3; + int bit_pos = hs_phy_reg->efuse_offset; + + u32 bit_mask = (1 << efuse_bits) - 1; + u32 tune_val = + (read32(&qfprom_corr_efuse->qusb_hstx_trim_lsb) >> bit_pos) + & bit_mask; + /* + * if efuse reg is updated (i.e non-zero) then use it to program + * tune parameters. + */ + if (tune_val) + clrsetbits32(&hs_phy_reg->phy_dig->tune1, + PORT_TUNE1_MASK, tune_val << 4); +} + +static void tune_phy(struct hs_usb_phy_reg *hs_phy_reg) +{ + write32(&hs_phy_reg->phy_dig->pwr_ctrl2, QUSB2PHY_PWR_CTRL2); + /* IMP_CTRL1: Control the impedance reduction */ + write32(&hs_phy_reg->phy_dig->imp_ctrl1, QUSB2PHY_IMP_CTRL1); + /* IMP_CTRL2: Impedance offset/mapping slope */ + write32(&hs_phy_reg->phy_dig->imp_ctrl2, QUSB2PHY_IMP_CTRL1); + write32(&hs_phy_reg->phy_dig->chg_ctrl2, QUSB2PHY_IMP_CTRL2); + /* + * TUNE1: Sets HS Impedance to approx 45 ohms + * then override with efuse value. + */ + write32(&hs_phy_reg->phy_dig->tune1, QUSB2PHY_PORT_TUNE1); + /* TUNE2: Tuning for HS Disconnect Level */ + write32(&hs_phy_reg->phy_dig->tune2, QUSB2PHY_PORT_TUNE2); + /* TUNE3: Tune squelch range */ + write32(&hs_phy_reg->phy_dig->tune3, QUSB2PHY_PORT_TUNE3); + /* TUNE4: Sets EOP_DLY(Squelch rising edge to linestate falling edge) */ + write32(&hs_phy_reg->phy_dig->tune4, QUSB2PHY_PORT_TUNE4); + write32(&hs_phy_reg->phy_dig->tune5, QUSB2PHY_PORT_TUNE5); + + if (hs_phy_reg->board_data) { + /* Override board specific PHY tuning values */ + qusb2_phy_override_phy_params(hs_phy_reg); + + /* Set efuse value for tuning the PHY */ + qusb2_phy_set_tune_param(hs_phy_reg); + } +} + +void hs_usb_phy_init(void *board_data) +{ + struct hs_usb_phy_reg *hs_phy_reg; + + hs_phy_reg = &qusb_phy; + + hs_phy_reg->board_data = (struct usb_board_data *) board_data; + + /* PWR_CTRL: set the power down bit to disable the PHY */ + + setbits32(&hs_phy_reg->phy_dig->pwr_ctrl1, POWER_DOWN); + + write32(&hs_phy_reg->phy_pll->analog_controls_two, + QUSB2PHY_PLL_ANALOG_CONTROLS_TWO); + write32(&hs_phy_reg->phy_pll->clock_inverters, + QUSB2PHY_PLL_CLOCK_INVERTERS); + write32(&hs_phy_reg->phy_pll->cmode, + QUSB2PHY_PLL_CMODE); + write32(&hs_phy_reg->phy_pll->lock_delay, + QUSB2PHY_PLL_LOCK_DELAY); + write32(&hs_phy_reg->phy_pll->dig_tim, + QUSB2PHY_PLL_DIGITAL_TIMERS_TWO); + write32(&hs_phy_reg->phy_pll->bias_ctrl_1, + QUSB2PHY_PLL_BIAS_CONTROL_1); + write32(&hs_phy_reg->phy_pll->bias_ctrl_2, + QUSB2PHY_PLL_BIAS_CONTROL_2); + + tune_phy(hs_phy_reg); + + /* PWR_CTRL1: Clear the power down bit to enable the PHY */ + clrbits32(&hs_phy_reg->phy_dig->pwr_ctrl1, POWER_DOWN); + + write32(&hs_phy_reg->phy_dig->debug_ctrl2, + DEBUG_CTRL2_MUX_PLL_LOCK_STATUS); + + /* + * DEBUG_STAT5: wait for 160uS for PLL lock; + * vstatus[0] changes from 0 to 1. + */ + long lock_us = wait_us(160, read32(&hs_phy_reg->phy_dig->debug_stat5) & + VSTATUS_PLL_LOCK_STATUS_MASK); + if (!lock_us) + printk(BIOS_ERR, "ERROR: QUSB PHY PLL LOCK fails\n"); + else + printk(BIOS_DEBUG, "QUSB PHY initialized and locked in %ldus\n", + lock_us); +} diff --git a/src/soc/qualcomm/common/usb/snps_usb_phy.c b/src/soc/qualcomm/common/usb/snps_usb_phy.c new file mode 100644 index 0000000..1b2d869 --- /dev/null +++ b/src/soc/qualcomm/common/usb/snps_usb_phy.c @@ -0,0 +1,86 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/usb/snps_usb_phy.h> +#include <soc/addressmap.h> +#include <commonlib/helpers.h> +#include <soc/usb/usb_common.h> + +#define SLEEPM BIT(0) + +#define TERMSEL BIT(5) + +#define POR BIT(1) + +#define FSEL_MASK GENMASK(7, 5) +#define FSEL_DEFAULT (0x3 << 4) + +#define VBUSVLDEXTSEL0 BIT(4) +#define PLLBTUNE BIT(5) + +#define VREGBYPASS BIT(0) + +#define VBUSVLDEXT0 BIT(0) + +#define USB2_SUSPEND_N BIT(2) +#define USB2_SUSPEND_N_SEL BIT(3) + +#define UTMI_PHY_CMN_CTRL_OVERRIDE_EN BIT(1) + +#define REFCLK_SEL_MASK GENMASK(1, 0) +#define REFCLK_SEL_DEFAULT (0x2 << 0) + +#define PARAM_OVRD_MASK 0xFF + +struct hs_usb_phy_reg *hs_phy_reg = (void *)HS_USB_PRIM_PHY_BASE; + +void hs_usb_phy_init(void *board_data) +{ + struct usb_board_data *override_data = + (struct usb_board_data *) board_data; + + clrsetbits32(&hs_phy_reg->cfg0, UTMI_PHY_CMN_CTRL_OVERRIDE_EN, + UTMI_PHY_CMN_CTRL_OVERRIDE_EN); + + clrsetbits32(&hs_phy_reg->utmi_ctrl5, POR, POR); + + clrsetbits32(&hs_phy_reg->hs_phy_ctrl_common0, FSEL_MASK, 0); + + clrsetbits32(&hs_phy_reg->hs_phy_ctrl_common1, PLLBTUNE, PLLBTUNE); + + clrsetbits32(&hs_phy_reg->refclk_ctrl, REFCLK_SEL_MASK, + REFCLK_SEL_DEFAULT); + + clrsetbits32(&hs_phy_reg->hs_phy_ctrl_common1, VBUSVLDEXTSEL0, + VBUSVLDEXTSEL0); + + clrsetbits32(&hs_phy_reg->hs_phy_ctrl1, VBUSVLDEXT0, VBUSVLDEXT0); + + if (board_data) { + clrsetbits32(&hs_phy_reg->hs_phy_override_x0, + PARAM_OVRD_MASK, override_data->parameter_override_x0); + + clrsetbits32(&hs_phy_reg->hs_phy_override_x1, + PARAM_OVRD_MASK, override_data->parameter_override_x1); + + clrsetbits32(&hs_phy_reg->hs_phy_override_x2, + PARAM_OVRD_MASK, override_data->parameter_override_x2); + + clrsetbits32(&hs_phy_reg->hs_phy_override_x3, + PARAM_OVRD_MASK, override_data->parameter_override_x3); + } + clrsetbits32(&hs_phy_reg->hs_phy_ctrl_common2, VREGBYPASS, VREGBYPASS); + + clrsetbits32(&hs_phy_reg->hs_phy_ctrl2, + USB2_SUSPEND_N_SEL | USB2_SUSPEND_N, + USB2_SUSPEND_N_SEL | USB2_SUSPEND_N); + + clrsetbits32(&hs_phy_reg->utmi_ctrl0, SLEEPM, SLEEPM); + + clrsetbits32(&hs_phy_reg->utmi_ctrl5, POR, 0); + + clrsetbits32(&hs_phy_reg->hs_phy_ctrl2, USB2_SUSPEND_N_SEL, 0); + + clrsetbits32(&hs_phy_reg->cfg0, UTMI_PHY_CMN_CTRL_OVERRIDE_EN, 0); + + printk(BIOS_DEBUG, "USB HS PHY initialized\n"); +} diff --git a/src/soc/qualcomm/common/usb/usb.c b/src/soc/qualcomm/common/usb/usb.c new file mode 100644 index 0000000..3a0c003 --- /dev/null +++ b/src/soc/qualcomm/common/usb/usb.c @@ -0,0 +1,141 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <device/mmio.h> +#include <soc/usb/usb_common.h> +#include <soc/addressmap.h> +#include <soc/clock.h> + +struct usb_dwc3 { + u32 sbuscfg0; + u32 sbuscfg1; + u32 txthrcfg; + u32 rxthrcfg; + u32 ctl; + u32 pmsts; + u32 sts; + u32 uctl1; + u32 snpsid; + u32 gpio; + u32 uid; + u32 uctl; + u64 buserraddr; + u64 prtbimap; + u8 reserved1[32]; + u32 dbgfifospace; + u32 dbgltssm; + u32 dbglnmcc; + u32 dbgbmu; + u32 dbglspmux; + u32 dbglsp; + u32 dbgepinfo0; + u32 dbgepinfo1; + u64 prtbimap_hs; + u64 prtbimap_fs; + u8 reserved2[112]; + u32 usb2phycfg; + u8 reserved3[124]; + u32 usb2phyacc; + u8 reserved4[60]; + u32 usb3pipectl; + u8 reserved5[60]; +}; +check_member(usb_dwc3, usb2phycfg, 0x100); +check_member(usb_dwc3, usb3pipectl, 0x1c0); + +struct usb_dwc3_cfg { + struct usb_dwc3 *usb_host_dwc3; + u32 *usb3_bcr; + u32 *qusb2phy_bcr; + u32 *gcc_usb3phy_bcr_reg; + u32 *gcc_qmpphy_bcr_reg; +}; + +static struct usb_dwc3_cfg usb_port0 = { + .usb_host_dwc3 = (void *)USB_HOST_DWC3_BASE, + .usb3_bcr = &gcc->usb30_prim_bcr, + .qusb2phy_bcr = &gcc->qusb2phy_prim_bcr, + .gcc_usb3phy_bcr_reg = &gcc->usb3_dp_phy_prim_bcr, + .gcc_qmpphy_bcr_reg = &gcc->usb3_phy_prim_bcr, +}; + +static void reset_usb(struct usb_dwc3_cfg *dwc3) +{ + /* Assert Core reset */ + clock_reset_bcr(dwc3->usb3_bcr, 1); + + /* Assert HS PHY reset */ + clock_reset_bcr(dwc3->qusb2phy_bcr, 1); + + /* Assert QMP PHY reset */ + clock_reset_bcr(dwc3->gcc_usb3phy_bcr_reg, 1); + clock_reset_bcr(dwc3->gcc_qmpphy_bcr_reg, 1); +} + +void reset_usb0(void) +{ + /* Before Resetting PHY, put Core in Reset */ + printk(BIOS_INFO, "Starting DWC3 and PHY resets for USB(0)\n"); + + reset_usb(&usb_port0); +} + +static void setup_dwc3(struct usb_dwc3 *dwc3) +{ + /* core exits U1/U2/U3 only in PHY power state P1/P2/P3 respectively */ + clrsetbits32(&dwc3->usb3pipectl, + DWC3_GUSB3PIPECTL_DELAYP1TRANS, + DWC3_GUSB3PIPECTL_UX_EXIT_IN_PX); + + /* + * Configure USB phy interface of DWC3 core. + * 1. Select UTMI+ PHY with 16-bit interface. + * 2. Set USBTRDTIM to the corresponding value + * according to the UTMI+ PHY interface. + */ + clrsetbits32(&dwc3->usb2phycfg, + (DWC3_GUSB2PHYCFG_USB2TRDTIM_MASK | + DWC3_GUSB2PHYCFG_PHYIF_MASK), + (DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) | + DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT))); + + clrsetbits32(&dwc3->ctl, (DWC3_GCTL_SCALEDOWN_MASK | + DWC3_GCTL_DISSCRAMBLE), + DWC3_GCTL_U2EXIT_LFPS | DWC3_GCTL_DSBLCLKGTNG); + + /* configure controller in Host mode */ + clrsetbits32(&dwc3->ctl, (DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG)), + DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_HOST)); + printk(BIOS_SPEW, "Configure USB in Host mode\n"); +} + +/* Initialization of DWC3 Core and PHY */ + +static void setup_usb_host(struct usb_dwc3_cfg *dwc3, + void *board_data) +{ + /* Clear core reset. */ + clock_reset_bcr(dwc3->usb3_bcr, 0); + + /* Clear QUSB PHY reset. */ + clock_reset_bcr(dwc3->qusb2phy_bcr, 0); + + /* Initialize HS PHY */ + hs_usb_phy_init(board_data); + + /* Clear QMP PHY resets. */ + clock_reset_bcr(dwc3->gcc_usb3phy_bcr_reg, 0); + clock_reset_bcr(dwc3->gcc_qmpphy_bcr_reg, 0); + + /* Initialize QMP PHY */ + ss_qmp_phy_init(); + + setup_dwc3(dwc3->usb_host_dwc3); + + printk(BIOS_INFO, "DWC3 and PHY setup finished\n"); +} +void setup_usb_host0(void *board_data) +{ + printk(BIOS_INFO, "Setting up USB HOST0 controller.\n"); + setup_usb_host(&usb_port0, board_data); +} diff --git a/src/soc/qualcomm/sc7180/Makefile.inc b/src/soc/qualcomm/sc7180/Makefile.inc index df565b4..cbdc5b3 100644 --- a/src/soc/qualcomm/sc7180/Makefile.inc +++ b/src/soc/qualcomm/sc7180/Makefile.inc @@ -29,7 +29,7 @@ romstage-y += ../common/qclib.c romstage-y += ../common/mmu.c romstage-y += mmu.c -romstage-y += usb.c +romstage-y += ../common/usb/usb.c romstage-y += carve_out.c romstage-$(CONFIG_DRIVERS_UART) += ../common/qupv3_uart.c @@ -37,8 +37,10 @@ ramstage-y += soc.c ramstage-y += carve_out.c ramstage-y += ../common/aop_load_reset.c -ramstage-y += usb.c ramstage-$(CONFIG_DRIVERS_UART) += ../common/qupv3_uart.c +ramstage-y += ../common/usb/usb.c +ramstage-y += ../common/usb/qusb_phy.c +ramstage-y += ../common/usb/qmpv3_usb_phy.c ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += display/dsi_phy_pll.c ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += display/dsi_phy.c ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += display/dsi.c diff --git a/src/soc/qualcomm/sc7180/include/soc/usb.h b/src/soc/qualcomm/sc7180/include/soc/usb.h deleted file mode 100644 index f3bc89a..0000000 --- a/src/soc/qualcomm/sc7180/include/soc/usb.h +++ /dev/null @@ -1,82 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -#include <types.h> - -#ifndef _SC7180_USB_H_ -#define _SC7180_USB_H_ - -/* QSCRATCH_GENERAL_CFG register bit offset */ -#define PIPE_UTMI_CLK_SEL BIT(0) -#define PIPE3_PHYSTATUS_SW BIT(3) -#define PIPE_UTMI_CLK_DIS BIT(8) - -/* Global USB3 Control Registers */ -#define DWC3_GUSB3PIPECTL_DELAYP1TRANS BIT(18) -#define DWC3_GUSB3PIPECTL_UX_EXIT_IN_PX BIT(27) -#define DWC3_GCTL_PRTCAPDIR(n) ((n) << 12) -#define DWC3_GCTL_PRTCAP_OTG 3 -#define DWC3_GCTL_PRTCAP_HOST 1 - -/* Global USB2 PHY Configuration Register */ -#define DWC3_GUSB2PHYCFG_USBTRDTIM(n) ((n) << 10) -#define DWC3_GUSB2PHYCFG_USB2TRDTIM_MASK DWC3_GUSB2PHYCFG_USBTRDTIM(0xf) -#define DWC3_GUSB2PHYCFG_PHYIF(n) ((n) << 3) -#define DWC3_GUSB2PHYCFG_PHYIF_MASK DWC3_GUSB2PHYCFG_PHYIF(1) -#define USBTRDTIM_UTMI_8_BIT 9 -#define UTMI_PHYIF_8_BIT 0 - -#define DWC3_GCTL_SCALEDOWN(n) ((n) << 4) -#define DWC3_GCTL_SCALEDOWN_MASK DWC3_GCTL_SCALEDOWN(3) -#define DWC3_GCTL_DISSCRAMBLE (1 << 3) -#define DWC3_GCTL_U2EXIT_LFPS (1 << 2) -#define DWC3_GCTL_DSBLCLKGTNG (1 << 0) - -#define PORT_TUNE1_MASK 0xf0 - -/* QUSB2PHY_PWR_CTRL1 register related bits */ -#define POWER_DOWN BIT(0) - -/* DEBUG_CTRL2 register value to program VSTATUS MUX for PHY status */ -#define DEBUG_CTRL2_MUX_PLL_LOCK_STATUS 0x4 - -/* STAT5 register bits */ -#define VSTATUS_PLL_LOCK_STATUS_MASK BIT(0) - -/* QUSB PHY register values */ -#define QUSB2PHY_PLL_ANALOG_CONTROLS_TWO 0x03 -#define QUSB2PHY_PLL_CLOCK_INVERTERS 0x7c -#define QUSB2PHY_PLL_CMODE 0x80 -#define QUSB2PHY_PLL_LOCK_DELAY 0x0a -#define QUSB2PHY_PLL_DIGITAL_TIMERS_TWO 0x19 -#define QUSB2PHY_PLL_BIAS_CONTROL_1 0x40 -#define QUSB2PHY_PLL_BIAS_CONTROL_2 0x22 -#define QUSB2PHY_PWR_CTRL2 0x21 -#define QUSB2PHY_IMP_CTRL1 0x08 -#define QUSB2PHY_IMP_CTRL2 0x58 -#define QUSB2PHY_PORT_TUNE1 0xc5 -#define QUSB2PHY_PORT_TUNE2 0x29 -#define QUSB2PHY_PORT_TUNE3 0xca -#define QUSB2PHY_PORT_TUNE4 0x04 -#define QUSB2PHY_PORT_TUNE5 0x03 -#define QUSB2PHY_CHG_CTRL2 0x30 - -/* USB3PHY_PCIE_USB3_PCS_PCS_STATUS bit */ -#define USB3_PCS_PHYSTATUS BIT(6) - -struct usb_board_data { - /* Register values going to override from the boardfile */ - u32 pll_bias_control_2; - u32 imp_ctrl1; - u32 port_tune1; -}; - -struct qmp_phy_init_tbl { - u32 *address; - u32 val; -}; - -void setup_usb_host0(struct usb_board_data *data); - -/* Call reset_ before setup_ */ -void reset_usb0(void); - -#endif /* _SC7180_USB_H_ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/56091 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1013ded22855286220cfa747cb25418070fe85a7 Gerrit-Change-Number: 56091 Gerrit-PatchSet: 42 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-CC: Sandeep Maheswaram <sanm(a)codeaurora.org> Gerrit-MessageType: merged

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Change in coreboot[master]: treewide: Replace spinlock calls with mutex
by Raul Rangel (Code Review) 30 Nov '21

30 Nov '21

Attention is currently required from: Julius Werner, Kyösti Mälkki, Rob Barnes, Patrick Rudolph, Karthik Ramasubramanian. Hello build bot (Jenkins), Julius Werner, Rob Barnes, Kyösti Mälkki, Patrick Rudolph, Karthik Ramasubramanian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59321 to look at the new patch set (#8). Change subject: treewide: Replace spinlock calls with mutex ...................................................................... treewide: Replace spinlock calls with mutex spinlock does not currently work nicely with coop-threads. If a `udelay` is called while in a critical section, it will context switch. If that second thread also tries to acquire the same lock then we deadlock since we never yield again. There is currently a hack in x86/spinlock.h where we disable coop threads when acquiring a spinlock. This hack only works for ramstage because in romstage we use the noop spinlock implementation. By replacing the spinlocks with mutex we no longer need to rely on the hack in the x86/spinlock.h. BUG=b:179699789 TEST=Boot guybrush to OS Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: Ibee331a9ccd491e819c7f2c9a19bca7dc4379d9d --- M src/console/printk.c M src/cpu/intel/microcode/microcode.c M src/cpu/x86/lapic/lapic_cpu_init.c M src/cpu/x86/mp_init.c M src/device/device.c M src/drivers/pc80/rtc/post.c 6 files changed, 41 insertions(+), 32 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/59321/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/59321 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibee331a9ccd491e819c7f2c9a19bca7dc4379d9d Gerrit-Change-Number: 59321 Gerrit-PatchSet: 8 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: lib: Add a mutex
by Raul Rangel (Code Review) 30 Nov '21

30 Nov '21

Attention is currently required from: Julius Werner, Kyösti Mälkki, Rob Barnes, Karthik Ramasubramanian. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59320 ) Change subject: lib: Add a mutex ...................................................................... Patch Set 9: (2 comments) File src/lib/mutex.c: https://review.coreboot.org/c/coreboot/+/59320/comment/72286616_a96f339c PS8, Line 12: return; > They don't belong in spinlock.h since the mutex and spinlock use different algorithms. […] Done https://review.coreboot.org/c/coreboot/+/59320/comment/18a983f8_1f08945d PS8, Line 27: } while (__atomic_load_1(&mutex->locked, __ATOMIC_RELAXED)); > static __always_inline int spin_is_locked(x) […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/59320 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I41e02a54a17b1f6513b36a0274e43fc715472d78 Gerrit-Change-Number: 59320 Gerrit-PatchSet: 9 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Mon, 29 Nov 2021 23:37:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: lib: Add a mutex
by Raul Rangel (Code Review) 30 Nov '21

30 Nov '21

Attention is currently required from: Julius Werner, Kyösti Mälkki, Rob Barnes, Karthik Ramasubramanian. Hello build bot (Jenkins), Julius Werner, Rob Barnes, Kyösti Mälkki, Karthik Ramasubramanian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59320 to look at the new patch set (#9). Change subject: lib: Add a mutex ...................................................................... lib: Add a mutex We currently have two synchronization primatives, spinlock and thread_mutex. spinlock is meant to block multiple CPUs from entering a critical section. thread_mutex is meant to block multiple coop-threads from entering a critical section. It is not AP aware at all. This CL introduces a mutex that can handle both concepts. The implementation is using the GCC/LLVM atomic builtin functions. The generated code uses the xchg instruction vs spinlock which uses (lock) decb. 8: b0 01 mov $0x1,%al a: 86 03 xchg %al,(%ebx) c: 84 c0 test %al,%al BUG=b:179699789 TEST=Boot guybrush to OS Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I41e02a54a17b1f6513b36a0274e43fc715472d78 --- A src/include/mutex.h 1 file changed, 88 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/59320/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/59320 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I41e02a54a17b1f6513b36a0274e43fc715472d78 Gerrit-Change-Number: 59320 Gerrit-PatchSet: 9 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: brya: add various ES variants
by Tim Wawrzynczak (Code Review) 30 Nov '21

30 Nov '21

Attention is currently required from: YH Lin, Nick Vaccaro, Zhuohao Lee. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59728 ) Change subject: brya: add various ES variants ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59728 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic9516fec591429238bde1478eca2522d8ed10127 Gerrit-Change-Number: 59728 Gerrit-PatchSet: 3 Gerrit-Owner: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Comment-Date: Mon, 29 Nov 2021 23:06:51 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: src/security/vboot: Set up secure counter space in TPM NVRAM
by Karthik Ramasubramanian (Code Review) 30 Nov '21

30 Nov '21

Attention is currently required from: Andrey Pronin, Raul Rangel, Paul Menzel, Julius Werner, Yu-Ping Wu. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59476 ) Change subject: src/security/vboot: Set up secure counter space in TPM NVRAM ...................................................................... Patch Set 7: (1 comment) File src/security/vboot/Kconfig: https://review.coreboot.org/c/coreboot/+/59476/comment/e7b28a3c_e2ac6770 PS6, Line 289: Entities that : use these counters increment them in the first use-case > "first use-case"? I think I would remove the sentence. Rephrased it to clarify what I meant by first use-case. -- To view, visit https://review.coreboot.org/c/coreboot/+/59476 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I915fbdada60e242d911b748ad5dc28028de9b657 Gerrit-Change-Number: 59476 Gerrit-PatchSet: 7 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Andrey Pronin <apronin(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Andrey Pronin <apronin(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Andrey Pronin <apronin(a)google.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Andrey Pronin <apronin(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Mon, 29 Nov 2021 23:01:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: src/security/vboot: Set up secure counter space in TPM NVRAM
by Raul Rangel (Code Review) 30 Nov '21

30 Nov '21

Attention is currently required from: Andrey Pronin, Paul Menzel, Julius Werner, Yu-Ping Wu, Karthik Ramasubramanian. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59476 ) Change subject: src/security/vboot: Set up secure counter space in TPM NVRAM ...................................................................... Patch Set 7: Code-Review+1 (1 comment) File src/security/vboot/Kconfig: https://review.coreboot.org/c/coreboot/+/59476/comment/04be5af4_475f6389 PS6, Line 289: Entities that : use these counters increment them in the first use-case > "first use-case"? I think I would remove the sentence. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/59476 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I915fbdada60e242d911b748ad5dc28028de9b657 Gerrit-Change-Number: 59476 Gerrit-PatchSet: 7 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Andrey Pronin <apronin(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Andrey Pronin <apronin(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Andrey Pronin <apronin(a)google.com> Gerrit-Attention: Andrey Pronin <apronin(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Mon, 29 Nov 2021 23:00:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: src/security/vboot: Set up secure counter space in TPM NVRAM
by Karthik Ramasubramanian (Code Review) 29 Nov '21

29 Nov '21

Attention is currently required from: Andrey Pronin, Paul Menzel, Julius Werner, Yu-Ping Wu, Karthik Ramasubramanian. Hello build bot (Jenkins), Andrey Pronin, Raul Rangel, Julius Werner, Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59476 to look at the new patch set (#7). Change subject: src/security/vboot: Set up secure counter space in TPM NVRAM ...................................................................... src/security/vboot: Set up secure counter space in TPM NVRAM High Definition (HD) protected content playback requires secure counters that are updated at regular interval while the protected content is playing. To support similar use-cases, define space for secure counters in TPM NVRAM and initialize them. These counters are defined once during the factory initialization stage. Also add VBOOT_DEFINE_WIDEVINE_COUNTERS config item to enable these secure counters only on the mainboard where they are required/used. BUG=b:205261728 TEST=Build and boot to OS in guybrush. Ensure that the secure counters are defined successfully in TPM NVRAM space. tlcl_define_space: response is 0 tlcl_define_space: response is 0 tlcl_define_space: response is 0 tlcl_define_space: response is 0 On reboot if forced to redefine the space, it is identified as already defined. tlcl_define_space: response is 14c define_space():219: define_space: Secure Counter space already exists tlcl_define_space: response is 14c define_space():219: define_space: Secure Counter space already exists tlcl_define_space: response is 14c define_space():219: define_space: Secure Counter space already exists tlcl_define_space: response is 14c define_space():219: define_space: Secure Counter space already exists Change-Id: I915fbdada60e242d911b748ad5dc28028de9b657 Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> --- M src/security/vboot/Kconfig M src/security/vboot/antirollback.h M src/security/vboot/secdata_tpm.c 3 files changed, 43 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/59476/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/59476 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I915fbdada60e242d911b748ad5dc28028de9b657 Gerrit-Change-Number: 59476 Gerrit-PatchSet: 7 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Andrey Pronin <apronin(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Andrey Pronin <apronin(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Andrey Pronin <apronin(a)google.com> Gerrit-Attention: Andrey Pronin <apronin(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newpatchset

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coreboot-gerrit November 2021