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Change subject: Cezanne FSP wrapper: Sync with PI 1.0.0.5
......................................................................
Cezanne FSP wrapper: Sync with PI 1.0.0.5
New PI 1.0.0.5 has more data in HOB of DMI. The dismatched size of HOB
causes the wrong data tranfer. So the coreboot also need to change.
BUG=b:204732649
Change-Id: Id95c37a0d7027d75afddf9d7528ff41ae3a347f5
Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com>
---
M src/vendorcode/amd/fsp/cezanne/dmi_info.h
1 file changed, 3 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/59687/2
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Change subject: vc/mediatek/mt8195: Fix rank1 CKE setting for single-rank DRAM
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/59715/comment/492f196b_5e97e6a2
PS1, Line 8:
> Please describe the problem first.
Done
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Change subject: vc/mediatek/mt8195: Fix rank1 CKE setting for single-rank DRAM
......................................................................
vc/mediatek/mt8195: Fix rank1 CKE setting for single-rank DRAM
Fix the issue that power consumption of single rank DRAM is greater
than dual rank DRAM due to incorrect settings of rank1 CKE.
Set rank1 CKE to the correct state to fix this issue.
BUG=b:196867407
TEST=DUT can boot to OS.
Signed-off-by: Ryan Chuang <ryan.chuang(a)mediatek.corp-partner.google.com>
Change-Id: If336197aea4770dda1332b6e83da8ec9a4f9d77b
---
M src/vendorcode/mediatek/mt8195/dramc/dramc_pi_main.c
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git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/59715/2
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SH Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59609 )
Change subject: mb/google/dedede: Add SAR sensor for bugzzy
......................................................................
Patch Set 3:
(6 comments)
Patchset:
PS3:
Thanks for the patch!
File src/mainboard/google/dedede/variants/bugzzy/gpio.c:
https://review.coreboot.org/c/coreboot/+/59609/comment/15360cf9_52145aa5
PS3, Line 51: /* E11 : WIFI_SAR_SENSOR_INT */
: PAD_CFG_GPI_APIC(GPP_E11, NONE, PLTRST, LEVEL, NONE),
We will not add Wifi P-sensor for bugzzy, so we can disable I2C5 port and remove the device from tree.
File src/mainboard/google/dedede/variants/bugzzy/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/59609/comment/5cb817c2_aca0468d
PS3, Line 51: [PchSerialIoIndexI2C5] = PchSerialIoPci,
We will not add Wifi P-sensor for bugzzy, so we can disable I2C5 port and remove the device from tree.
https://review.coreboot.org/c/coreboot/+/59609/comment/79b497e1_63aebf86
PS3, Line 67: #| I2C5 | P-sensor(Wifi) |
We will not add Wifi P-sensor for bugzzy, so we can disable I2C5 port and remove the device from tree.
https://review.coreboot.org/c/coreboot/+/59609/comment/6dc18130_f2116cc5
PS3, Line 239: #register "generic.probed" = "1"
We don't need it.
https://review.coreboot.org/c/coreboot/+/59609/comment/7a68fb2b_4cf7843d
PS3, Line 338: device pci 19.1 on
: chip drivers/i2c/sx9360
: register "desc" = ""SAR Proximity Sensor - Wifi""
: register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E11_IRQ)"
: register "uid" = "2"
: register "proxraw_strength" = "2"
: register "avg_pos_strength" = "16"
: register "resolution" = "1024"
: device i2c 28 on end
: end
: end #I2C 5
We will not add Wifi P-sensor for bugzzy, so we can disable I2C5 port and remove the device from tree.
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Change subject: mb/google/brya/var/vell: update gpio override
......................................................................
Patch Set 13:
(1 comment)
File src/mainboard/google/brya/variants/vell/gpio.c:
https://review.coreboot.org/c/coreboot/+/59305/comment/ee512991_23f46abc
PS8, Line 17: /* B2 : VRALERT# ==> RGB_RST_ODL */
: PAD_CFG_GPI(GPP_B2, NONE, DEEP),
> yes,it is output, had Corrected
Done
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Change subject: mb/google/brya/var/vell: update memory settings
......................................................................
Patch Set 12:
(2 comments)
File src/mainboard/google/brya/variants/vell/memory.c:
https://review.coreboot.org/c/coreboot/+/59334/comment/b57eaed0_277cfa69
PS12, Line 67: 1
> `true`
Done
https://review.coreboot.org/c/coreboot/+/59334/comment/9bc55e7c_07939769
PS12, Line 68:
> is `. […]
Done
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Change subject: mb/google/brya/var/vell: update gpio override
......................................................................
Patch Set 13:
(1 comment)
File src/mainboard/google/brya/variants/vell/gpio.c:
https://review.coreboot.org/c/coreboot/+/59305/comment/cdd465f7_5644925b
PS8, Line 17: /* B2 : VRALERT# ==> RGB_RST_ODL */
: PAD_CFG_GPI(GPP_B2, NONE, DEEP),
> then should it be an output, to control the state?
yes,it is output, had Corrected
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Change subject: mb/google/brya/var/vell: update gpio override
......................................................................
mb/google/brya/var/vell: update gpio override
Configure GPIOs according to schematics
Update initial gpio configuration for redrix
BUG=b:205908918
TEST=emerge-brya coreboot
Change-Id: Icc91866f7555c294af7eed9e5d1550e73d8059d0
Signed-off-by: Kevin Chiu <Kevin.Chiu(a)quantatw.com>
---
A src/mainboard/google/brya/variants/vell/Makefile.inc
A src/mainboard/google/brya/variants/vell/gpio.c
2 files changed, 196 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/59305/13
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Change subject: mb/google/herobrine: Initialize USB by calling SOC method
......................................................................
Patch Set 41: Code-Review+2
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