coreboot-gerrit November 2021

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Change in coreboot[master]: soc/mediatek/mt8195: update devapc settings
by Rex-BC Chen (Code Review) 30 Nov '21

30 Nov '21

Attention is currently required from: Hung-Te Lin. Hello Hung-Te Lin, build bot (Jenkins), Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59746 to look at the new patch set (#4). Change subject: soc/mediatek/mt8195: update devapc settings ...................................................................... soc/mediatek/mt8195: update devapc settings In previous patch(chromium:2972318), we only add basic drivers and settings, so we add this patch to set devapc final settings on MT8195. 1. Update permission setting 2. Updtate master domain setting: - domain 1: PCIE0, PCIE1 - domain 2: SPM, SSPM, CPU_EB 3. Set domain remap - MMSYS (4-bit to 2-bit) - TINYSYS (4-bit to 3-bit) - TINYSYS (3-bit to 4-bit) - TINYSYS to EMI (3-bit to 4-bit) - INFRA2 (3-bit to 4-bit) 4. Set SCP domain and ADSP domain - domain 3: SCP - domain 4: ADSP BUG=b:204347737 TEST=build pass Change-Id: I1846d56d2dc362de64b28e0ed9a0681f186af7ee Signed-off-by: Nina Wu <nina-cm.wu(a)mediatek.com> --- M src/soc/mediatek/mt8195/devapc.c M src/soc/mediatek/mt8195/include/soc/addressmap.h M src/soc/mediatek/mt8195/include/soc/devapc.h 3 files changed, 274 insertions(+), 142 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/59746/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/59746 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1846d56d2dc362de64b28e0ed9a0681f186af7ee Gerrit-Change-Number: 59746 Gerrit-PatchSet: 4 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/mediatek/mt8195: update devapc settings
by Rex-BC Chen (Code Review) 30 Nov '21

30 Nov '21

Attention is currently required from: Hung-Te Lin. Hello Hung-Te Lin, build bot (Jenkins), Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59746 to look at the new patch set (#3). Change subject: soc/mediatek/mt8195: update devapc settings ...................................................................... soc/mediatek/mt8195: update devapc settings In previous patch(chromium:2972318), we only add basic drivers and setting, and we add this patch to set devapc final settings on MT8195. 1. Update permission setting 2. Updtate master domain setting: - domain 1: PCIE0, PCIE1 - domain 2: SPM, SSPM, CPU_EB 3. Set domain remap - MMSYS (4-bit to 2-bit) - TINYSYS (4-bit to 3-bit) - TINYSYS (3-bit to 4-bit) - TINYSYS to EMI (3-bit to 4-bit) - INFRA2 (3-bit to 4-bit) 4. Set SCP domain and ADSP domain - domain 3: SCP - domain 4: ADSP BUG=b:204347737 TEST=build pass Change-Id: I1846d56d2dc362de64b28e0ed9a0681f186af7ee Signed-off-by: Nina Wu <nina-cm.wu(a)mediatek.com> --- M src/soc/mediatek/mt8195/devapc.c M src/soc/mediatek/mt8195/include/soc/addressmap.h M src/soc/mediatek/mt8195/include/soc/devapc.h 3 files changed, 274 insertions(+), 142 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/59746/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/59746 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1846d56d2dc362de64b28e0ed9a0681f186af7ee Gerrit-Change-Number: 59746 Gerrit-PatchSet: 3 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/mediatek/mt8195: update devapc settings
by Rex-BC Chen (Code Review) 30 Nov '21

30 Nov '21

Attention is currently required from: Hung-Te Lin, Rex-BC Chen. Hello Hung-Te Lin, build bot (Jenkins), Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59746 to look at the new patch set (#2). Change subject: soc/mediatek/mt8195: update devapc settings ...................................................................... soc/mediatek/mt8195: update devapc settings In previous patch, we only add basic drivers and setting, and we add this patch to set devapc final settings on MT8195. 1. Update permission setting 2. Updtate master domain setting: - domain 1: PCIE0, PCIE1 - domain 2: SPM, SSPM, CPU_EB 3. Set domain remap - MMSYS (4-bit to 2-bit) - TINYSYS (4-bit to 3-bit) - TINYSYS (3-bit to 4-bit) - TINYSYS to EMI (3-bit to 4-bit) - INFRA2 (3-bit to 4-bit) 4. Set SCP domain and ADSP domain - domain 3: SCP - domain 4: ADSP BUG=b:204347737 TEST=build pass Change-Id: I1846d56d2dc362de64b28e0ed9a0681f186af7ee Signed-off-by: Nina Wu <nina-cm.wu(a)mediatek.com> --- M src/soc/mediatek/mt8195/devapc.c M src/soc/mediatek/mt8195/include/soc/addressmap.h M src/soc/mediatek/mt8195/include/soc/devapc.h 3 files changed, 274 insertions(+), 142 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/59746/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59746 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1846d56d2dc362de64b28e0ed9a0681f186af7ee Gerrit-Change-Number: 59746 Gerrit-PatchSet: 2 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/mediatek/mt8195: update devapc settings
by Yu-Ping Wu (Code Review) 30 Nov '21

30 Nov '21

Attention is currently required from: Hung-Te Lin, Rex-BC Chen. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59746 ) Change subject: soc/mediatek/mt8195: update devapc settings ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/59746/comment/a31fd11d_4205ff4c PS1, Line 8: Please explain what this is for. What problem does it try to solve? -- To view, visit https://review.coreboot.org/c/coreboot/+/59746 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1846d56d2dc362de64b28e0ed9a0681f186af7ee Gerrit-Change-Number: 59746 Gerrit-PatchSet: 1 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Comment-Date: Tue, 30 Nov 2021 08:06:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mainboard/google/brya/variants/brask: Enable audio driver option in b...
by Zhuohao Lee (Code Review) 30 Nov '21

30 Nov '21

Attention is currently required from: Tim Wawrzynczak, Adam Liu. Zhuohao Lee has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59610 ) Change subject: mainboard/google/brya/variants/brask: Enable audio driver option in bios-stage for brask ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: Could you please clarify in the bug b/205646582 that why this patch is needed? -- To view, visit https://review.coreboot.org/c/coreboot/+/59610 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I05c5d734ab9cd9a894084398decb5e3bac45ddf2 Gerrit-Change-Number: 59610 Gerrit-PatchSet: 2 Gerrit-Owner: Adam Liu <adam.liu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alan Huang <alan-huang(a)quanta.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Adam Liu <adam.liu(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Tue, 30 Nov 2021 07:58:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/pmc: Drop redundant pmc_ipc.c entry
by Subrata Banik (Code Review) 30 Nov '21

30 Nov '21

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59747 ) Change subject: soc/intel/common/pmc: Drop redundant pmc_ipc.c entry ...................................................................... soc/intel/common/pmc: Drop redundant pmc_ipc.c entry This patch drops redundant `pmc_ipc.c` from Makefile as this file is getting included upon CONFIG_PMC_IPC_ACPI_INTERFACE selection. Change-Id: Ie66f0833daf033ec16210221610508f9fbb1e6c7 Signed-off-by: Subrata Banik <subi.banik(a)gmail.com> --- M src/soc/intel/common/block/pmc/Makefile.inc 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/59747/1 diff --git a/src/soc/intel/common/block/pmc/Makefile.inc b/src/soc/intel/common/block/pmc/Makefile.inc index de69b63..8dacc10 100644 --- a/src/soc/intel/common/block/pmc/Makefile.inc +++ b/src/soc/intel/common/block/pmc/Makefile.inc @@ -2,7 +2,7 @@ bootblock-y += pmclib.c romstage-y += pmclib.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PMC_DISCOVERABLE) += pmc.c -ramstage-y += pmclib.c pmc_ipc.c +ramstage-y += pmclib.c smm-y += pmclib.c verstage-y += pmclib.c postcar-y += pmclib.c -- To view, visit https://review.coreboot.org/c/coreboot/+/59747 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie66f0833daf033ec16210221610508f9fbb1e6c7 Gerrit-Change-Number: 59747 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subi.banik(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/mediatek/mt8195: update devapc settings
by build bot (Jenkins) (Code Review) 30 Nov '21

30 Nov '21

Attention is currently required from: Hung-Te Lin, Yu-Ping Wu. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59746 ) Change subject: soc/mediatek/mt8195: update devapc settings ...................................................................... Patch Set 1: (9 comments) File src/soc/mediatek/mt8195/include/soc/devapc.h: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-134635): https://review.coreboot.org/c/coreboot/+/59746/comment/0327ef6d_a7bfb508 PS1, Line 106: #define NO_PROTECTION2 NO_PROTECTION, NO_PROTECTION Macros with complex values should be enclosed in parentheses Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-134635): https://review.coreboot.org/c/coreboot/+/59746/comment/7f4ea517_ba4eb814 PS1, Line 107: #define NO_PROTECTION3 NO_PROTECTION2, NO_PROTECTION Macros with complex values should be enclosed in parentheses Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-134635): https://review.coreboot.org/c/coreboot/+/59746/comment/5e0b6752_655f51fb PS1, Line 109: #define FORBIDDEN2 FORBIDDEN, FORBIDDEN Macros with complex values should be enclosed in parentheses Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-134635): https://review.coreboot.org/c/coreboot/+/59746/comment/84a3f89d_09464338 PS1, Line 113: #define FORBIDDEN10 FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, \ Macros with complex values should be enclosed in parentheses Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-134635): https://review.coreboot.org/c/coreboot/+/59746/comment/00274cee_526ef157 PS1, Line 116: #define FORBIDDEN11 FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, \ Macros with complex values should be enclosed in parentheses Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-134635): https://review.coreboot.org/c/coreboot/+/59746/comment/8d2a300d_f16f5baa PS1, Line 119: #define FORBIDDEN12 FORBIDDEN11, FORBIDDEN Macros with complex values should be enclosed in parentheses Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-134635): https://review.coreboot.org/c/coreboot/+/59746/comment/b8d9c8f5_a09c2d38 PS1, Line 120: #define FORBIDDEN13 FORBIDDEN12, FORBIDDEN Macros with complex values should be enclosed in parentheses Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-134635): https://review.coreboot.org/c/coreboot/+/59746/comment/af5478f4_d9bb244f PS1, Line 121: #define FORBIDDEN14 FORBIDDEN13, FORBIDDEN Macros with complex values should be enclosed in parentheses Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-134635): https://review.coreboot.org/c/coreboot/+/59746/comment/c425b250_5adb8519 PS1, Line 122: #define FORBIDDEN15 FORBIDDEN14, FORBIDDEN Macros with complex values should be enclosed in parentheses -- To view, visit https://review.coreboot.org/c/coreboot/+/59746 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1846d56d2dc362de64b28e0ed9a0681f186af7ee Gerrit-Change-Number: 59746 Gerrit-PatchSet: 1 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Tue, 30 Nov 2021 07:47:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek/mt8195: update devapc settings
by Rex-BC Chen (Code Review) 30 Nov '21

30 Nov '21

Rex-BC Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59746 ) Change subject: soc/mediatek/mt8195: update devapc settings ...................................................................... soc/mediatek/mt8195: update devapc settings 1. Update permission setting 2. Updtate master domain setting: - domain 1: PCIE0, PCIE1 - domain 2: SPM, SSPM, CPU_EB 3. Set domain remap - MMSYS (4-bit to 2-bit) - TINYSYS (4-bit to 3-bit) - TINYSYS (3-bit to 4-bit) - TINYSYS to EMI (3-bit to 4-bit) - INFRA2 (3-bit to 4-bit) 4. Set SCP domain and ADSP domain - domain 3: SCP - domain 4: ADSP BUG=b:204347737 TEST=build pass Change-Id: I1846d56d2dc362de64b28e0ed9a0681f186af7ee Signed-off-by: Nina Wu <nina-cm.wu(a)mediatek.com> --- M src/soc/mediatek/mt8195/devapc.c M src/soc/mediatek/mt8195/include/soc/addressmap.h M src/soc/mediatek/mt8195/include/soc/devapc.h 3 files changed, 274 insertions(+), 142 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/59746/1 diff --git a/src/soc/mediatek/mt8195/devapc.c b/src/soc/mediatek/mt8195/devapc.c index c41b1ac..1b0de8c 100644 --- a/src/soc/mediatek/mt8195/devapc.c +++ b/src/soc/mediatek/mt8195/devapc.c @@ -7,7 +7,7 @@ static const struct apc_infra_peri_dom_16 infra_ao_sys0_devices[] = { /* 0 */ DAPC_INFRA_AO_SYS0_ATTR("SPM_APB_S", - NO_PROTECTION, FORBIDDEN13, NO_PROTECTION, FORBIDDEN), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13), DAPC_INFRA_AO_SYS0_ATTR("SPM_APB_S-1", NO_PROTECTION, FORBIDDEN15), DAPC_INFRA_AO_SYS0_ATTR("SPM_APB_S-2", @@ -15,26 +15,26 @@ DAPC_INFRA_AO_SYS0_ATTR("SPM_APB_S-4", NO_PROTECTION, FORBIDDEN15), DAPC_INFRA_AO_SYS0_ATTR("APMIXEDSYS_APB_S", - NO_PROTECTION, FORBIDDEN13, NO_PROTECTION, FORBIDDEN), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION3, FORBIDDEN11), DAPC_INFRA_AO_SYS0_ATTR("APMIXEDSYS_APB_S-1", - NO_PROTECTION, FORBIDDEN13, NO_PROTECTION, FORBIDDEN), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13), DAPC_INFRA_AO_SYS0_ATTR("TOPCKGEN_APB_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION3, FORBIDDEN11), DAPC_INFRA_AO_SYS0_ATTR("INFRACFG_AO_APB_S", - NO_PROTECTION, FORBIDDEN13, NO_PROTECTION, FORBIDDEN), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13), DAPC_INFRA_AO_SYS0_ATTR("INFRACFG_AO_MEM_APB_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN3, NO_PROTECTION, FORBIDDEN11), DAPC_INFRA_AO_SYS0_ATTR("PERICFG_AO_APB_S", NO_PROTECTION, FORBIDDEN15), /* 10 */ DAPC_INFRA_AO_SYS0_ATTR("GPIO_APB_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION2, FORBIDDEN12), DAPC_INFRA_AO_SYS0_ATTR("TOPRGU_APB_S", NO_PROTECTION, FORBIDDEN15), DAPC_INFRA_AO_SYS0_ATTR("DSP_IRQ_APB_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN3, NO_PROTECTION, FORBIDDEN11), DAPC_INFRA_AO_SYS0_ATTR("DEVICE_APC_INFRA_AO_APB_S", - SEC_RW_ONLY, FORBIDDEN15), + SEC_RW_ONLY, FORBIDDEN15), DAPC_INFRA_AO_SYS0_ATTR("BCRM_INFRA_AO_APB_S", NO_PROTECTION, FORBIDDEN15), DAPC_INFRA_AO_SYS0_ATTR("DEBUG_CTRL_INFRA_AO_APB_S", @@ -42,16 +42,14 @@ DAPC_INFRA_AO_SYS0_ATTR("AP_CIRQ_EINT_APB_S", NO_PROTECTION, FORBIDDEN15), DAPC_INFRA_AO_SYS0_ATTR("PMIC_WRAP_APB_S", - NO_PROTECTION, FORBIDDEN, FORBIDDEN, NO_PROTECTION, - FORBIDDEN12), + NO_PROTECTION, FORBIDDEN15), DAPC_INFRA_AO_SYS0_ATTR("KP_APB_S", NO_PROTECTION, FORBIDDEN15), DAPC_INFRA_AO_SYS0_ATTR("TOP_MISC_APB_S", NO_PROTECTION, FORBIDDEN15), /* 20 */ DAPC_INFRA_AO_SYS0_ATTR("DVFSRC_APB_S", - NO_PROTECTION, FORBIDDEN, FORBIDDEN, NO_PROTECTION, - FORBIDDEN12), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13), DAPC_INFRA_AO_SYS0_ATTR("MBIST_AO_APB_S", NO_PROTECTION, FORBIDDEN15), DAPC_INFRA_AO_SYS0_ATTR("HDMI_CEC_APB_S", @@ -63,19 +61,16 @@ DAPC_INFRA_AO_SYS0_ATTR("IRRX_APB_S", NO_PROTECTION, FORBIDDEN15), DAPC_INFRA_AO_SYS0_ATTR("SYS_TIMER_APB_S", - NO_PROTECTION, FORBIDDEN, FORBIDDEN, NO_PROTECTION, - FORBIDDEN12), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13), DAPC_INFRA_AO_SYS0_ATTR("MODEM_TEMP_SHARE_APB_S", NO_PROTECTION, FORBIDDEN15), DAPC_INFRA_AO_SYS0_ATTR("PMIF1_APB_S", - NO_PROTECTION, FORBIDDEN, FORBIDDEN, NO_PROTECTION, - FORBIDDEN12), + NO_PROTECTION, FORBIDDEN15), DAPC_INFRA_AO_SYS0_ATTR("PMICSPI_MST_APB_S", - NO_PROTECTION, FORBIDDEN, FORBIDDEN, NO_PROTECTION, - FORBIDDEN12), + NO_PROTECTION, FORBIDDEN15), /* 30 */ DAPC_INFRA_AO_SYS0_ATTR("TIA_APB_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13), DAPC_INFRA_AO_SYS0_ATTR("TOPCKGEN_INFRA_CFG_APB_S", NO_PROTECTION, FORBIDDEN15), DAPC_INFRA_AO_SYS0_ATTR("DRM_DEBUG_TOP_APB_S", @@ -91,15 +86,14 @@ DAPC_INFRA_AO_SYS0_ATTR("SECURITY_AO_APB_S", NO_PROTECTION, FORBIDDEN15), DAPC_INFRA_AO_SYS0_ATTR("SPMI_MST_APB_S", - NO_PROTECTION, FORBIDDEN, FORBIDDEN, NO_PROTECTION, - FORBIDDEN12), + NO_PROTECTION, FORBIDDEN15), DAPC_INFRA_AO_SYS0_ATTR("DEBUG_CTRL_FMEM_AO_APB_S", NO_PROTECTION, FORBIDDEN15), /* 40 */ DAPC_INFRA_AO_SYS0_ATTR("BCRM_FMEM_AO_APB_S", NO_PROTECTION, FORBIDDEN15), DAPC_INFRA_AO_SYS0_ATTR("DEVICE_APC_FMEM_AO_APB_S", - SEC_RW_ONLY, FORBIDDEN15), + SEC_RW_ONLY, FORBIDDEN15), DAPC_INFRA_AO_SYS0_ATTR("PWM_APB_S", NO_PROTECTION, FORBIDDEN15), DAPC_INFRA_AO_SYS0_ATTR("PMSR_APB_S", @@ -141,13 +135,13 @@ DAPC_INFRA_AO_SYS0_ATTR("MCUSYS_CFGREG_APB_S", NO_PROTECTION, FORBIDDEN15), DAPC_INFRA_AO_SYS0_ATTR("MCUSYS_CFGREG_APB_S-1", - NO_PROTECTION, FORBIDDEN13, NO_PROTECTION, FORBIDDEN), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13), DAPC_INFRA_AO_SYS0_ATTR("MCUSYS_CFGREG_APB_S-2", - NO_PROTECTION, FORBIDDEN13, NO_PROTECTION, FORBIDDEN), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13), DAPC_INFRA_AO_SYS0_ATTR("MCUSYS_CFGREG_APB_S-3", - NO_PROTECTION, FORBIDDEN13, NO_PROTECTION, FORBIDDEN), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13), DAPC_INFRA_AO_SYS0_ATTR("MCUSYS_CFGREG_APB_S-4", - NO_PROTECTION, FORBIDDEN13, NO_PROTECTION, FORBIDDEN), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13), DAPC_INFRA_AO_SYS0_ATTR("L3C_S", NO_PROTECTION, FORBIDDEN15), DAPC_INFRA_AO_SYS0_ATTR("L3C_S-1", @@ -160,11 +154,11 @@ NO_PROTECTION, FORBIDDEN15), /* 70 */ DAPC_INFRA_AO_SYS0_ATTR("NNA_APB_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13), DAPC_INFRA_AO_SYS0_ATTR("PCIE0_AXI_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION2, FORBIDDEN14), DAPC_INFRA_AO_SYS0_ATTR("PCIE1_AXI_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION2, FORBIDDEN14), DAPC_INFRA_AO_SYS0_ATTR("VIOSYS_APB0_S", NO_PROTECTION, FORBIDDEN15), DAPC_INFRA_AO_SYS0_ATTR("VIOSYS_APB1_S", @@ -180,42 +174,42 @@ static const struct apc_infra_peri_dom_4 infra_ao_sys1_devices[] = { /* 0 */ DAPC_INFRA_AO_SYS1_ATTR("MM_S_S", - NO_PROTECTION, FORBIDDEN3), + NO_PROTECTION, FORBIDDEN2, NO_PROTECTION), DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-1", - NO_PROTECTION, FORBIDDEN3), + NO_PROTECTION, FORBIDDEN2, NO_PROTECTION), DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-2", - NO_PROTECTION, FORBIDDEN3), + NO_PROTECTION, FORBIDDEN2, NO_PROTECTION), DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-3", - NO_PROTECTION, FORBIDDEN3), + NO_PROTECTION, FORBIDDEN2, NO_PROTECTION), DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-4", - NO_PROTECTION, FORBIDDEN3), + NO_PROTECTION, FORBIDDEN2, NO_PROTECTION), DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-5", - NO_PROTECTION, FORBIDDEN3), + NO_PROTECTION, FORBIDDEN2, NO_PROTECTION), DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-6", - NO_PROTECTION, FORBIDDEN3), + NO_PROTECTION, FORBIDDEN2, NO_PROTECTION), DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-7", - NO_PROTECTION, FORBIDDEN3), + NO_PROTECTION, FORBIDDEN2, NO_PROTECTION), DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-8", - NO_PROTECTION, FORBIDDEN3), + NO_PROTECTION, FORBIDDEN2, NO_PROTECTION), DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-9", - NO_PROTECTION, FORBIDDEN3), + NO_PROTECTION, FORBIDDEN2, NO_PROTECTION), /* 10 */ DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-10", - NO_PROTECTION, FORBIDDEN3), + NO_PROTECTION, FORBIDDEN2, NO_PROTECTION), DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-11", - NO_PROTECTION, FORBIDDEN3), + NO_PROTECTION, FORBIDDEN2, NO_PROTECTION), DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-12", - NO_PROTECTION, FORBIDDEN3), + NO_PROTECTION, FORBIDDEN2, NO_PROTECTION), DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-13", - NO_PROTECTION, FORBIDDEN3), + NO_PROTECTION, FORBIDDEN2, NO_PROTECTION), DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-14", - NO_PROTECTION, FORBIDDEN3), + NO_PROTECTION, FORBIDDEN2, NO_PROTECTION), DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-15", NO_PROTECTION, FORBIDDEN3), DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-16", NO_PROTECTION, FORBIDDEN3), DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-17", - NO_PROTECTION, FORBIDDEN3), + NO_PROTECTION, FORBIDDEN2, NO_PROTECTION), DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-18", NO_PROTECTION, FORBIDDEN3), DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-19", @@ -232,7 +226,7 @@ DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-24", NO_PROTECTION, FORBIDDEN3), DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-25", - NO_PROTECTION, FORBIDDEN3), + NO_PROTECTION, FORBIDDEN2, NO_PROTECTION), DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-26", NO_PROTECTION, FORBIDDEN3), DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-27", @@ -1100,34 +1094,34 @@ static const struct apc_infra_peri_dom_16 peri_ao_sys0_devices[] = { /* 0 */ DAPC_PERI_AO_SYS0_ATTR("DEVICE_APC_PERI_AO_APB_S", - SEC_RW_ONLY, FORBIDDEN15), + SEC_RW_ONLY, FORBIDDEN15), DAPC_PERI_AO_SYS0_ATTR("BCRM_PERI_AO_APB_S", NO_PROTECTION, FORBIDDEN15), DAPC_PERI_AO_SYS0_ATTR("DEBUG_CTRL_PERI_AO_APB_S", NO_PROTECTION, FORBIDDEN15), DAPC_PERI_AO_SYS0_ATTR("PWR_MD32_S", - NO_PROTECTION, FORBIDDEN, FORBIDDEN, NO_PROTECTION, FORBIDDEN12), + NO_PROTECTION, FORBIDDEN15), DAPC_PERI_AO_SYS0_ATTR("PWR_MD32_S-1", - NO_PROTECTION, FORBIDDEN, FORBIDDEN, NO_PROTECTION, FORBIDDEN12), + NO_PROTECTION, FORBIDDEN15), DAPC_PERI_AO_SYS0_ATTR("PWR_MD32_S-2", - NO_PROTECTION, FORBIDDEN, FORBIDDEN, NO_PROTECTION, FORBIDDEN12), + NO_PROTECTION, FORBIDDEN15), DAPC_PERI_AO_SYS0_ATTR("PWR_MD32_S-3", - NO_PROTECTION, FORBIDDEN, FORBIDDEN, NO_PROTECTION, FORBIDDEN12), + NO_PROTECTION, FORBIDDEN15), DAPC_PERI_AO_SYS0_ATTR("PWR_MD32_S-4", - NO_PROTECTION, FORBIDDEN, FORBIDDEN, NO_PROTECTION, FORBIDDEN12), + NO_PROTECTION, FORBIDDEN15), DAPC_PERI_AO_SYS0_ATTR("PWR_MD32_S-5", - NO_PROTECTION, FORBIDDEN, FORBIDDEN, NO_PROTECTION, FORBIDDEN12), + NO_PROTECTION, FORBIDDEN15), DAPC_PERI_AO_SYS0_ATTR("PWR_MD32_S-6", - NO_PROTECTION, FORBIDDEN, FORBIDDEN, NO_PROTECTION, FORBIDDEN12), + NO_PROTECTION, FORBIDDEN15), /* 10 */ DAPC_PERI_AO_SYS0_ATTR("PWR_MD32_S-7", - NO_PROTECTION, FORBIDDEN, FORBIDDEN, NO_PROTECTION, FORBIDDEN12), + NO_PROTECTION, FORBIDDEN15), DAPC_PERI_AO_SYS0_ATTR("PWR_MD32_S-8", - NO_PROTECTION, FORBIDDEN, FORBIDDEN, NO_PROTECTION, FORBIDDEN12), + NO_PROTECTION, FORBIDDEN15), DAPC_PERI_AO_SYS0_ATTR("PWR_MD32_S-9", - NO_PROTECTION, FORBIDDEN, FORBIDDEN, NO_PROTECTION, FORBIDDEN12), + NO_PROTECTION, FORBIDDEN15), DAPC_PERI_AO_SYS0_ATTR("PWR_MD32_S-10", - NO_PROTECTION, FORBIDDEN, FORBIDDEN, NO_PROTECTION, FORBIDDEN12), + NO_PROTECTION, FORBIDDEN15), DAPC_PERI_AO_SYS0_ATTR("SSUSB_S", NO_PROTECTION, FORBIDDEN15), DAPC_PERI_AO_SYS0_ATTR("SSUSB_S-1", @@ -1135,83 +1129,79 @@ DAPC_PERI_AO_SYS0_ATTR("SSUSB_S-2", NO_PROTECTION, FORBIDDEN15), DAPC_PERI_AO_SYS0_ATTR("DEBUGSYS_APB_S", - NO_PROTECTION, FORBIDDEN13, NO_PROTECTION, FORBIDDEN), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13), DAPC_PERI_AO_SYS0_ATTR("DRAMC_MD32_S0_APB_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13), DAPC_PERI_AO_SYS0_ATTR("DRAMC_MD32_S0_APB_S-1", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN2, + NO_PROTECTION, FORBIDDEN10), /* 20 */ DAPC_PERI_AO_SYS0_ATTR("DRAMC_MD32_S1_APB_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13), DAPC_PERI_AO_SYS0_ATTR("DRAMC_MD32_S1_APB_S-1", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN2, + NO_PROTECTION, FORBIDDEN10), DAPC_PERI_AO_SYS0_ATTR("NOR_AXI_S", NO_PROTECTION, FORBIDDEN15), DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH0_TOP0_APB_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13), DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH0_TOP1_APB_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13), DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH0_TOP2_APB_S", - NO_PROTECTION, FORBIDDEN, FORBIDDEN, NO_PROTECTION, FORBIDDEN12), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13), DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH0_TOP3_APB_S", - NO_PROTECTION, FORBIDDEN, FORBIDDEN, NO_PROTECTION, FORBIDDEN12), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13), DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH0_TOP4_APB_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13), DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH0_TOP5_APB_S", - NO_PROTECTION, FORBIDDEN, FORBIDDEN, NO_PROTECTION, FORBIDDEN12), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13), DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH0_TOP6_APB_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13), /* 30 */ DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH1_TOP0_APB_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13), DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH1_TOP1_APB_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13), DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH1_TOP2_APB_S", - NO_PROTECTION, FORBIDDEN, FORBIDDEN, NO_PROTECTION, FORBIDDEN12), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13), DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH1_TOP3_APB_S", - NO_PROTECTION, FORBIDDEN, FORBIDDEN, NO_PROTECTION, FORBIDDEN12), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13), DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH1_TOP4_APB_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13), DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH1_TOP5_APB_S", - NO_PROTECTION, FORBIDDEN, FORBIDDEN, NO_PROTECTION, FORBIDDEN12), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13), DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH1_TOP6_APB_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13), DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH2_TOP0_APB_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13), DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH2_TOP1_APB_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13), DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH2_TOP2_APB_S", - NO_PROTECTION, FORBIDDEN, FORBIDDEN, NO_PROTECTION, - FORBIDDEN12), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13), /* 40 */ DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH2_TOP3_APB_S", - NO_PROTECTION, FORBIDDEN, FORBIDDEN, NO_PROTECTION, - FORBIDDEN12), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13), DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH2_TOP4_APB_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13), DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH2_TOP5_APB_S", - NO_PROTECTION, FORBIDDEN, FORBIDDEN, NO_PROTECTION, - FORBIDDEN12), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13), DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH2_TOP6_APB_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13), DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH3_TOP0_APB_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13), DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH3_TOP1_APB_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13), DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH3_TOP2_APB_S", - NO_PROTECTION, FORBIDDEN, FORBIDDEN, NO_PROTECTION, - FORBIDDEN12), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13), DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH3_TOP3_APB_S", - NO_PROTECTION, FORBIDDEN, FORBIDDEN, NO_PROTECTION, - FORBIDDEN12), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13), DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH3_TOP4_APB_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13), DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH3_TOP5_APB_S", - NO_PROTECTION, FORBIDDEN, FORBIDDEN, NO_PROTECTION, - FORBIDDEN12), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13), /* 50 */ DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH3_TOP6_APB_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13), DAPC_PERI_AO_SYS0_ATTR("CCIF2_AP_APB_S", NO_PROTECTION, FORBIDDEN15), DAPC_PERI_AO_SYS0_ATTR("CCIF2_MD_APB_S", @@ -1240,7 +1230,7 @@ static const struct apc_infra_peri_dom_8 peri_ao_sys1_devices[] = { /* 0 */ DAPC_PERI_AO_SYS1_ATTR("TINSYS_S", - NO_PROTECTION, FORBIDDEN7), + NO_PROTECTION, FORBIDDEN3, NO_PROTECTION, FORBIDDEN3), DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-1", NO_PROTECTION, FORBIDDEN7), DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-2", @@ -1252,22 +1242,22 @@ DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-5", NO_PROTECTION, FORBIDDEN7), DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-6", - NO_PROTECTION, FORBIDDEN7), + NO_PROTECTION, FORBIDDEN3, NO_PROTECTION, FORBIDDEN3), DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-7", - NO_PROTECTION, FORBIDDEN7), + NO_PROTECTION, FORBIDDEN3, NO_PROTECTION, FORBIDDEN3), DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-8", - NO_PROTECTION, FORBIDDEN7), + NO_PROTECTION, FORBIDDEN3, NO_PROTECTION, FORBIDDEN3), DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-9", - NO_PROTECTION, FORBIDDEN7), + NO_PROTECTION, FORBIDDEN3, NO_PROTECTION, FORBIDDEN3), /* 10 */ DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-10", - NO_PROTECTION, FORBIDDEN7), + NO_PROTECTION, FORBIDDEN3, NO_PROTECTION, FORBIDDEN3), DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-11", - NO_PROTECTION, FORBIDDEN7), + NO_PROTECTION, FORBIDDEN3, NO_PROTECTION, FORBIDDEN3), DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-12", - NO_PROTECTION, FORBIDDEN7), + NO_PROTECTION, FORBIDDEN3, NO_PROTECTION, FORBIDDEN3), DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-13", - NO_PROTECTION, FORBIDDEN7), + NO_PROTECTION, FORBIDDEN3, NO_PROTECTION, FORBIDDEN3), DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-14", NO_PROTECTION, FORBIDDEN7), DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-15", @@ -1275,18 +1265,18 @@ DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-16", NO_PROTECTION, FORBIDDEN7), DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-17", - NO_PROTECTION, FORBIDDEN7), + NO_PROTECTION, FORBIDDEN3, NO_PROTECTION, FORBIDDEN3), DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-18", - NO_PROTECTION, FORBIDDEN7), + NO_PROTECTION, FORBIDDEN3, NO_PROTECTION, FORBIDDEN3), DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-19", - NO_PROTECTION, FORBIDDEN7), + NO_PROTECTION, FORBIDDEN3, NO_PROTECTION, FORBIDDEN3), /* 20 */ DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-20", - NO_PROTECTION, FORBIDDEN7), + NO_PROTECTION, FORBIDDEN3, NO_PROTECTION, FORBIDDEN3), DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-21", - NO_PROTECTION, FORBIDDEN7), + NO_PROTECTION, FORBIDDEN3, NO_PROTECTION, FORBIDDEN3), DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-22", - NO_PROTECTION, FORBIDDEN7), + NO_PROTECTION, FORBIDDEN3, NO_PROTECTION, FORBIDDEN3), }; static const struct apc_infra_peri_dom_16 peri2_ao_sys0_devices[] = { @@ -1300,7 +1290,7 @@ DAPC_PERI2_AO_SYS0_ATTR("BND_EAST_APB0_S", NO_PROTECTION, FORBIDDEN15), DAPC_PERI2_AO_SYS0_ATTR("BND_EAST_APB1_S", - NO_PROTECTION, FORBIDDEN13, NO_PROTECTION, FORBIDDEN), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13), DAPC_PERI2_AO_SYS0_ATTR("BND_EAST_APB2_S", NO_PROTECTION, FORBIDDEN15), DAPC_PERI2_AO_SYS0_ATTR("BND_EAST_APB3_S", @@ -1449,8 +1439,7 @@ DAPC_PERI2_AO_SYS0_ATTR("MBIST_PDN_APB_S", NO_PROTECTION, FORBIDDEN15), DAPC_PERI2_AO_SYS0_ATTR("INFRACFG_PDN_APB_S", - NO_PROTECTION, FORBIDDEN, FORBIDDEN, NO_PROTECTION, - FORBIDDEN12), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13), DAPC_PERI2_AO_SYS0_ATTR("TRNG_APB_S", NO_PROTECTION, FORBIDDEN15), DAPC_PERI2_AO_SYS0_ATTR("GCPU_APB_S", @@ -1488,10 +1477,9 @@ DAPC_PERI2_AO_SYS0_ATTR("INFRA_IOMMU_WRAP_APB4_S", NO_PROTECTION, FORBIDDEN15), DAPC_PERI2_AO_SYS0_ATTR("EMI_APB_S", - NO_PROTECTION, FORBIDDEN, FORBIDDEN, NO_PROTECTION, - FORBIDDEN12), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13), DAPC_PERI2_AO_SYS0_ATTR("EMI_MPU_APB_S", - NO_PROTECTION, FORBIDDEN15), + SEC_RW_ONLY, FORBIDDEN15), DAPC_PERI2_AO_SYS0_ATTR("DEVICE_MPU_PDN_APB_S", NO_PROTECTION, FORBIDDEN15), DAPC_PERI2_AO_SYS0_ATTR("APDMA_APB_S", @@ -1520,8 +1508,7 @@ DAPC_PERI2_AO_SYS0_ATTR("PERI_SLOW_M_APB_S", NO_PROTECTION, FORBIDDEN15), DAPC_PERI2_AO_SYS0_ATTR("EMI_SUB_INFRA_APB_S", - NO_PROTECTION, FORBIDDEN, FORBIDDEN, NO_PROTECTION, - FORBIDDEN12), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13), DAPC_PERI2_AO_SYS0_ATTR("EMI_MPU_SUB_INFRA_APB_S", NO_PROTECTION, FORBIDDEN15), /* 110 */ @@ -1530,8 +1517,7 @@ DAPC_PERI2_AO_SYS0_ATTR("MBIST_PDN_SUB_INFRA_APB_S", NO_PROTECTION, FORBIDDEN15), DAPC_PERI2_AO_SYS0_ATTR("INFRACFG_MEM_SUB_INFRA_APB_S", - NO_PROTECTION, FORBIDDEN, FORBIDDEN, NO_PROTECTION, - FORBIDDEN12), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13), DAPC_PERI2_AO_SYS0_ATTR("BCRM_SUB_INFRA_AO_APB_S", NO_PROTECTION, FORBIDDEN15), DAPC_PERI2_AO_SYS0_ATTR("DEBUG_CTRL_SUB_INFRA_AO_APB_S", @@ -1543,7 +1529,7 @@ DAPC_PERI2_AO_SYS0_ATTR("SSC_SUB_INFRA_APB2_S", NO_PROTECTION, FORBIDDEN15), DAPC_PERI2_AO_SYS0_ATTR("INFRACFG_AO_MEM_SUB_INFRA_APB_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN3, NO_PROTECTION, FORBIDDEN11), DAPC_PERI2_AO_SYS0_ATTR("SUB_FAKE_ENGINE_MM_S", NO_PROTECTION, FORBIDDEN15), /* 120 */ @@ -1570,9 +1556,9 @@ DAPC_PERI_PAR_AO_SYS0_ATTR("MSDC2_S", NO_PROTECTION, FORBIDDEN15), DAPC_PERI_PAR_AO_SYS0_ATTR("PCIE0_AHB_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION2, FORBIDDEN14), DAPC_PERI_PAR_AO_SYS0_ATTR("PCIE1_AHB_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION2, FORBIDDEN14), DAPC_PERI_PAR_AO_SYS0_ATTR("SSUSB_P1_S", NO_PROTECTION, FORBIDDEN15), /* 10 */ @@ -1583,7 +1569,7 @@ DAPC_PERI_PAR_AO_SYS0_ATTR("AUXADC_APB_S", NO_PROTECTION, FORBIDDEN15), DAPC_PERI_PAR_AO_SYS0_ATTR("UART0_APB_S", - NO_PROTECTION, FORBIDDEN13, NO_PROTECTION, FORBIDDEN), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13), DAPC_PERI_PAR_AO_SYS0_ATTR("UART1_APB_S", NO_PROTECTION, FORBIDDEN15), DAPC_PERI_PAR_AO_SYS0_ATTR("UART2_APB_S", @@ -1598,7 +1584,7 @@ NO_PROTECTION, FORBIDDEN15), /* 20 */ DAPC_PERI_PAR_AO_SYS0_ATTR("PTP_THERM_CTRL_APB_S", - NO_PROTECTION, FORBIDDEN13, NO_PROTECTION, FORBIDDEN), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13), DAPC_PERI_PAR_AO_SYS0_ATTR("PERI_MBIST_PDN_APB_S", NO_PROTECTION, FORBIDDEN15), DAPC_PERI_PAR_AO_SYS0_ATTR("DISP_PWM_APB_S", @@ -1633,9 +1619,9 @@ DAPC_PERI_PAR_AO_SYS0_ATTR("BCRM_PERI_PAR_PDN_APB_S", NO_PROTECTION, FORBIDDEN15), DAPC_PERI_PAR_AO_SYS0_ATTR("DEVICE_APC_PERI_PAR_PDN_APB_S", - SEC_RW_ONLY, FORBIDDEN15), + SEC_RW_ONLY, FORBIDDEN15), DAPC_PERI_PAR_AO_SYS0_ATTR("PTP_THERM_CTRL2_APB_S", - NO_PROTECTION, FORBIDDEN13, NO_PROTECTION, FORBIDDEN), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13), DAPC_PERI_PAR_AO_SYS0_ATTR("IIC_P2P_REMAP_APB_S", NO_PROTECTION, FORBIDDEN15), /* 40 */ @@ -1768,6 +1754,9 @@ printk(BIOS_DEBUG, "[DEVAPC] (INFRA_AO)MAS_SEC_0: %#x\n", read32(getreg(base, MAS_SEC_0))); + + printk(BIOS_DEBUG, "[DEVAPC] (INFRA_AO %#lx)DOM_REMAP_0_0: %#x\n", + base, read32(getreg(base, DOM_REMAP_0_0))); } static void dump_peri_ao_apc(uintptr_t base) @@ -1818,19 +1807,91 @@ read32(getreg(base, MAS_SEC_0))); } +static void dump_fmem_ao(uintptr_t base) +{ + printk(BIOS_DEBUG, "[DEVAPC] (DEVAPC_FMEM_AO_BASE %#lx)DOM_REMAP_0_0:%#x\n", + base, read32(getreg(base, DOM_REMAP_0_0))); +} + +static void dump_infra2_ao_apc(uintptr_t base) +{ + printk(BIOS_DEBUG, "[DEVAPC] (DEVAPC_INFRA2_AO_BASE %#lx)DOM_REMAP_0_0:%#x\n", + base, read32(getreg(base, DOM_REMAP_0_0))); +} + +static void dump_scp_master(uintptr_t base) +{ + printk(BIOS_DEBUG, "[DEVAPC] SCP:%#x ADSP:%#x Lock:%#x\n", + read32(getreg(base, SCP_DOM)), + read32(getreg(base, ADSP_DOM)), + read32(getreg(base, ONETIME_LOCK))); +} + static void infra_init(uintptr_t base) { /* Side band */ SET32_BITFIELDS(getreg(base, MAS_SEC_0), CPU_EB_SEC, SECURE_TRANS); + /* Master Domain */ + SET32_BITFIELDS(getreg(base, MAS_DOM_0), + SCP_SSPM_DOM, DOMAIN_2, + CPU_EB_DOM, DOMAIN_2); + /* Default APC Setting */ set_infra_ao_apc(base); + + /* + * Domain Remap: MMSYS slave domain remap (4-bit to 2-bit) + * 1. From domain 0 to domain 0 (no protection for all) + * 2. From domain 1, 2, 4, 5 to domain 1 (forbidden for all) + * 3. From domain 3 to domain 3 + * 4. others from XXX to domain 0 + */ + SET32_BITFIELDS(getreg(base, DOM_REMAP_2_0), + TWO_BIT_DOM_REMAP_0, DOMAIN_0, + TWO_BIT_DOM_REMAP_1, DOMAIN_1, + TWO_BIT_DOM_REMAP_2, DOMAIN_1, + TWO_BIT_DOM_REMAP_3, DOMAIN_3, + TWO_BIT_DOM_REMAP_4, DOMAIN_1, + TWO_BIT_DOM_REMAP_5, DOMAIN_1); + /* + * Domain Remap: TINYSYS (3-bit to 4-bit) + * 1. SCP from 3 to 3 + * 2. DSP from 4 to 4 + * 3. others from XXX to 15 + */ + SET32_BITFIELDS(getreg(base, DOM_REMAP_0_0), + FOUR_BIT_DOM_REMAP_0, DOMAIN_15, + FOUR_BIT_DOM_REMAP_1, DOMAIN_15, + FOUR_BIT_DOM_REMAP_2, DOMAIN_15, + FOUR_BIT_DOM_REMAP_3, DOMAIN_3, + FOUR_BIT_DOM_REMAP_4, DOMAIN_4, + FOUR_BIT_DOM_REMAP_5, DOMAIN_15, + FOUR_BIT_DOM_REMAP_6, DOMAIN_15, + FOUR_BIT_DOM_REMAP_7, DOMAIN_15); } static void peri_init(uintptr_t base) { /* Default APC Setting */ set_peri_ao_apc(base); + + /* Master Domain */ + SET32_BITFIELDS(getreg(base, MAS_DOM_0), SPM_DOM, DOMAIN_2); + + /* + * Domain Remap: TINYSYS slave domain remap (4-bit to 3-bit) + * 1. From domain 0 to domain 0 (no protection for all) + * 2. From domain 1 ~ 5 to domain 1 ~ 5 + * 3. others from XXX to domain 0 (no protection for all) + */ + SET32_BITFIELDS(getreg(base, DOM_REMAP_0_0), + THREE_BIT_DOM_REMAP_0, DOMAIN_0, + THREE_BIT_DOM_REMAP_1, DOMAIN_1, + THREE_BIT_DOM_REMAP_2, DOMAIN_2, + THREE_BIT_DOM_REMAP_3, DOMAIN_3, + THREE_BIT_DOM_REMAP_4, DOMAIN_4, + THREE_BIT_DOM_REMAP_5, DOMAIN_5); } static void peri2_init(uintptr_t base) @@ -1850,10 +1911,56 @@ SSUSB_P2_SEC, SECURE_TRANS, SSUSB_P3_SEC, SECURE_TRANS); + /* Master Domain */ + SET32_BITFIELDS(getreg(base, MAS_DOM_4), + PCIE0_DOM, DOMAIN_1, + PCIE1_DOM, DOMAIN_1); + /* Default APC Setting */ set_peri_par_ao_apc(base); } +static void fmem_master_init(uintptr_t base) +{ + /* + * Domain Remap: TINYSYS to EMI (3-bit to 4-bit) + * 1. SCP from 3 to 3 + * 2. DSP from 4 to 4 + * 3. others from XXX to 15 + */ + SET32_BITFIELDS(getreg(base, DOM_REMAP_0_0), + FOUR_BIT_DOM_REMAP_0, DOMAIN_15, + FOUR_BIT_DOM_REMAP_1, DOMAIN_15, + FOUR_BIT_DOM_REMAP_2, DOMAIN_15, + FOUR_BIT_DOM_REMAP_3, DOMAIN_3, + FOUR_BIT_DOM_REMAP_4, DOMAIN_4, + FOUR_BIT_DOM_REMAP_5, DOMAIN_15, + FOUR_BIT_DOM_REMAP_6, DOMAIN_15, + FOUR_BIT_DOM_REMAP_7, DOMAIN_15); +} + +static void infra2_init(uintptr_t base) +{ + SET32_BITFIELDS(getreg(base, DOM_REMAP_0_0), + FOUR_BIT_DOM_REMAP_0, DOMAIN_15, + FOUR_BIT_DOM_REMAP_1, DOMAIN_15, + FOUR_BIT_DOM_REMAP_2, DOMAIN_15, + FOUR_BIT_DOM_REMAP_3, DOMAIN_3, + FOUR_BIT_DOM_REMAP_4, DOMAIN_4, + FOUR_BIT_DOM_REMAP_5, DOMAIN_15, + FOUR_BIT_DOM_REMAP_6, DOMAIN_15, + FOUR_BIT_DOM_REMAP_7, DOMAIN_15); +} + +static void scp_master_init(uintptr_t base) +{ + write32(getreg(base, SCP_DOM), DOMAIN_3); + write32(getreg(base, ADSP_DOM), DOMAIN_4); + + /* Let SCP_DOM and ADSP_DOM registers be read-only for security */ + write32(getreg(base, ONETIME_LOCK), 0x5); +} + struct devapc_init_ops { uintptr_t base; void (*init)(uintptr_t base); @@ -1863,6 +1970,9 @@ { DEVAPC_PERI_AO_BASE, peri_init, dump_peri_ao_apc }, { DEVAPC_PERI2_AO_BASE, peri2_init, dump_peri2_ao_apc }, { DEVAPC_PERI_PAR_AO_BASE, peri_par_init, dump_peri_par_ao_apc }, + { DEVAPC_FMEM_AO_BASE, fmem_master_init, dump_fmem_ao }, + { DEVAPC_INFRA2_AO_BASE, infra2_init, dump_infra2_ao_apc }, + { SCP_CFG_BASE, scp_master_init, dump_scp_master }, }; void dapc_init(void) diff --git a/src/soc/mediatek/mt8195/include/soc/addressmap.h b/src/soc/mediatek/mt8195/include/soc/addressmap.h index d9486b3..e5fd822 100644 --- a/src/soc/mediatek/mt8195/include/soc/addressmap.h +++ b/src/soc/mediatek/mt8195/include/soc/addressmap.h @@ -43,6 +43,7 @@ I2C_DMA_BASE = IO_PHYS + 0x00220080, EMI1_SUB_BASE = IO_PHYS + 0x00225000, EMI0_MPU_BASE = IO_PHYS + 0x00226000, + DEVAPC_INFRA2_AO_BASE = IO_PHYS + 0x00228000, DRAMC_CHA_AO_BASE = IO_PHYS + 0x00230000, INFRA_TRACKER_BASE = IO_PHYS + 0x00314000, SSPM_SRAM_BASE = IO_PHYS + 0x00400000, diff --git a/src/soc/mediatek/mt8195/include/soc/devapc.h b/src/soc/mediatek/mt8195/include/soc/devapc.h index df81972..5267b3b 100644 --- a/src/soc/mediatek/mt8195/include/soc/devapc.h +++ b/src/soc/mediatek/mt8195/include/soc/devapc.h @@ -17,10 +17,17 @@ DOM_REMAP_1_1 = 0x814, DOM_REMAP_2_0 = 0x820, MAS_DOM_0 = 0x0900, + MAS_DOM_4 = 0x0910, MAS_SEC_0 = 0x0A00, AO_APC_CON = 0x0F00, }; +enum scp_offset { + SCP_DOM = 0xA5080, + ADSP_DOM = 0xA5088, + ONETIME_LOCK = 0xA5104, +}; + /****************************************************************************** * STRUCTURE DEFINITION ******************************************************************************/ @@ -96,18 +103,23 @@ PERM_ATTR12, PERM_ATTR13, \ PERM_ATTR14, PERM_ATTR15) +#define NO_PROTECTION2 NO_PROTECTION, NO_PROTECTION +#define NO_PROTECTION3 NO_PROTECTION2, NO_PROTECTION + +#define FORBIDDEN2 FORBIDDEN, FORBIDDEN #define FORBIDDEN3 FORBIDDEN, FORBIDDEN, FORBIDDEN #define FORBIDDEN7 FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, \ FORBIDDEN, FORBIDDEN -#define FORBIDDEN12 FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, \ +#define FORBIDDEN10 FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, \ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, \ - FORBIDDEN, FORBIDDEN -#define FORBIDDEN13 FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, \ + FORBIDDEN +#define FORBIDDEN11 FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, \ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, \ - FORBIDDEN, FORBIDDEN, FORBIDDEN -#define FORBIDDEN15 FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, \ - FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, \ - FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN + FORBIDDEN +#define FORBIDDEN12 FORBIDDEN11, FORBIDDEN +#define FORBIDDEN13 FORBIDDEN12, FORBIDDEN +#define FORBIDDEN14 FORBIDDEN13, FORBIDDEN +#define FORBIDDEN15 FORBIDDEN14, FORBIDDEN enum devapc_sys_dom_num { DOM_NUM_INFRA_AO_SYS0 = 16, @@ -144,6 +156,10 @@ DEFINE_BIT(CPU_EB_SEC, 1) DEFINE_BITFIELD(CPU_EB_DOM, 11, 8) /* 1 */ +DEFINE_BITFIELD(SCP_SSPM_DOM, 19, 16) /* 2 */ + +/* PERI */ +DEFINE_BITFIELD(SPM_DOM, 11, 8) /* 1 */ /* PERI_PAR */ DEFINE_BIT(SSUSB_SEC, 21) @@ -153,6 +169,9 @@ DEFINE_BIT(SSUSB_P2_SEC, 3) DEFINE_BIT(SSUSB_P3_SEC, 4) +DEFINE_BITFIELD(PCIE0_DOM, 11, 8) /* 17 */ +DEFINE_BITFIELD(PCIE1_DOM, 19, 16) /* 18 */ + /* Domain Remap */ DEFINE_BITFIELD(FOUR_BIT_DOM_REMAP_0, 3, 0) DEFINE_BITFIELD(FOUR_BIT_DOM_REMAP_1, 7, 4) @@ -168,11 +187,13 @@ DEFINE_BITFIELD(THREE_BIT_DOM_REMAP_2, 8, 6) DEFINE_BITFIELD(THREE_BIT_DOM_REMAP_3, 11, 9) DEFINE_BITFIELD(THREE_BIT_DOM_REMAP_4, 14, 12) +DEFINE_BITFIELD(THREE_BIT_DOM_REMAP_5, 17, 15) -DEFINE_BITFIELD(TWO_BIT_DOM_REMAP_0, 1, 0) -DEFINE_BITFIELD(TWO_BIT_DOM_REMAP_1, 3, 2) -DEFINE_BITFIELD(TWO_BIT_DOM_REMAP_2, 5, 4) -DEFINE_BITFIELD(TWO_BIT_DOM_REMAP_3, 7, 6) -DEFINE_BITFIELD(TWO_BIT_DOM_REMAP_4, 9, 8) +DEFINE_BITFIELD(TWO_BIT_DOM_REMAP_0, 1, 0) +DEFINE_BITFIELD(TWO_BIT_DOM_REMAP_1, 3, 2) +DEFINE_BITFIELD(TWO_BIT_DOM_REMAP_2, 5, 4) +DEFINE_BITFIELD(TWO_BIT_DOM_REMAP_3, 7, 6) +DEFINE_BITFIELD(TWO_BIT_DOM_REMAP_4, 9, 8) +DEFINE_BITFIELD(TWO_BIT_DOM_REMAP_5, 11, 10) #endif /* SOC_MEDIATEK_MT8195_DEVAPC_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/59746 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1846d56d2dc362de64b28e0ed9a0681f186af7ee Gerrit-Change-Number: 59746 Gerrit-PatchSet: 1 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/alderlake: Add support for x86_64 [Don't merge]
by Subrata Banik (Code Review) 30 Nov '21

30 Nov '21

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59745 ) Change subject: soc/intel/alderlake: Add support for x86_64 [Don't merge] ...................................................................... soc/intel/alderlake: Add support for x86_64 [Don't merge] Allow to compile the experimental x86_64 code. Change-Id: I0ea8fd9986224b0b552e982ecc2cbef07bdcca78 Signed-off-by: Subrata Banik <subi.banik(a)gmail.com> --- M src/soc/intel/alderlake/Kconfig 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/59745/1 diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index e5d6d6b..8db03af 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -84,6 +84,8 @@ select UDELAY_TSC select UDK_202005_BINDING select DISPLAY_FSP_VERSION_INFO + select HAVE_EXP_X86_64_SUPPORT + select USE_EXP_X86_64_SUPPORT config ALDERLAKE_CAR_ENHANCED_NEM bool -- To view, visit https://review.coreboot.org/c/coreboot/+/59745 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0ea8fd9986224b0b552e982ecc2cbef07bdcca78 Gerrit-Change-Number: 59745 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subi.banik(a)gmail.com> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: helpers: Add fls support
by Yu-Ping Wu (Code Review) 30 Nov '21

30 Nov '21

Attention is currently required from: Hung-Te Lin, Shelley Chen, Paul Menzel, Jianjun Wang. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59738 ) Change subject: helpers: Add fls support ...................................................................... Patch Set 1: (6 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/59738/comment/a5f12654_c430502d PS1, Line 12: only used define fls only https://review.coreboot.org/c/coreboot/+/59738/comment/caf3f59a_515945dd PS1, Line 15: This code is copied from Linux kernel in: include/asm-generic/bitops/fls.h The license here (BSD) is different (from kernel's GPL-2.0), so we usually don't copy things from kernel. No need to mention that in the commit message. File src/commonlib/bsd/include/commonlib/bsd/helpers.h: https://review.coreboot.org/c/coreboot/+/59738/comment/488099de_1d1313c8 PS1, Line 129: ARCH_X86 We should use #if CONFIG(ARCH_X86) There's build error for x86 platforms: In file included from src/commonlib/include/commonlib/helpers.h:10, from src/include/stddef.h:4, from src/include/stdarg.h:11, from src/include/console/vtxprintf.h:6, from src/include/console/console.h:7, from src/cpu/x86/mtrr/debug.c:3: src/commonlib/bsd/include/commonlib/bsd/helpers.h:137:28: note: previous definition of 'fls' with type 'int(unsigned int)' 137 | static __always_inline int fls(unsigned int x) | ^~~ make[1]: *** [Makefile:381: /cb-build/coreboot-gerrit.0/chromeos/AMD_MAJOLICA/bootblock/cpu/x86/mtrr/debug.o] Error 1 make[1]: Leaving directory '/home/coreboot/node-root/workspace/coreboot-gerrit' EMULATION_QEMU_X86_Q35_SMM_TSEG build FAILED after 2s! https://review.coreboot.org/c/coreboot/+/59738/comment/d134ec8b_8f17fa5f PS1, Line 132: @x: the word to search @param x Input number. https://review.coreboot.org/c/coreboot/+/59738/comment/8974d8bc_6aa4d9f0 PS1, Line 134: ffs There's no such function here. Please remove the comment. https://review.coreboot.org/c/coreboot/+/59738/comment/d61c5775_8ca4e091 PS1, Line 137: fls Please add unit tests. See CB:56543 as an example. -- To view, visit https://review.coreboot.org/c/coreboot/+/59738 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib458abfec7e03b2979569a8440a6e69b0285ac32 Gerrit-Change-Number: 59738 Gerrit-PatchSet: 1 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Comment-Date: Tue, 30 Nov 2021 07:31:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit November 2021