coreboot-gerrit November 2021

coreboot-gerrit@coreboot.org

1 participants
6394 discussions

Change in coreboot[master]: drivers/intel/fsp2_0: Add support for FSP runs in long mode (x86_64)
by Subrata Banik (Code Review) 30 Nov '21

30 Nov '21

Attention is currently required from: Andrey Petrov, Patrick Rudolph. Hello Andrey Petrov, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59744 to look at the new patch set (#2). Change subject: drivers/intel/fsp2_0: Add support for FSP runs in long mode (x86_64) ...................................................................... drivers/intel/fsp2_0: Add support for FSP runs in long mode (x86_64) Add new Kconfig `PLATFORM_USES_FSP2_X86_64` to mark FSP binarycapable of running in x86_64 mode. Fix the compilation issue by addingrequired FSP headers to make the code compiled with`HAVE_EXP_X86_64_SUPPORT` Kconfig enabled. TEST=Verified on Intel Alder Lake with experimental 64-bit support FSP. Change-Id: If12b63a282c660da6f57fe23b0b848e2d155853f Signed-off-by: Subrata Banik <subi.banik(a)gmail.com> --- M src/drivers/intel/fsp2_0/Kconfig M src/drivers/intel/fsp2_0/include/fsp/info_header.h M src/vendorcode/intel/edk2/UDK2017/IntelFsp2Pkg/Include/FspEas/FspApi.h 3 files changed, 67 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/59744/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59744 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If12b63a282c660da6f57fe23b0b848e2d155853f Gerrit-Change-Number: 59744 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: drivers/intel/fsp2_0: Add support for FSP runs in long mode (x86_64)
by Subrata Banik (Code Review) 30 Nov '21

30 Nov '21

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59744 ) Change subject: drivers/intel/fsp2_0: Add support for FSP runs in long mode (x86_64) ...................................................................... drivers/intel/fsp2_0: Add support for FSP runs in long mode (x86_64) Add new Kconfig `PLATFORM_USES_FSP2_X86_64` to mark FSP binarycapable of running in x86_64 mode. Fix the compilation issue by addingrequired FSP headers to make the code compiled with`HAVE_EXP_X86_64_SUPPORT` Kconfig enabled. TEST=Verified on Intel Alder Lake with experimental 64-bit support FSP.h Change-Id: If12b63a282c660da6f57fe23b0b848e2d155853f Signed-off-by: Subrata Banik <subi.banik(a)gmail.com> --- M src/drivers/intel/fsp2_0/Kconfig M src/drivers/intel/fsp2_0/include/fsp/info_header.h M src/vendorcode/intel/edk2/UDK2017/IntelFsp2Pkg/Include/FspEas/FspApi.h 3 files changed, 67 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/59744/1 diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig index a0e02a8..58da9b4 100644 --- a/src/drivers/intel/fsp2_0/Kconfig +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -33,10 +33,18 @@ config PLATFORM_USES_FSP2_X86_32 bool - default y + default y if !HAVE_EXP_X86_64_SUPPORT + default n help The FSP 2.0 runs in x86_32 protected mode. - Once there's a x86_64 FSP this needs to default to n. + +config PLATFORM_USES_FSP2_X86_64 + bool + depends on HAVE_EXP_X86_64_SUPPORT + default y if HAVE_EXP_X86_64_SUPPORT + default n + help + Select when FSP 2.0 runs in x86_64 long mode. config HAVE_INTEL_FSP_REPO bool diff --git a/src/drivers/intel/fsp2_0/include/fsp/info_header.h b/src/drivers/intel/fsp2_0/include/fsp/info_header.h index 5b6318c..23b48ff 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/info_header.h +++ b/src/drivers/intel/fsp2_0/include/fsp/info_header.h @@ -31,7 +31,24 @@ uint8_t revision; } __packed; #else -#error You need to implement this struct for x86_64 FSP +struct fsp_header { + uint32_t fsp_revision; + uint64_t image_size; + uint64_t image_base; + uint16_t image_attribute; + uint8_t spec_version; + uint16_t component_attribute; + uint64_t cfg_region_offset; + uint64_t cfg_region_size; + uint64_t temp_ram_init_entry; + uint64_t temp_ram_exit_entry; + uint64_t notify_phase_entry_offset; + uint64_t memory_init_entry_offset; + uint64_t silicon_init_entry_offset; + uint64_t multi_phase_si_init_entry_offset; + char image_id[sizeof(uint64_t) + 1]; + uint8_t revision; +} __packed; #endif diff --git a/src/vendorcode/intel/edk2/UDK2017/IntelFsp2Pkg/Include/FspEas/FspApi.h b/src/vendorcode/intel/edk2/UDK2017/IntelFsp2Pkg/Include/FspEas/FspApi.h index c22b701..4146369 100644 --- a/src/vendorcode/intel/edk2/UDK2017/IntelFsp2Pkg/Include/FspEas/FspApi.h +++ b/src/vendorcode/intel/edk2/UDK2017/IntelFsp2Pkg/Include/FspEas/FspApi.h @@ -91,7 +91,45 @@ UINT8 Reserved1[8]; } FSPM_ARCH_UPD; #else -#error You need to implement this struct for x86_64 FSP +// +/// FSPM_ARCH_UPD Configuration. +/// +typedef struct { + /// + /// Revision of the structure. For FSP v2.0 value is 1. + /// + UINT8 Revision; + UINT8 Reserved[3]; + /// + /// Pointer to the non-volatile storage (NVS) data buffer. + /// If it is NULL it indicates the NVS data is not available. + /// + /// Note: This ought to be VOID*, but that won't allow calling this binary on x86_64. + /// + UINT64 NvsBufferPtr; + /// + /// Pointer to the temporary stack base address to be + /// consumed inside FspMemoryInit() API. + /// + /// Note: This ought to be VOID*, but that won't allow calling this binary on x86_64. + /// + UINT64 StackBase; + /// + /// Temporary stack size to be consumed inside + /// FspMemoryInit() API. + /// + UINT32 StackSize; + /// + /// Size of memory to be reserved by FSP below "top + /// of low usable memory" for bootloader usage. + /// + UINT32 BootLoaderTolumSize; + /// + /// Current boot mode. + /// + UINT32 BootMode; + UINT8 Reserved1[8]; +} FSPM_ARCH_UPD; #endif /// -- To view, visit https://review.coreboot.org/c/coreboot/+/59744 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If12b63a282c660da6f57fe23b0b848e2d155853f Gerrit-Change-Number: 59744 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subi.banik(a)gmail.com> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: soc/mediatek: Add PCIe support
by Jianjun Wang (Code Review) 30 Nov '21

30 Nov '21

Attention is currently required from: Shelley Chen, Hung-Te Lin, Furquan Shaikh, Paul Menzel, Yu-Ping Wu. Jianjun Wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56791 ) Change subject: soc/mediatek: Add PCIe support ...................................................................... Patch Set 5: (2 comments) File src/soc/mediatek/common/pcie.c: https://review.coreboot.org/c/coreboot/+/56791/comment/32324deb_b173de57 PS4, Line 194: - 1 > There's already "(size) - 1" in PCIE_ATR_SIZE(). Please confirm if this extra "- 1" is needed. Yes, the extra "-1" is needed. fls(size) will get a value with one more bit offset, we need to get the actually value here. And the value we write to the ATR_SIZE still need to be subtracted by one base on the hardware design. Here is the example: If we need to assign a table to 16MBytes size, the res->size will be 0x100_0000, and fls(res->size) = 25, but the actual bit offset should be 24. After all these operations, we write the value 23 into the ATR_SIZE register. Base on the hardware design, the table size will be 2^(ATR_SIZE +1) = 2^(23 + 1)= 0x100_0000 https://review.coreboot.org/c/coreboot/+/56791/comment/3c4c3e47_085a8df2 PS4, Line 216: if (!res->size) : continue; > When will this happen? I found some resource size will be 0, such as the resource which index is PCI_IO_BASE or PCI_MEMORY_BASE, I'm not sure if there is something incorrect, so I added this check to prevent break their resource size. -- To view, visit https://review.coreboot.org/c/coreboot/+/56791 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib9b6adaafa20aeee136372ec9564273f86776da0 Gerrit-Change-Number: 56791 Gerrit-PatchSet: 5 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Tue, 30 Nov 2021 07:13:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: amdfwtool: remove duplicates
by Kangheui Won (Code Review) 30 Nov '21

30 Nov '21

Attention is currently required from: Bao Zheng, Felix Held. Kangheui Won has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59581 ) Change subject: amdfwtool: remove duplicates ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/59581/comment/a813ce1d_f5614a69 PS1, Line 12: TEST=build guybrush and confirm amdfw and coreboot.rom are identical > this needs to be tested on picasso and stoneyridge where it might make a difference. the cezanne fw. […] I don't think smu firmware makes any difference here since only duplicate entries are removed. (e.g. line 235 and line 271 in amdfwtool.c) For picasso I checked amdfw.rom is identical with this whole CL chain. However on stoney it's a bit different because AMD_FW_PSP_TRUSTLETS and AMD_FW_PSP_SECURED_DEBUG, there are both code to check command line config and not to check (see line 135 and line 207 in data_parse.c) and code not checking comes before in if-else block so they were added unconditionally. On picasso and cezanne we set unlock_secure and use_secureos so they are added anyway but on grunt we don't set those flags so it's now removed. I confirmed that if I add AMD_FW_PSP_TRUSTLETS and AMD_FW_PSP_SECURED_DEBUG files unconditionally amdfw.rom is identical. I don't know any history why this work like this but do you think we should add them on stoney? -- To view, visit https://review.coreboot.org/c/coreboot/+/59581 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3b86e24ba1c2769985e2864528e4dfcbf3cccc4b Gerrit-Change-Number: 59581 Gerrit-PatchSet: 1 Gerrit-Owner: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Bao Zheng <zheng.bao(a)amd.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Bao Zheng <zheng.bao(a)amd.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 30 Nov 2021 06:28:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/mediatek: Add PCIe support
by Yu-Ping Wu (Code Review) 30 Nov '21

30 Nov '21

Attention is currently required from: Shelley Chen, Hung-Te Lin, Furquan Shaikh, Paul Menzel, Jianjun Wang. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56791 ) Change subject: soc/mediatek: Add PCIe support ...................................................................... Patch Set 5: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/56791/comment/02fa8b4e_6f16ce41 PS3, Line 11: > > Since this file is not platform related, I'm not sure if this is a good idea to add this comment i […] Ack File src/soc/mediatek/common/pcie.c: https://review.coreboot.org/c/coreboot/+/56791/comment/84e1aad3_0504b512 PS3, Line 85: static inline int mtk_fls(int x) > Maybe commonlib/bsd/include/commonlib/bsd/helpers. […] Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/56791 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib9b6adaafa20aeee136372ec9564273f86776da0 Gerrit-Change-Number: 56791 Gerrit-PatchSet: 5 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Comment-Date: Tue, 30 Nov 2021 06:25:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Comment-In-Reply-To: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/mediatek: Add PCIe support
by Yu-Ping Wu (Code Review) 30 Nov '21

30 Nov '21

Attention is currently required from: Shelley Chen, Hung-Te Lin, Furquan Shaikh, Paul Menzel, Jianjun Wang. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56791 ) Change subject: soc/mediatek: Add PCIe support ...................................................................... Patch Set 5: (4 comments) File src/soc/mediatek/common/pcie.c: https://review.coreboot.org/c/coreboot/+/56791/comment/4948fed2_3c4be429 PS4, Line 116: i > size_t for i Ack https://review.coreboot.org/c/coreboot/+/56791/comment/e844de87_c7a94930 PS4, Line 200: printk(BIOS_INFO, "%s: set %s trans window[%d]: cpu_addr = %#llx, pci_addr = %#llx, size = %#llx\n", > Yes, it’s allowed by the coding style, and line length limit does not apply. […] Ack https://review.coreboot.org/c/coreboot/+/56791/comment/5dab2aa3_38724678 PS4, Line 202: (unsigned long long) > Why do we need to cast it? Can't we just print with %#x? Ack https://review.coreboot.org/c/coreboot/+/56791/comment/caf1fd27_b339a7cd PS4, Line 326: (struct bus *) > No need to cast. Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/56791 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib9b6adaafa20aeee136372ec9564273f86776da0 Gerrit-Change-Number: 56791 Gerrit-PatchSet: 5 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Comment-Date: Tue, 30 Nov 2021 06:24:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Comment-In-Reply-To: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: helpers: Add fls support
by Jianjun Wang (Code Review) 30 Nov '21

30 Nov '21

Jianjun Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59738 ) Change subject: helpers: Add fls support ...................................................................... helpers: Add fls support Introduce the C-language equivalent function of fls: find last (most-significant) bit set. Since x86 has its specific function, only used in non-x86 platform, and remove the duplicate definitions in commonlib/storage/sdhci.c. This code is copied from Linux kernel in: include/asm-generic/bitops/fls.h Signed-off-by: Jianjun Wang <jianjun.wang(a)mediatek.com> Change-Id: Ib458abfec7e03b2979569a8440a6e69b0285ac32 --- M src/commonlib/bsd/include/commonlib/bsd/helpers.h M src/commonlib/storage/sdhci.c 2 files changed, 38 insertions(+), 30 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/59738/1 diff --git a/src/commonlib/bsd/include/commonlib/bsd/helpers.h b/src/commonlib/bsd/include/commonlib/bsd/helpers.h index 733b05a..80a1790 100644 --- a/src/commonlib/bsd/include/commonlib/bsd/helpers.h +++ b/src/commonlib/bsd/include/commonlib/bsd/helpers.h @@ -126,4 +126,42 @@ #define retry(attempts, condition, ...) \ _retry_impl(attempts, condition, __VA_ARGS__) +#ifndef ARCH_X86 +/** + * fls - find last (most-significant) bit set + * @x: the word to search + * + * This is defined the same way as ffs. + * Note fls(0) = 0, fls(1) = 1, fls(0x80000000) = 32. + */ +static __always_inline int fls(unsigned int x) +{ + int r = 32; + + if (!x) + return 0; + if (!(x & 0xffff0000u)) { + x <<= 16; + r -= 16; + } + if (!(x & 0xff000000u)) { + x <<= 8; + r -= 8; + } + if (!(x & 0xf0000000u)) { + x <<= 4; + r -= 4; + } + if (!(x & 0xc0000000u)) { + x <<= 2; + r -= 2; + } + if (!(x & 0x80000000u)) { + x <<= 1; + r -= 1; + } + return r; +} +#endif + #endif /* COMMONLIB_BSD_HELPERS_H */ diff --git a/src/commonlib/storage/sdhci.c b/src/commonlib/storage/sdhci.c index 6d39a45..0dcc66e 100644 --- a/src/commonlib/storage/sdhci.c +++ b/src/commonlib/storage/sdhci.c @@ -411,36 +411,6 @@ return 0; } -/* Find leftmost set bit in a 32 bit integer */ -static int fls(u32 x) -{ - int r = 32; - - if (!x) - return 0; - if (!(x & 0xffff0000u)) { - x <<= 16; - r -= 16; - } - if (!(x & 0xff000000u)) { - x <<= 8; - r -= 8; - } - if (!(x & 0xf0000000u)) { - x <<= 4; - r -= 4; - } - if (!(x & 0xc0000000u)) { - x <<= 2; - r -= 2; - } - if (!(x & 0x80000000u)) { - x <<= 1; - r -= 1; - } - return r; -} - static void sdhci_set_power(struct sdhci_ctrlr *sdhci_ctrlr, unsigned short power) { -- To view, visit https://review.coreboot.org/c/coreboot/+/59738 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib458abfec7e03b2979569a8440a6e69b0285ac32 Gerrit-Change-Number: 59738 Gerrit-PatchSet: 1 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: soc/mediatek: Enable PCIe support for mt8195
by Jianjun Wang (Code Review) 30 Nov '21

30 Nov '21

Attention is currently required from: Hung-Te Lin. Hello Hung-Te Lin, build bot (Jenkins), Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56793 to look at the new patch set (#5). Change subject: soc/mediatek: Enable PCIe support for mt8195 ...................................................................... soc/mediatek: Enable PCIe support for mt8195 Enable PCIe support for mt8195. Signed-off-by: Jianjun Wang <jianjun.wang(a)mediatek.com> Change-Id: I314572955f1021abe9f2f0f4635670135ed08fff --- M src/soc/mediatek/mt8195/Kconfig M src/soc/mediatek/mt8195/Makefile.inc M src/soc/mediatek/mt8195/pcie.c M src/soc/mediatek/mt8195/soc.c 4 files changed, 6 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/56793/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/56793 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I314572955f1021abe9f2f0f4635670135ed08fff Gerrit-Change-Number: 56793 Gerrit-PatchSet: 5 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: soc/mediatek: Add PCIe support
by Jianjun Wang (Code Review) 30 Nov '21

30 Nov '21

Attention is currently required from: Shelley Chen, Hung-Te Lin, Furquan Shaikh, Yu-Ping Wu, Jianjun Wang. Hello Shelley Chen, Hung-Te Lin, build bot (Jenkins), Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56791 to look at the new patch set (#5). Change subject: soc/mediatek: Add PCIe support ...................................................................... soc/mediatek: Add PCIe support Add PCIe support for MediaTek platform. Reference: - MT8195 Register Map V0.3-2, Chapter 3.18 PCIe controller (Page 1250) - linux/drivers/pci/controller/pcie-mediatek-gen3.c This code is based on MT8195 platform, but it should be common in each platform with the same PCIe IP in the future. TEST=Build pass and boot up to kernel successfully via SSD BUG=b:178565024 Signed-off-by: Jianjun Wang <jianjun.wang(a)mediatek.com> Change-Id: Ib9b6adaafa20aeee136372ec9564273f86776da0 --- A src/soc/mediatek/common/include/soc/pcie_common.h A src/soc/mediatek/common/pcie.c 2 files changed, 335 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/56791/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/56791 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib9b6adaafa20aeee136372ec9564273f86776da0 Gerrit-Change-Number: 56791 Gerrit-PatchSet: 5 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: mb/google/brya/variants/primus: Swap TPM I2C with touchscreen I2C
by Malik Hsu (Code Review) 30 Nov '21

30 Nov '21

Malik Hsu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59737 ) Change subject: mb/google/brya/variants/primus: Swap TPM I2C with touchscreen I2C ...................................................................... mb/google/brya/variants/primus: Swap TPM I2C with touchscreen I2C In next build phase, primus will exchange i2c port for touchscreen and cr50. BUG=b:207834727 TEST=build pass Signed-off-by: Malik_Hsu <malik_hsu(a)wistron.corp-partner.google.com> Change-Id: Ief1b156b866a9aaa2919f0e209b6439c7019e939 --- M src/mainboard/google/brya/Kconfig M src/mainboard/google/brya/variants/primus/gpio.c M src/mainboard/google/brya/variants/primus/overridetree.cb 3 files changed, 22 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/59737/1 diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index 6231762..7c7f808 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -74,7 +74,7 @@ hex default 0x3 if BOARD_GOOGLE_BRYA0 default 0x3 if BOARD_GOOGLE_BRASK - default 0x3 if BOARD_GOOGLE_PRIMUS + default 0x1 if BOARD_GOOGLE_PRIMUS default 0x3 if BOARD_GOOGLE_GIMBLE default 0x3 if BOARD_GOOGLE_REDRIX default 0x1 if BOARD_GOOGLE_KANO diff --git a/src/mainboard/google/brya/variants/primus/gpio.c b/src/mainboard/google/brya/variants/primus/gpio.c index df0930c..0ec9b87 100644 --- a/src/mainboard/google/brya/variants/primus/gpio.c +++ b/src/mainboard/google/brya/variants/primus/gpio.c @@ -80,10 +80,10 @@ PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), /* B4 : PROC_GP3 ==> SSD_PERST_L */ PAD_CFG_GPO(GPP_B4, 0, DEEP), - /* B7 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */ - PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2), - /* B8 : ISH_12C1_SCL ==> PCH_I2C_TPM_SCL */ - PAD_CFG_NF(GPP_B8, NONE, DEEP, NF2), + /* H6 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */ + PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), + /* H7 : ISH_12C1_SCL ==> PCH_I2C_TPM_SCL */ + PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), /* * D1 : ISH_GP1 ==> FP_RST_ODL * FP_RST_ODL comes out of reset as hi-z and does not have an external pull-down. diff --git a/src/mainboard/google/brya/variants/primus/overridetree.cb b/src/mainboard/google/brya/variants/primus/overridetree.cb index c12939f..8424319 100644 --- a/src/mainboard/google/brya/variants/primus/overridetree.cb +++ b/src/mainboard/google/brya/variants/primus/overridetree.cb @@ -42,11 +42,11 @@ #+-------------------+---------------------------+ #| GSPI1 | Fingerprint MCU | #| I2C0 | Audio | - #| I2C1 | Touchscreen | - #| I2C2 | | - #| I2C3 | cr50 TPM. Early init is | + #| I2C1 | cr50 TPM. Early init is | #| | required to set up a BAR | #| | for TPM communication | + #| I2C2 | | + #| I2C3 | Touchscreen | #| I2C5 | Trackpad | #+-------------------+---------------------------+ register "common_soc_config" = "{ @@ -54,14 +54,20 @@ .speed = I2C_SPEED_FAST, }, .i2c[1] = { + .early_init = 1, .speed = I2C_SPEED_FAST, + .rise_time_ns = 600, + .fall_time_ns = 400, + .data_hold_time_ns = 50, }, .i2c[2] = { .speed = I2C_SPEED_FAST, }, .i2c[3] = { - .early_init = 1, .speed = I2C_SPEED_FAST, + .rise_time_ns = 650, + .fall_time_ns = 400, + .data_hold_time_ns = 50, }, .i2c[5] = { .speed = I2C_SPEED_FAST, @@ -197,6 +203,13 @@ end end #I2C0 device ref i2c1 on + chip drivers/i2c/tpm + register "hid" = ""GOOG0005"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A13_IRQ)" + device i2c 50 on end + end + end + device ref i2c3 on chip drivers/i2c/hid register "generic.hid" = ""ELAN9050"" register "generic.desc" = ""ELAN Touchscreen"" @@ -232,13 +245,6 @@ device i2c 0x40 on end end end - device ref i2c3 on - chip drivers/i2c/tpm - register "hid" = ""GOOG0005"" - register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A13_IRQ)" - device i2c 50 on end - end - end device ref i2c5 on chip drivers/i2c/generic register "hid" = ""ELAN0000"" -- To view, visit https://review.coreboot.org/c/coreboot/+/59737 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ief1b156b866a9aaa2919f0e209b6439c7019e939 Gerrit-Change-Number: 59737 Gerrit-PatchSet: 1 Gerrit-Owner: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-MessageType: newchange

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit November 2021