coreboot-gerrit November 2021

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Change in coreboot[master]: soc/intel/common Add support for CSE IOM/NPHY sub-parition update
by Sridhar Siricilla (Code Review) 29 Nov '21

29 Nov '21

Attention is currently required from: Marx Wang, Tim Wawrzynczak, Rizwan Qureshi, Sridhar Siricilla, Balaji Manigandan, Nick Vaccaro, Patrick Rudolph. Sridhar Siricilla has uploaded a new patch set (#11) to the change originally created by Krishna P Bhat D. ( https://review.coreboot.org/c/coreboot/+/59685 ) Change subject: soc/intel/common Add support for CSE IOM/NPHY sub-parition update ...................................................................... soc/intel/common Add support for CSE IOM/NPHY sub-parition update This patch adds the following support to coreboot 1. Kconfig to add IOM/NPHY in the COREBOOT/FW_MAIN_A/FW_MAIN_B partition of BIOS 2. Helper functions to support update. Pre-requisites to enable IOM/NPHY FW Update: 1.NPHY and IOM blobs have to be added to added COREBOOT, FW_MAIN_A and FW_MAIN_B through board configuration files. CONFIG_SOC_INTEL_CSE_IOM_CBFS_FILE: IOM blob Path SOC_INTEL_CSE_NPHY_CBFS_FILE: NPHY blob path 2.Enable CONFIG_CSE_SUB_PARTITION_UPDATE to enable CSE sub-partition NPHY/IOM update. coreboot follows below procedure to update NPHY and IOM: NPHY Update: 1.coreboot will navigate through the CSE region, identify the CSE’s NPHY FW version and BIOS NPHY version. 2.Compare both versions, if there is a difference, CSE will trigger an NPHY FW update. Otherwise, skips the NPHY FW update. IOM Update: 1.coreboot will navigate through the CSE region, identify CSE's IOM FW version and BIOS IOM version. 2.Compares both versions, if there is a difference, coreboot will trigger an IOM FW update.Otherwise, skip IOM FW update. Before coreboot triggers update of NPHY/IOM, BIOS sends SET BOOT PARTITION INFO(RO) to CSE and issues GLOBAL RESET commands if CSE boots from RW. coreboot updates CSE's NPHY and IOM sub-partition only if CSE boots from CSE RO Boot partition. Once CSE boots from RO, BIOS sends HMRFPO command to CSE, then triggers update of NPHY and IOM FW in the CSE Region(RO and RW). coreboot triggers NPHY/IOM update procedure in all ChromeOS boot modes(Normal and Recovery). BUG=b:202143532 BRANCH=None TEST=Build and verify CSE sub-partitions IOM and NPHY are getting updated with CBFS IOM and NPHY blobs. Change-Id: I7c0cda51314c4f722f5432486a43e19b46f4b240 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d(a)intel.com> --- M src/soc/intel/alderlake/romstage/romstage.c M src/soc/intel/common/block/cse/Kconfig M src/soc/intel/common/block/cse/Makefile.inc M src/soc/intel/common/block/cse/cse_lite.c M src/soc/intel/common/block/include/intelblocks/cse.h A src/soc/intel/common/block/include/intelblocks/cse_layout.h 6 files changed, 507 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/59685/11 -- To view, visit https://review.coreboot.org/c/coreboot/+/59685 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7c0cda51314c4f722f5432486a43e19b46f4b240 Gerrit-Change-Number: 59685 Gerrit-PatchSet: 11 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Marx Wang <marx.wang(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Marx Wang <marx.wang(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/amd/common/block/include/lpc: add missing LPC_PCI_CONTROL bit defs
by Raul Rangel (Code Review) 29 Nov '21

29 Nov '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59674 ) Change subject: soc/amd/common/block/include/lpc: add missing LPC_PCI_CONTROL bit defs ...................................................................... Patch Set 1: Code-Review+2 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/59674/comment/dac1b94d_eb571263 PS1, Line 10: LPC_PCI_CONTROL > i'm not really planning to use those, but those might be needed for the !DISABLE_SPI_FLASH_ROM_SHARI […] Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/59674 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I855e640d020daf21c9f5b2f62a2ad0fd0274a575 Gerrit-Change-Number: 59674 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 29 Nov 2021 21:03:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/cezanne: add missing PM_ACPI_* bit definitions
by Raul Rangel (Code Review) 29 Nov '21

29 Nov '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59588 ) Change subject: soc/amd/cezanne: add missing PM_ACPI_* bit definitions ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59588 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icd128dca1ec30e7c70501c0e64482159be71cc7b Gerrit-Change-Number: 59588 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 29 Nov 2021 21:02:54 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: intel: cse_lite: Use cbfs_unverified_area API
by Tim Wawrzynczak (Code Review) 29 Nov '21

29 Nov '21

Attention is currently required from: Raul Rangel, Julius Werner, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59679 ) Change subject: intel: cse_lite: Use cbfs_unverified_area API ...................................................................... Patch Set 2: (1 comment) File src/soc/intel/common/block/cse/cse_lite.c: https://review.coreboot.org/c/coreboot/+/59679/comment/d316a947_b9a55597 PS2, Line 676: cbfs_unverified_area_map > Just curious, is the FW compressed in CBFS? If it's not, could we switch to using a raw FMAP region […] We are planning on doing that for some upcoming platforms because of SPI flash size, but currently it was uncompressed because it's already ~10s to do the update, and this is pre-graphics so we didn't want the extra hit of decompression time. -- To view, visit https://review.coreboot.org/c/coreboot/+/59679 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If4855280d6d06cf1aa646fded916fd830b287b30 Gerrit-Change-Number: 59679 Gerrit-PatchSet: 2 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 29 Nov 2021 20:56:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/kano: Enable USB2 port 9 for BlueTooth
by Tim Wawrzynczak (Code Review) 29 Nov '21

29 Nov '21

Attention is currently required from: David Wu, Nick Vaccaro. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59658 ) Change subject: mb/google/brya/var/kano: Enable USB2 port 9 for BlueTooth ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59658 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7971509d7428562c80e781339ead059a189cea13 Gerrit-Change-Number: 59658 Gerrit-PatchSet: 1 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Mon, 29 Nov 2021 20:52:01 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/common/block/include/lpc: add missing LPC_PCI_CONTROL bit defs
by Felix Held (Code Review) 29 Nov '21

29 Nov '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59674 ) Change subject: soc/amd/common/block/include/lpc: add missing LPC_PCI_CONTROL bit defs ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/59674/comment/a3743208_5e801e93 PS1, Line 10: LPC_PCI_CONTROL > Do we actually need to define these bits? Is anyone going to use them? i'm not really planning to use those, but those might be needed for the !DISABLE_SPI_FLASH_ROM_SHARING case, so i'd say that it's a good idea to at least add those definitions -- To view, visit https://review.coreboot.org/c/coreboot/+/59674 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I855e640d020daf21c9f5b2f62a2ad0fd0274a575 Gerrit-Change-Number: 59674 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Comment-Date: Mon, 29 Nov 2021 20:52:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: brya: add various ES variants
by YH Lin (Code Review) 29 Nov '21

29 Nov '21

Attention is currently required from: Nick Vaccaro, Zhuohao Lee. Hello build bot (Jenkins), Tim Wawrzynczak, Nick Vaccaro, Zhuohao Lee, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59728 to look at the new patch set (#3). Change subject: brya: add various ES variants ...................................................................... brya: add various ES variants Fork multiple "4ES" variants off some brya devices to properly support ES SoC. BRANCH=none BUG=b:201767461 TEST=emerge-brya coreboot and check the artifacts Signed-off-by: YH Lin <yueherngl(a)google.com> Change-Id: Ic9516fec591429238bde1478eca2522d8ed10127 --- M src/mainboard/google/brya/Kconfig M src/mainboard/google/brya/Kconfig.name A src/mainboard/google/brya/variants/anahera4es/Makefile.inc A src/mainboard/google/brya/variants/anahera4es/fw_config.c A src/mainboard/google/brya/variants/anahera4es/gpio.c A src/mainboard/google/brya/variants/anahera4es/include/variant/ec.h A src/mainboard/google/brya/variants/anahera4es/include/variant/gpio.h A src/mainboard/google/brya/variants/anahera4es/memory/Makefile.inc A src/mainboard/google/brya/variants/anahera4es/memory/dram_id.generated.txt A src/mainboard/google/brya/variants/anahera4es/memory/mem_parts_used.txt A src/mainboard/google/brya/variants/anahera4es/overridetree.cb A src/mainboard/google/brya/variants/brya4es/Makefile.inc A src/mainboard/google/brya/variants/brya4es/fw_config.c A src/mainboard/google/brya/variants/brya4es/gpio.c A src/mainboard/google/brya/variants/brya4es/include/variant/ec.h A src/mainboard/google/brya/variants/brya4es/include/variant/gpio.h A src/mainboard/google/brya/variants/brya4es/memory/Makefile.inc A src/mainboard/google/brya/variants/brya4es/memory/dram_id.generated.txt A src/mainboard/google/brya/variants/brya4es/memory/mem_parts_used.txt A src/mainboard/google/brya/variants/brya4es/overridetree.cb A src/mainboard/google/brya/variants/brya4es/ramstage.c A src/mainboard/google/brya/variants/brya4es/variant.c A src/mainboard/google/brya/variants/gimble4es/Makefile.inc A src/mainboard/google/brya/variants/gimble4es/fw_config.c A src/mainboard/google/brya/variants/gimble4es/gpio.c A src/mainboard/google/brya/variants/gimble4es/include/variant/ec.h A src/mainboard/google/brya/variants/gimble4es/include/variant/gpio.h A src/mainboard/google/brya/variants/gimble4es/memory/Makefile.inc A src/mainboard/google/brya/variants/gimble4es/memory/dram_id.generated.txt A src/mainboard/google/brya/variants/gimble4es/memory/mem_parts_used.txt A src/mainboard/google/brya/variants/gimble4es/overridetree.cb A src/mainboard/google/brya/variants/gimble4es/variant.c A src/mainboard/google/brya/variants/primus4es/Makefile.inc A src/mainboard/google/brya/variants/primus4es/fw_config.c A src/mainboard/google/brya/variants/primus4es/gpio.c A src/mainboard/google/brya/variants/primus4es/include/variant/ec.h A src/mainboard/google/brya/variants/primus4es/include/variant/gpio.h A src/mainboard/google/brya/variants/primus4es/memory/Makefile.inc A src/mainboard/google/brya/variants/primus4es/memory/dram_id.generated.txt A src/mainboard/google/brya/variants/primus4es/memory/mem_parts_used.txt A src/mainboard/google/brya/variants/primus4es/overridetree.cb A src/mainboard/google/brya/variants/primus4es/variant.c A src/mainboard/google/brya/variants/redrix4es/Makefile.inc A src/mainboard/google/brya/variants/redrix4es/fw_config.c A src/mainboard/google/brya/variants/redrix4es/gpio.c A src/mainboard/google/brya/variants/redrix4es/include/variant/ec.h A src/mainboard/google/brya/variants/redrix4es/include/variant/gpio.h A src/mainboard/google/brya/variants/redrix4es/memory/Makefile.inc A src/mainboard/google/brya/variants/redrix4es/memory/dram_id.generated.txt A src/mainboard/google/brya/variants/redrix4es/memory/mem_parts_used.txt A src/mainboard/google/brya/variants/redrix4es/overridetree.cb A src/mainboard/google/brya/variants/redrix4es/variant.c A src/mainboard/google/brya/variants/taeko4es/Makefile.inc A src/mainboard/google/brya/variants/taeko4es/fw_config.c A src/mainboard/google/brya/variants/taeko4es/gpio.c A src/mainboard/google/brya/variants/taeko4es/include/variant/ec.h A src/mainboard/google/brya/variants/taeko4es/include/variant/gpio.h A src/mainboard/google/brya/variants/taeko4es/memory.c A src/mainboard/google/brya/variants/taeko4es/memory/Makefile.inc A src/mainboard/google/brya/variants/taeko4es/memory/dram_id.generated.txt A src/mainboard/google/brya/variants/taeko4es/memory/mem_parts_used.txt A src/mainboard/google/brya/variants/taeko4es/overridetree.cb 62 files changed, 4,936 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/59728/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/59728 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic9516fec591429238bde1478eca2522d8ed10127 Gerrit-Change-Number: 59728 Gerrit-PatchSet: 3 Gerrit-Owner: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/amd/common/block/lpc: use 32 bit accesses in lpc_enable_port80
by Felix Held (Code Review) 29 Nov '21

29 Nov '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59676 ) Change subject: soc/amd/common/block/lpc: use 32 bit accesses in lpc_enable_port80 ...................................................................... soc/amd/common/block/lpc: use 32 bit accesses in lpc_enable_port80 When using 32 bit PCI accesses in lpc_enable_port80, we can use the LPC_IO_OR_MEM_DECODE_ENABLE and DECODE_IO_PORT_ENABLE4 defines and don't need to re-define bits with offsets from the beginning of the third byte within this 32 bit register. This allows to drop the LPC_IO_OR_MEM_DEC_EN_HIGH register definition which points to LPC_IO_OR_MEM_DECODE_ENABLE + 2 and to drop the re-definitions of the bit re-definitions with a different offset. The code in lpc_enable_port80 was originally copied from sb/amd/agesa/ hudson/early_setup.c which might be sort-of a copy from what the AGESA reference code does. TEST=When commenting out SOC_AMD_COMMON_BLOCK_USE_ESPI in the Kconfig of Mandolin and selecting AMD_LPC_DEBUG_CARD, all POST codes still get shown on the POST code LED display when this patch is applied. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I001bb1c2ccf99e36d4fbd73d3bf96b78ddb87d67 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59676 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> --- M src/soc/amd/common/block/include/amdblocks/lpc.h M src/soc/amd/common/block/lpc/lpc_util.c 2 files changed, 4 insertions(+), 16 deletions(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved diff --git a/src/soc/amd/common/block/include/amdblocks/lpc.h b/src/soc/amd/common/block/include/amdblocks/lpc.h index 024d479..c5f3c78 100644 --- a/src/soc/amd/common/block/include/amdblocks/lpc.h +++ b/src/soc/amd/common/block/include/amdblocks/lpc.h @@ -67,18 +67,6 @@ #define LPC_SELECT_SIO_2E2F 0 #define WIDEIO_RANGE_ERROR -1 -/* Assuming word access to higher word (register 0x4a) */ -#define LPC_IO_OR_MEM_DEC_EN_HIGH 0x4a -#define LPC_WIDEIO2_ENABLE_H BIT(9) -#define LPC_WIDEIO1_ENABLE_H BIT(8) -#define DECODE_IO_PORT_ENABLE6_H BIT(7) -#define DECODE_IO_PORT_ENABLE5_H BIT(6) -#define DECODE_IO_PORT_ENABLE4_H BIT(5) -#define DECODE_IO_PORT_ENABLE3_H BIT(3) -#define DECODE_IO_PORT_ENABLE2_H BIT(2) -#define DECODE_IO_PORT_ENABLE1_H BIT(1) -#define DECODE_IO_PORT_ENABLE0_H BIT(0) - #define LPC_MEM_PORT1 0x4c #define ROM_PROTECT_RANGE0 0x50 #define ROM_BASE_MASK 0xfffff000 /* bits 31-12 */ diff --git a/src/soc/amd/common/block/lpc/lpc_util.c b/src/soc/amd/common/block/lpc/lpc_util.c index c40a198..7291959 100644 --- a/src/soc/amd/common/block/lpc/lpc_util.c +++ b/src/soc/amd/common/block/lpc/lpc_util.c @@ -138,11 +138,11 @@ void lpc_enable_port80(void) { - u8 byte; + uint32_t tmp; - byte = pci_read_config8(_LPCB_DEV, LPC_IO_OR_MEM_DEC_EN_HIGH); - byte |= DECODE_IO_PORT_ENABLE4_H; - pci_write_config8(_LPCB_DEV, LPC_IO_OR_MEM_DEC_EN_HIGH, byte); + tmp = pci_read_config32(_LPCB_DEV, LPC_IO_OR_MEM_DECODE_ENABLE); + tmp |= DECODE_IO_PORT_ENABLE4; + pci_write_config32(_LPCB_DEV, LPC_IO_OR_MEM_DECODE_ENABLE, tmp); } void lpc_enable_sio_decode(const bool addr) -- To view, visit https://review.coreboot.org/c/coreboot/+/59676 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I001bb1c2ccf99e36d4fbd73d3bf96b78ddb87d67 Gerrit-Change-Number: 59676 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/common/block/lpc/lpc_util: drop lpc_enable_pci_port80
by Felix Held (Code Review) 29 Nov '21

29 Nov '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59675 ) Change subject: soc/amd/common/block/lpc/lpc_util: drop lpc_enable_pci_port80 ...................................................................... soc/amd/common/block/lpc/lpc_util: drop lpc_enable_pci_port80 This function is unused and none of the SoCs using this code has a physical PCI interface any more, so drop this function. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ia5c5a8ec29264a075fefe75038ef2a84684d6427 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59675 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> --- M src/soc/amd/common/block/include/amdblocks/lpc.h M src/soc/amd/common/block/lpc/lpc_util.c 2 files changed, 0 insertions(+), 10 deletions(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved diff --git a/src/soc/amd/common/block/include/amdblocks/lpc.h b/src/soc/amd/common/block/include/amdblocks/lpc.h index 09eafb8..024d479 100644 --- a/src/soc/amd/common/block/include/amdblocks/lpc.h +++ b/src/soc/amd/common/block/include/amdblocks/lpc.h @@ -142,7 +142,6 @@ * with the enable bits. */ void lpc_disable_decodes(void); void lpc_enable_port80(void); -void lpc_enable_pci_port80(void); void lpc_enable_decode(uint32_t decodes); /* addr = index/data to enable: LPC_SELECT_SIO_2E2F or LPC_SELECT_SIO_4E4F */ void lpc_enable_sio_decode(const bool addr); diff --git a/src/soc/amd/common/block/lpc/lpc_util.c b/src/soc/amd/common/block/lpc/lpc_util.c index fb231dd..c40a198 100644 --- a/src/soc/amd/common/block/lpc/lpc_util.c +++ b/src/soc/amd/common/block/lpc/lpc_util.c @@ -145,15 +145,6 @@ pci_write_config8(_LPCB_DEV, LPC_IO_OR_MEM_DEC_EN_HIGH, byte); } -void lpc_enable_pci_port80(void) -{ - u8 byte; - - byte = pci_read_config8(_LPCB_DEV, LPC_IO_OR_MEM_DEC_EN_HIGH); - byte &= ~DECODE_IO_PORT_ENABLE4_H; /* disable lpc port 80 */ - pci_write_config8(_LPCB_DEV, LPC_IO_OR_MEM_DEC_EN_HIGH, byte); -} - void lpc_enable_sio_decode(const bool addr) { uint32_t decodes; -- To view, visit https://review.coreboot.org/c/coreboot/+/59675 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia5c5a8ec29264a075fefe75038ef2a84684d6427 Gerrit-Change-Number: 59675 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/cezanne: add missing PM_ACPI_* bit definitions
by Felix Held (Code Review) 29 Nov '21

29 Nov '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59588 ) Change subject: soc/amd/cezanne: add missing PM_ACPI_* bit definitions ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > Do we need them of they aren't used? picasso has all bits in this register defined and only uses a few. the file hasn't been updated with the additional bits cezanne has defined and since there's a lot of potentially useful stuff in there, i'd just add the definitions -- To view, visit https://review.coreboot.org/c/coreboot/+/59588 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icd128dca1ec30e7c70501c0e64482159be71cc7b Gerrit-Change-Number: 59588 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Comment-Date: Mon, 29 Nov 2021 20:45:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: comment

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coreboot-gerrit November 2021