coreboot-gerrit November 2021

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Change in coreboot[master]: brya: add various ES variants
by YH Lin (Code Review) 29 Nov '21

29 Nov '21

YH Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59728 ) Change subject: brya: add various ES variants ...................................................................... brya: add various ES variants Fork multiple "4ES" variants off some brya devices to properly support ES SoC. BRANCH=none BUG=b:201767461 TEST=emerge-brya coreboot and check the artifacts Signed-off-by: YH Lin <yueherngl(a)google.com> Change-Id: Ic9516fec591429238bde1478eca2522d8ed10127 --- M src/mainboard/google/brya/Kconfig M src/mainboard/google/brya/Kconfig.name A src/mainboard/google/brya/variants/anahera4es A src/mainboard/google/brya/variants/brya4es A src/mainboard/google/brya/variants/gimble4es A src/mainboard/google/brya/variants/primus4es A src/mainboard/google/brya/variants/redrix4es A src/mainboard/google/brya/variants/taeko4es 8 files changed, 66 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/59728/1 diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index 6231762..a5ca942 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -104,26 +104,38 @@ config MAINBOARD_PART_NUMBER default "Brya" if BOARD_GOOGLE_BRYA0 + default "Brya4ES" if BOARD_GOOGLE_BRYA4ES default "Brask" if BOARD_GOOGLE_BRASK default "Primus" if BOARD_GOOGLE_PRIMUS + default "Primus4ES" if BOARD_GOOGLE_PRIMUS4ES default "Gimble" if BOARD_GOOGLE_GIMBLE + default "Gimble4ES" if BOARD_GOOGLE_GIMBLE4ES default "Redrix" if BOARD_GOOGLE_REDRIX + default "Redrix4ES" if BOARD_GOOGLE_REDRIX4ES default "Kano" if BOARD_GOOGLE_KANO default "Taeko" if BOARD_GOOGLE_TAEKO + default "Taeko4ES" if BOARD_GOOGLE_TAEKO4ES default "Felwinter" if BOARD_GOOGLE_FELWINTER default "Anahera" if BOARD_GOOGLE_ANAHERA + default "Anahera4ES" if BOARD_GOOGLE_ANAHERA4ES default "Vell" if BOARD_GOOGLE_VELL config VARIANT_DIR default "brya0" if BOARD_GOOGLE_BRYA0 + default "brya4es" if BOARD_GOOGLE_BRYA4ES default "brask" if BOARD_GOOGLE_BRASK default "primus" if BOARD_GOOGLE_PRIMUS + default "primus4es" if BOARD_GOOGLE_PRIMUS4ES default "gimble" if BOARD_GOOGLE_GIMBLE + default "gimble4es" if BOARD_GOOGLE_GIMBLE4ES default "redrix" if BOARD_GOOGLE_REDRIX + default "redrix4es" if BOARD_GOOGLE_REDRIX4ES default "kano" if BOARD_GOOGLE_KANO default "taeko" if BOARD_GOOGLE_TAEKO + default "taeko4es" if BOARD_GOOGLE_TAEKO4ES default "felwinter" if BOARD_GOOGLE_FELWINTER default "anahera" if BOARD_GOOGLE_ANAHERA + default "anahera4es" if BOARD_GOOGLE_ANAHERA4ES default "vell" if BOARD_GOOGLE_VELL config VBOOT diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name index 92b71a8..07124ac 100644 --- a/src/mainboard/google/brya/Kconfig.name +++ b/src/mainboard/google/brya/Kconfig.name @@ -10,6 +10,15 @@ select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES select SOC_INTEL_CRASHLOG +config BOARD_GOOGLE_BRYA4ES + bool "-> Brya4ES" + select BOARD_GOOGLE_BASEBOARD_BRYA + select DRIVERS_GENESYSLOGIC_GL9755 + select DRIVERS_INTEL_MIPI_CAMERA + select HAVE_WWAN_POWER_SEQUENCE + select SOC_INTEL_COMMON_BLOCK_IPU + select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES + config BOARD_GOOGLE_BRASK bool "-> Brask" select BOARD_GOOGLE_BASEBOARD_BRASK @@ -24,6 +33,13 @@ select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES select HAVE_WWAN_POWER_SEQUENCE +config BOARD_GOOGLE_PRIMUS4ES + bool "-> Primus4ES" + select BOARD_GOOGLE_BASEBOARD_BRYA + select DRIVERS_GENESYSLOGIC_GL9755 + select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES + select HAVE_WWAN_POWER_SEQUENCE + config BOARD_GOOGLE_GIMBLE bool "-> Gimble" select BOARD_GOOGLE_BASEBOARD_BRYA @@ -32,6 +48,13 @@ select DRIVERS_GENESYSLOGIC_GL9750 select DRIVERS_I2C_MAX98390 +config BOARD_GOOGLE_GIMBLE4ES + bool "-> Gimble4ES" + select BOARD_GOOGLE_BASEBOARD_BRYA + select CHROMEOS_DSM_CALIB if CHROMEOS + select CHROMEOS_DSM_PARAM_FILE_NAME if CHROMEOS + select DRIVERS_I2C_MAX98390 + config BOARD_GOOGLE_REDRIX bool "-> Redrix" select BOARD_GOOGLE_BASEBOARD_BRYA @@ -46,6 +69,19 @@ select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES select HAVE_WWAN_POWER_SEQUENCE +config BOARD_GOOGLE_REDRIX4ES + bool "-> Redrix4ES" + select BOARD_GOOGLE_BASEBOARD_BRYA + select CHROMEOS_DSM_CALIB if CHROMEOS + select CHROMEOS_DSM_PARAM_FILE_NAME if CHROMEOS + select DRIVERS_I2C_MAX98390 + select DRIVERS_INTEL_MIPI_CAMERA + select EC_GOOGLE_CHROMEEC_INCLUDE_SSFC_IN_FW_CONFIG + select SOC_INTEL_COMMON_BLOCK_IPU + select DRIVERS_GENESYSLOGIC_GL9755 + select DRIVERS_GFX_GENERIC + select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES + config BOARD_GOOGLE_KANO bool "-> Kano" select BOARD_GOOGLE_BASEBOARD_BRYA @@ -60,6 +96,11 @@ select BOARD_GOOGLE_BASEBOARD_BRYA select DRIVERS_GENESYSLOGIC_GL9763E +config BOARD_GOOGLE_TAEKO4ES + bool "-> Taeko4ES" + select BOARD_GOOGLE_BASEBOARD_BRYA + select DRIVERS_GENESYSLOGIC_GL9763E + config BOARD_GOOGLE_FELWINTER bool "-> Felwinter" select BOARD_GOOGLE_BASEBOARD_BRYA @@ -72,6 +113,13 @@ select DRIVERS_GFX_GENERIC select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES +config BOARD_GOOGLE_ANAHERA4ES + bool "-> Anahera4ES" + select BOARD_GOOGLE_BASEBOARD_BRYA + select DRIVERS_GENESYSLOGIC_GL9763E + select DRIVERS_GFX_GENERIC + select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES + config BOARD_GOOGLE_VELL bool "-> Vell" select BOARD_GOOGLE_BASEBOARD_BRYA diff --git a/src/mainboard/google/brya/variants/anahera4es b/src/mainboard/google/brya/variants/anahera4es new file mode 120000 index 0000000..d938655 --- /dev/null +++ b/src/mainboard/google/brya/variants/anahera4es @@ -0,0 +1 @@ +anahera \ No newline at end of file diff --git a/src/mainboard/google/brya/variants/brya4es b/src/mainboard/google/brya/variants/brya4es new file mode 120000 index 0000000..6d4e828 --- /dev/null +++ b/src/mainboard/google/brya/variants/brya4es @@ -0,0 +1 @@ +brya0 \ No newline at end of file diff --git a/src/mainboard/google/brya/variants/gimble4es b/src/mainboard/google/brya/variants/gimble4es new file mode 120000 index 0000000..c0e2933 --- /dev/null +++ b/src/mainboard/google/brya/variants/gimble4es @@ -0,0 +1 @@ +gimble \ No newline at end of file diff --git a/src/mainboard/google/brya/variants/primus4es b/src/mainboard/google/brya/variants/primus4es new file mode 120000 index 0000000..1f085cc --- /dev/null +++ b/src/mainboard/google/brya/variants/primus4es @@ -0,0 +1 @@ +primus \ No newline at end of file diff --git a/src/mainboard/google/brya/variants/redrix4es b/src/mainboard/google/brya/variants/redrix4es new file mode 120000 index 0000000..2cf6f1e --- /dev/null +++ b/src/mainboard/google/brya/variants/redrix4es @@ -0,0 +1 @@ +redrix \ No newline at end of file diff --git a/src/mainboard/google/brya/variants/taeko4es b/src/mainboard/google/brya/variants/taeko4es new file mode 120000 index 0000000..9a4278e --- /dev/null +++ b/src/mainboard/google/brya/variants/taeko4es @@ -0,0 +1 @@ +taeko \ No newline at end of file -- To view, visit https://review.coreboot.org/c/coreboot/+/59728 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic9516fec591429238bde1478eca2522d8ed10127 Gerrit-Change-Number: 59728 Gerrit-PatchSet: 1 Gerrit-Owner: YH Lin <yueherngl(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/cezanne: add missing PM_ACPI_* bit definitions
by Raul Rangel (Code Review) 29 Nov '21

29 Nov '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59588 ) Change subject: soc/amd/cezanne: add missing PM_ACPI_* bit definitions ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: Do we need them of they aren't used? -- To view, visit https://review.coreboot.org/c/coreboot/+/59588 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icd128dca1ec30e7c70501c0e64482159be71cc7b Gerrit-Change-Number: 59588 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 29 Nov 2021 17:40:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/lippert/frontrunner-af: Use common cpu/ and nb/ ASL files
by Felix Held (Code Review) 29 Nov '21

29 Nov '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50658 ) Change subject: mb/lippert/frontrunner-af: Use common cpu/ and nb/ ASL files ...................................................................... mb/lippert/frontrunner-af: Use common cpu/ and nb/ ASL files There are no quad-core CPU models with fam14, \_SB.C002 and .C003 get removed from ASL. Change-Id: I96df5b3f93c2dd6a05d5693069b991ca01f71d73 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50658 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/lippert/frontrunner-af/dsdt.asl 1 file changed, 4 insertions(+), 112 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/mainboard/lippert/frontrunner-af/dsdt.asl b/src/mainboard/lippert/frontrunner-af/dsdt.asl index 1839b64..5f834fc 100644 --- a/src/mainboard/lippert/frontrunner-af/dsdt.asl +++ b/src/mainboard/lippert/frontrunner-af/dsdt.asl @@ -13,29 +13,7 @@ { /* Start of ASL file */ #include <acpi/dsdt_top.asl> - - /* - * Processor Object - * - */ - Scope (\_SB) { /* define processor scope */ - Device (C000) { - Name (_HID, "ACPI0007") - Name (_UID, 0) - } - Device (C001) { - Name (_HID, "ACPI0007") - Name (_UID, 1) - } - Device (C002) { - Name (_HID, "ACPI0007") - Name (_UID, 2) - } - Device (C003) { - Name (_HID, "ACPI0007") - Name (_UID, 3) - } - } /* End _SB scope */ + #include <cpu/amd/agesa/family14/acpi/cpu.asl> #include <southbridge/amd/cimx/sb800/acpi/misc_io.asl> @@ -58,10 +36,9 @@ /* _SB.PCI0 */ /* Note: Only need HID on Primary Bus */ Device(PCI0) { - External (TOM1) - External (TOM2) - Name(_HID, EISAID("PNP0A08")) /* PCI Express Root Bridge */ - Name(_CID, EISAID("PNP0A03")) /* PCI Root Bridge */ + + /* Describe the AMD Northbridge */ + #include <northbridge/amd/agesa/family14/acpi/northbridge.asl> /* Operating System Capabilities Method */ Method (_OSC, 4) @@ -93,91 +70,6 @@ Return (PR0) /* PIC Mode */ } /* end _PRT */ - /* Describe the Northbridge devices */ - Device(AMRT) { - Name(_ADR, 0x00000000) - } /* end AMRT */ - - /* The internal GFX bridge */ - Device(AGPB) { - Name(_ADR, 0x00010000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - Return (APR1) - } - } /* end AGPB */ - - /* Dev 2 & 3 are external GFX bridges, not used in Family14 */ - - Device(PBR4) { - Name(_ADR, 0x00040000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PICM){ Return(APS4) } /* APIC mode */ - Return (PS4) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR4 */ - - Device(PBR5) { - Name(_ADR, 0x00050000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PICM){ Return(APS5) } /* APIC mode */ - Return (PS5) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR5 */ - - Device(PBR6) { - Name(_ADR, 0x00060000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PICM){ Return(APS6) } /* APIC mode */ - Return (PS6) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR6 */ - - /* The onboard EtherNet chip */ - Device(PBR7) { - Name(_ADR, 0x00070000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PICM){ Return(APS7) } /* APIC mode */ - Return (PS7) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR7 */ - - Device(PE20) { - Name(_ADR, 0x00150000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PICM){ Return(APE0) } /* APIC mode */ - Return (PE0) /* PIC Mode */ - } /* end _PRT */ - } /* end PE20 */ - Device(PE21) { - Name(_ADR, 0x00150001) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PICM){ Return(APE1) } /* APIC mode */ - Return (PE1) /* PIC Mode */ - } /* end _PRT */ - } /* end PE21 */ - Device(PE22) { - Name(_ADR, 0x00150002) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PICM){ Return(APE2) } /* APIC mode */ - Return (APE2) /* PIC Mode */ - } /* end _PRT */ - } /* end PE22 */ - Device(PE23) { - Name(_ADR, 0x00150003) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PICM){ Return(APE3) } /* APIC mode */ - Return (PE3) /* PIC Mode */ - } /* end _PRT */ - } /* end PE23 */ /* Describe the Southbridge devices */ 4 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/50658 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I96df5b3f93c2dd6a05d5693069b991ca01f71d73 Gerrit-Change-Number: 50658 Gerrit-PatchSet: 6 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/alderlake: Add TDP to give correct VR configuration.
by Tim Wawrzynczak (Code Review) 29 Nov '21

29 Nov '21

Attention is currently required from: Curtis Chen, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59644 ) Change subject: soc/intel/alderlake: Add TDP to give correct VR configuration. ...................................................................... Patch Set 1: (1 comment) File src/soc/intel/alderlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/59644/comment/ab637bd8_463c7c06 PS1, Line 42: 34250 line up with the others, please -- To view, visit https://review.coreboot.org/c/coreboot/+/59644 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4d31e7afc76d9a8c772781671f92ec08f9d8713f Gerrit-Change-Number: 59644 Gerrit-PatchSet: 1 Gerrit-Owner: Curtis Chen <curtis.chen(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Curtis Chen <curtis.chen(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 29 Nov 2021 17:31:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/common/block/lpc: use 32 bit accesses in lpc_enable_port80
by Raul Rangel (Code Review) 29 Nov '21

29 Nov '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59676 ) Change subject: soc/amd/common/block/lpc: use 32 bit accesses in lpc_enable_port80 ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59676 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I001bb1c2ccf99e36d4fbd73d3bf96b78ddb87d67 Gerrit-Change-Number: 59676 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 29 Nov 2021 17:30:43 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/common/block/lpc/lpc_util: drop lpc_enable_pci_port80
by Raul Rangel (Code Review) 29 Nov '21

29 Nov '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59675 ) Change subject: soc/amd/common/block/lpc/lpc_util: drop lpc_enable_pci_port80 ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59675 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia5c5a8ec29264a075fefe75038ef2a84684d6427 Gerrit-Change-Number: 59675 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 29 Nov 2021 17:29:24 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/common/block/include/lpc: add missing LPC_PCI_CONTROL bit defs
by Raul Rangel (Code Review) 29 Nov '21

29 Nov '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59674 ) Change subject: soc/amd/common/block/include/lpc: add missing LPC_PCI_CONTROL bit defs ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/59674/comment/0f72d7bc_b43f97c1 PS1, Line 10: LPC_PCI_CONTROL Do we actually need to define these bits? Is anyone going to use them? -- To view, visit https://review.coreboot.org/c/coreboot/+/59674 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I855e640d020daf21c9f5b2f62a2ad0fd0274a575 Gerrit-Change-Number: 59674 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 29 Nov 2021 17:28:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: [WIP]Cezanne FSP wrapper: Sync with PI 1.0.0.5
by Raul Rangel (Code Review) 29 Nov '21

29 Nov '21

Attention is currently required from: Bao Zheng, Jason Glenesk, Marshall Dawson, Zheng Bao, Rob Barnes, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59687 ) Change subject: [WIP]Cezanne FSP wrapper: Sync with PI 1.0.0.5 ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/59687/comment/dfeb242b_3fffcc7b PS1, Line 7: [WIP] Why WIP? -- To view, visit https://review.coreboot.org/c/coreboot/+/59687 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id95c37a0d7027d75afddf9d7528ff41ae3a347f5 Gerrit-Change-Number: 59687 Gerrit-PatchSet: 1 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 29 Nov 2021 17:25:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/stoneyridge/psp: move soc_get_mbox_address to common psp_gen1
by Raul Rangel (Code Review) 29 Nov '21

29 Nov '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Paul Menzel, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59701 ) Change subject: soc/amd/stoneyridge/psp: move soc_get_mbox_address to common psp_gen1 ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59701 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I78126cb710a6ee674b58b35c8294685a5965ecd6 Gerrit-Change-Number: 59701 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 29 Nov 2021 17:15:08 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/stoneyridge/psp: use PSP_MAILBOX_BAR define
by Raul Rangel (Code Review) 29 Nov '21

29 Nov '21

Attention is currently required from: Marshall Dawson, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59700 ) Change subject: soc/amd/stoneyridge/psp: use PSP_MAILBOX_BAR define ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59700 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8658b674b9adea85dfc71d7036ccf3ae17464b58 Gerrit-Change-Number: 59700 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 29 Nov 2021 17:13:51 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit November 2021