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Change subject: soc/amd/common/block/psp/psp_def: drop PSPV2_STATUS_* defines
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Patch Set 1: Code-Review+2
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Change subject: guybrush: add RO_GSCVD area to FMAP
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Patch Set 2: Code-Review+2
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Change subject: device/pci_device.c: Scan only one device for PCIe
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Patch Set 5:
(1 comment)
File src/device/pci_device.c:
https://review.coreboot.org/c/coreboot/+/56788/comment/48b6c712_e3ef6c72
PS5, Line 1207: normally
> That's not the same thing as "always", though. […]
I don't think that coreboot currently supports ARI devices, however, section 6.13 of the PCIe spec gives this information:
```
ARI is controlled by a new set of optional capability and control register bits. These provide:
- Software the ability to detect whether a component supports ARI.
- Software the ability to configure an ARI Downstream Port so the logic that determines when to turn a Type 1 Configuration Request into a Type 0 Configuration Request no longer enforces a restriction on the traditional Device Number field being 0.
- Software the ability to configure an ARI Device to assign each Function to a Function Group. Controls based on Function Groups may be preferable when finer granularity controls based on individual Functions are not required.
```
The section even gives an example flow to enable ARI devices, so that would probably be the correct way to implement this.
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Change subject: util/cbfstool/.gitignore: Add CSE tool executables
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Patch Set 1: Code-Review+2
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Change subject: acpi: Convert ACPI_DEVICE_SLEEP_* values to an enum
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Patch Set 1:
(1 comment)
Patchset:
PS1:
> oh, didn't think of using those defines in the asl code. […]
It's possible? Usually it's used for e.g. _S0W, which is typically generated by acpigen. We haven't seen a use-case yet for having them in the ASL files (and wouldn't we rather keep more things out of them anyway? 😊)
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Change subject: mb/google/dedede/var/beetley: Enable GEO_SAR_ENABLE for beetley
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Patch Set 4: Code-Review+2
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Change subject: soc/amd/*: PSP verstage minbuild
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Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/59585/comment/3e6cbe5b_0a3b58f0
PS2, Line 9: The PSP that is supplied for Picasso AMD-based chromebooks currently
: requires a psp_verstage to boot
:( this seems unfortunate. Does that mean that non chromeos boards currently don't work? This approach is going to result in the PSP entering developer mode since this verstage blob isn't signed. I think we should push on AMD to fix this in the PSP.
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Change subject: mb/google/brya/var/brask: Set vGPIO reset type
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Patch Set 4: Code-Review+1
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