Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58076 )
Change subject: lib/hardwaremain: change type of "complete" element in boot_state struct
......................................................................
lib/hardwaremain: change type of "complete" element in boot_state struct
A signed bitfield with a length of 1 bit can only have the values 0 and
-1. Assigning a 1 ends up behaving as expected, but it's not the
semantically correct thing to do there. Changing the type of the element
to an unsigned bitfield with a length of 1 would fix that, but since
this is used as a boolean value, just change it to bool type.
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: I230804335e7a15a8a9489859b20846988ba6c5cd
---
M src/lib/hardwaremain.c
1 file changed, 3 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/58076/1
diff --git a/src/lib/hardwaremain.c b/src/lib/hardwaremain.c
index cb45903..fe8e53f 100644
--- a/src/lib/hardwaremain.c
+++ b/src/lib/hardwaremain.c
@@ -56,7 +56,7 @@
boot_state_t (*run_state)(void *arg);
void *arg;
int num_samples;
- int complete : 1;
+ bool complete;
};
#define BS_INIT(state_, run_func_) \
@@ -67,7 +67,7 @@
.phases = { { NULL, 0 }, { NULL, 0 } }, \
.run_state = run_func_, \
.arg = NULL, \
- .complete = 0, \
+ .complete = false, \
}
#define BS_INIT_ENTRY(state_, run_func_) \
[state_] = BS_INIT(state_, run_func_)
@@ -367,7 +367,7 @@
bs_sample_time(state);
- state->complete = 1;
+ state->complete = true;
}
}
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Gerrit-Change-Id: I230804335e7a15a8a9489859b20846988ba6c5cd
Gerrit-Change-Number: 58076
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Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58075 )
Change subject: lib/hardwaremain: add missing types.h include
......................................................................
lib/hardwaremain: add missing types.h include
The u8 type is used in the file, but neither stdint.h not types.h was
included in the file.
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: Ifd67aff9eba01f9618004c869f1473217b3aeae4
---
M src/lib/hardwaremain.c
1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/58075/1
diff --git a/src/lib/hardwaremain.c b/src/lib/hardwaremain.c
index 2f782e7..cb45903 100644
--- a/src/lib/hardwaremain.c
+++ b/src/lib/hardwaremain.c
@@ -23,6 +23,7 @@
#include <thread.h>
#include <timer.h>
#include <timestamp.h>
+#include <types.h>
#include <vendorcode/google/chromeos/gnvs.h>
#include <version.h>
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Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58017 )
Change subject: soc/intel: drop Kconfig `PM_ACPI_TIMER_OPTIONAL`
......................................................................
Patch Set 4:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/58017/comment/17abd26e_9068ae91
PS3, Line 11: according
> respective?
Done
https://review.coreboot.org/c/coreboot/+/58017/comment/dae004c3_d51f0ecf
PS3, Line 12: set, which is done in the, which is done in the, which is done in the,
: which is done in the, which is done in the
:
: This change drops this guard, while actually breaking the spec, in order
: to a) keep the following patch-train in a review-able size and b)
:
> WAT?! :'D
Done
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Hello Felix Singer, build bot (Jenkins), Furquan Shaikh, Mariusz Szafrański, Jonathan Zhang, Paul Menzel, Angel Pons, Subrata Banik, Arthur Heymans, Patrick Rudolph, Lance Zhao, Anjaneya "Reddy" Chagam, Nico Huber, Johnny Lin, Christian Walter, Suresh Bellampalli, Tim Wawrzynczak, Vanessa Eusebio, Michal Motyl, Tim Chu,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#21).
Change subject: soc/intel/{skl,cnl,dnv,xeon_sp}: disable PM ACPI timer if chosen
......................................................................
soc/intel/{skl,cnl,dnv,xeon_sp}: disable PM ACPI timer if chosen
Disable the PM ACPI timer during PMC init, when `USE_PM_ACPI_TIMER` is
disabled. This is done to bring SKL and CNL in line with the other
platforms, in order to transition handling of the PM timer from FSP to
coreboot in the follow-up changes.
For Denverton-NS the PM Timer FADT flag is guarded by the Kconfig, so
we're spec-compliant. The other platforms already have this guard.
Change-Id: I47280cd670a96c8fa5af107986496234f04e1f77
Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de>
---
M src/soc/intel/cannonlake/pmc.c
M src/soc/intel/denverton_ns/acpi.c
M src/soc/intel/denverton_ns/include/soc/pmc.h
M src/soc/intel/denverton_ns/pmc.c
M src/soc/intel/skylake/pmc.c
M src/soc/intel/xeon_sp/include/soc/pmc.h
M src/soc/intel/xeon_sp/pmc.c
7 files changed, 46 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/57932/21
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I'd like you to reexamine a change. Please visit
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Change subject: soc/intel: drop Kconfig `PM_ACPI_TIMER_OPTIONAL`
......................................................................
soc/intel: drop Kconfig `PM_ACPI_TIMER_OPTIONAL`
Technically, it's not depending on the hardware but on the software
(OS/payload), if the PM Timer is optional. OSes with ACPI >= 5.0A
support disabling of the PM Timer, when the respective FADT flag is
unset, which is done as of the parent change. Thus, drop this guard.
Change-Id: I973ad418ba43cbd80b023abf94d3548edc53a561
Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de>
---
M src/soc/intel/cannonlake/Kconfig
M src/soc/intel/common/block/pmc/Kconfig
M src/soc/intel/skylake/Kconfig
3 files changed, 0 insertions(+), 13 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/58017/4
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Change subject: soc/intel/{common,skl,dnv}: set ACPI_FADT_PLATFORM_CLOCK based on Kconfig
......................................................................
Patch Set 18:
(1 comment)
Patchset:
PS17:
> Oh, well, one more thing. […]
found a way... this commit now only fixes the platforms that already can disable
the pm timer; dnv is moved to CB:57932
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Hello Felix Singer, build bot (Jenkins), Furquan Shaikh, Mariusz Szafrański, Paul Menzel, Angel Pons, Subrata Banik, Patrick Rudolph, Lance Zhao, Nico Huber, Tim Wawrzynczak, Suresh Bellampalli, Vanessa Eusebio, Michal Motyl,
I'd like you to reexamine a change. Please visit
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Change subject: soc/intel/{common,skl,dnv}: set ACPI_FADT_PLATFORM_CLOCK based on Kconfig
......................................................................
soc/intel/{common,skl,dnv}: set ACPI_FADT_PLATFORM_CLOCK based on Kconfig
uCode PM ACPI Timer emulation does not support `TMR_STS`. Any OS or
software relying on the overflow flag will not work properly. The FADT
contains a flag `ACPI_FADT_PLATFORM_CLOCK` telling the OSPM if a
specification-compliant PM Timer is present or not. Only set the flag,
when the hardware PM Timer is enabled.
Change-Id: Id2e5d69b5515c21e6ce922dab2cb88b494c65ebe
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---
M src/soc/intel/common/block/acpi/acpi.c
M src/soc/intel/skylake/fadt.c
2 files changed, 8 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/57934/18
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Change subject: soc/intel/{skl,cnl,dnv,xeon_sp}: disable PM ACPI timer if chosen
......................................................................
Patch Set 20:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/57932/comment/6e61cd94_2cd220f0
PS15, Line 9: Disable the PM ACPI timer during the PCH finalize phase, when
> Because that's the place where it was done before and I don't want to make this patch train even lon […]
I've moved it to PM init; see CB:58019
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