coreboot-gerrit October 2021

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Change in coreboot[master]: soc/intel: replace dt option PmTimerDisabled by Kconfig
by Tim Wawrzynczak (Code Review) 01 Oct '21

01 Oct '21

Attention is currently required from: Felix Singer, Lance Zhao, Furquan Shaikh, Tim Wawrzynczak, Jeremy Soller, Paul Menzel, Angel Pons, Subrata Banik, Michael Niewöhner, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58016 ) Change subject: soc/intel: replace dt option PmTimerDisabled by Kconfig ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/58016 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If1811c6b98847b22272acfa35ca44f4fbca68947 Gerrit-Change-Number: 58016 Gerrit-PatchSet: 3 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Lance Zhao Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 01 Oct 2021 20:22:26 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel: deduplicate acpi_fill_soc_wake
by Tim Wawrzynczak (Code Review) 01 Oct '21

01 Oct '21

Attention is currently required from: Felix Singer, Nico Huber, Furquan Shaikh, Paul Menzel, Duncan Laurie, Angel Pons, Michael Niewöhner, Andrey Petrov, Kyösti Mälkki, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58043 ) Change subject: soc/intel: deduplicate acpi_fill_soc_wake ...................................................................... Patch Set 2: Code-Review+1 (1 comment) File src/soc/intel/common/block/acpi/acpi.c: https://review.coreboot.org/c/coreboot/+/58043/comment/c55ef523_5c10ab84 PS1, Line 220: RTC_EN > that bit is in the RTC well... if it's enabled, it will survive, anyways. […] Separate change? -- To view, visit https://review.coreboot.org/c/coreboot/+/58043 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I06628aeb5b82b30142a383b87c82a1e22a073ef5 Gerrit-Change-Number: 58043 Gerrit-PatchSet: 2 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Duncan Laurie Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Duncan Laurie Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 01 Oct 2021 20:22:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brask/var/brask: Configure GPIOs according to schematics
by 9elements QA (Code Review) 01 Oct '21

01 Oct '21

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58041 ) Change subject: mb/google/brask/var/brask: Configure GPIOs according to schematics ...................................................................... Patch Set 5: Automatic boot test returned (PASS/FAIL/TOTAL): 8 / 1 / 9 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/80471 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/80470 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/80469 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/80468 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/80467 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload TianoCore : https://lava.9esec.io/r/80466 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload SeaBIOS : https://lava.9esec.io/r/80465 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload TianoCore : https://lava.9esec.io/r/80464 FAIL: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/80463 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/58041 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I71026565b876739d2a08ef79940f47c476ca70a8 Gerrit-Change-Number: 58041 Gerrit-PatchSet: 5 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Alan Huang <alan-huang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Fri, 01 Oct 2021 20:18:56 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel: Don't send CSE EOP if CSME is disabled
by Tim Wawrzynczak (Code Review) 01 Oct '21

01 Oct '21

Attention is currently required from: Sean Rhodes, Furquan Shaikh, Angel Pons. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57149 ) Change subject: soc/intel: Don't send CSE EOP if CSME is disabled ...................................................................... Patch Set 19: (1 comment) File src/soc/intel/common/block/cse/cse_eop.c: https://review.coreboot.org/c/coreboot/+/57149/comment/9f0e6f54_4c8d7a60 PS17, Line 103: if (cse_is_hfs1_com_soft_temp_disable()) { > You aren't wrong there. […] I think so yes 😊 -- To view, visit https://review.coreboot.org/c/coreboot/+/57149 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic00fdb0d97fefac977c0878d1d5893d07d4481ea Gerrit-Change-Number: 57149 Gerrit-PatchSet: 19 Gerrit-Owner: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Fri, 01 Oct 2021 20:16:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sean Rhodes <admin(a)starlabs.systems> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: driver/intel/pmc_mux/conn: Add type-c port info to cbmem
by Nick Vaccaro (Code Review) 01 Oct '21

01 Oct '21

Attention is currently required from: Furquan Shaikh, Patrick Rudolph. Hello build bot (Jenkins), Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/57345 to look at the new patch set (#13). Change subject: driver/intel/pmc_mux/conn: Add type-c port info to cbmem ...................................................................... driver/intel/pmc_mux/conn: Add type-c port info to cbmem This change adds type-c port information for USB type-c ports to cbmem. BUG=b:149830546 TEST='emerge-volteer coreboot chromeos-bootimage', flash and boot volteer2 to kernel, log in and check cbmem for type-c info exported to the payload: localhost ~ # cbmem -c | grep type-c added type-c port0 info to cbmem: usb2:9 usb3:1 sbu:0 data:0 added type-c port1 info to cbmem: usb2:4 usb3:2 sbu:1 data:0 Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com> Change-Id: Ic56a1ad1b617e3af000664147d21165e6ea3a742 --- M payloads/libpayload/include/coreboot_tables.h M src/commonlib/include/commonlib/coreboot_tables.h M src/drivers/intel/pmc_mux/conn/chip.h M src/drivers/intel/pmc_mux/conn/conn.c 4 files changed, 85 insertions(+), 18 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/57345/13 -- To view, visit https://review.coreboot.org/c/coreboot/+/57345 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic56a1ad1b617e3af000664147d21165e6ea3a742 Gerrit-Change-Number: 57345 Gerrit-PatchSet: 13 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: coreboot tables: Add type-c port info to coreboot table
by Nick Vaccaro (Code Review) 01 Oct '21

01 Oct '21

Attention is currently required from: Nico Huber, Furquan Shaikh, Tim Wawrzynczak. Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Zhuohao Lee, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/57069 to look at the new patch set (#29). Change subject: coreboot tables: Add type-c port info to coreboot table ...................................................................... coreboot tables: Add type-c port info to coreboot table This change adds type-c port information for USB Type-C ports to the coreboot table. This allows depthcharge to know the usb2 and usb3 port number assignments for each available port, as well as the SBU and data line orientation for the board. BUG=b:149830546 TEST='emerge-volteer coreboot chromeos-bootimage' and verify it builds successfully. Cherry-pick CL to enable this feature for volteer, flash and boot volteer2 to kernel, log in and check cbmem for type-c info exported to the payload: localhost ~ # cbmem -c | grep type-c added type-c port0 info to cbmem: usb2:9 usb3:1 sbu:0 data:0 added type-c port1 info to cbmem: usb2:4 usb3:2 sbu:1 data:0 Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com> Change-Id: Ice732be2fa634dbf31ec620552b383c4a5b41451 --- M payloads/libpayload/include/coreboot_tables.h M payloads/libpayload/include/sysinfo.h M payloads/libpayload/libc/coreboot.c M src/commonlib/include/commonlib/cbmem_id.h M src/commonlib/include/commonlib/coreboot_tables.h M src/lib/coreboot_table.c 6 files changed, 57 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/57069/29 -- To view, visit https://review.coreboot.org/c/coreboot/+/57069 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ice732be2fa634dbf31ec620552b383c4a5b41451 Gerrit-Change-Number: 57069 Gerrit-PatchSet: 29 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: drivers/intel/dptf: Add support for PCH methods
by Tim Wawrzynczak (Code Review) 01 Oct '21

01 Oct '21

Attention is currently required from: Furquan Shaikh, Sumeet R Pawnikar, Patrick Rudolph, Karthik Ramasubramanian, Felix Held. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57925 ) Change subject: drivers/intel/dptf: Add support for PCH methods ...................................................................... Patch Set 5: (2 comments) File src/drivers/intel/dptf/dptf.c: https://review.coreboot.org/c/coreboot/+/57925/comment/8b15dbef_7791e0c2 PS4, Line 356: write_pkgc_method(); > This is required only for READ methods, not required for WRITE. So, I kept inside if(... […] But this will write out 5 copies of the PKGC Method won't it? Don't you see something in `dmesg` about conflicting definitions? Have you double checked the SSDT output? File src/drivers/intel/dptf/dptf.c: https://review.coreboot.org/c/coreboot/+/57925/comment/7ff4c973_dd23d7cd PS5, Line 230: acpigen_write_package(1); : acpigen_write_zero(); Sorry I mean this seems like a separate change. I had thought the above `Return 0` was working. Is this a change in the ESIF shell that it requires a package now? -- To view, visit https://review.coreboot.org/c/coreboot/+/57925 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2d40fff98cb4eb9144d55fd5383d9946e4cb0558 Gerrit-Change-Number: 57925 Gerrit-PatchSet: 5 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 01 Oct 2021 20:13:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: Documentation: Fix spelling errors.
by Martin Roth (Code Review) 01 Oct '21

01 Oct '21

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58078 ) Change subject: Documentation: Fix spelling errors. ...................................................................... Documentation: Fix spelling errors. These issues were found and fixed by codespell, a useful tool for finding spelling errors. Signed-off-by: Martin Roth <martin(a)coreboot.org> Change-Id: If2a8e97911420c19e9365d5c28810b998f2c2ac8 --- M Documentation/RFC/chip.tex M Documentation/acpi/devicetree.md M Documentation/arch/x86/index.md M Documentation/conf.py M Documentation/contributing/coding_style.md M Documentation/contributing/project_ideas.md M Documentation/drivers/index.md M Documentation/flash_tutorial/index.md M Documentation/gcov.txt M Documentation/getting_started/architecture.md M Documentation/getting_started/writing_documentation.md M Documentation/lib/payloads/fit.md M Documentation/lib/timestamp.md M Documentation/mainboard/amd/padmelon/padmelon.md M Documentation/mainboard/asus/p8c_ws.md M Documentation/mainboard/emulation/qemu-aarch64.md M Documentation/mainboard/lenovo/Ivy_Bridge_series.md M Documentation/mainboard/lenovo/Sandy_Bridge_series.md M Documentation/mainboard/lenovo/vboot.md M Documentation/mainboard/ocp/tiogapass.md M Documentation/mainboard/supermicro/x9sae.md M Documentation/mainboard/up/squared/index.md M Documentation/northbridge/intel/sandybridge/nri.md M Documentation/northbridge/intel/sandybridge/nri_freq.md M Documentation/northbridge/intel/sandybridge/nri_registers.md M Documentation/releases/coreboot-4.13-relnotes.md M Documentation/releases/coreboot-4.3-relnotes.md M Documentation/security/intel/txt.md M Documentation/security/smm.md M Documentation/security/vboot/measured_boot.md M Documentation/soc/cavium/cn81xx/index.md M Documentation/superio/common/ssdt.md M Documentation/superio/nuvoton/npcd378.md M Documentation/technotes/2020-03-unit-testing-coreboot.md M Documentation/tutorial/part1.md M Documentation/util.md 36 files changed, 45 insertions(+), 45 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/58078/1 diff --git a/Documentation/RFC/chip.tex b/Documentation/RFC/chip.tex index 01f40c1..c671092 100644 --- a/Documentation/RFC/chip.tex +++ b/Documentation/RFC/chip.tex @@ -7,7 +7,7 @@ \section{Scope} This document defines how LinuxBIOS programmers can specify chips that -are used, specified, and initalized. The current scope is for superio +are used, specified, and initialized. The current scope is for superio chips, but the architecture should allow for specification of other chips such as southbridges. Multiple chips of same or different type are supported. diff --git a/Documentation/acpi/devicetree.md b/Documentation/acpi/devicetree.md index 5cbaf15..41f5901 100644 --- a/Documentation/acpi/devicetree.md +++ b/Documentation/acpi/devicetree.md @@ -5,7 +5,7 @@ ACPI exposes a platform-independent interface for operating systems to perform power management and other platform-level functions. Some operating systems also use ACPI to enumerate devices that are not immediately discoverable, such -as those behind I2C or SPI busses (in contrast to PCI). This document discusses +as those behind I2C or SPI buses (in contrast to PCI). This document discusses the way that coreboot uses the concept of a "device tree" to generate ACPI tables for usage by the operating system. diff --git a/Documentation/arch/x86/index.md b/Documentation/arch/x86/index.md index 0e14115..a30c5e2 100644 --- a/Documentation/arch/x86/index.md +++ b/Documentation/arch/x86/index.md @@ -92,6 +92,6 @@ page tables in ROM will be loaded and used, which breaks code and data as the page table doesn't contain the expected data. This in turn leads to undefined behaviour whenever the 'wrong' address is being read. -* Disabling paging in compability mode crashes the CPU. -* Returning from long mode to compability mode crashes the CPU. +* Disabling paging in compatibility mode crashes the CPU. +* Returning from long mode to compatibility mode crashes the CPU. * Entering long mode crashes on AMD host platforms. diff --git a/Documentation/conf.py b/Documentation/conf.py index 3180fd9..70b189a 100644 --- a/Documentation/conf.py +++ b/Documentation/conf.py @@ -185,7 +185,7 @@ enable_auto_toc_tree = True class MyCommonMarkParser(CommonMarkParser): - # remove this hack once upsteam RecommonMark supports inline code + # remove this hack once upstream RecommonMark supports inline code def visit_code(self, mdnode): from docutils import nodes n = nodes.literal(mdnode.literal, mdnode.literal) diff --git a/Documentation/contributing/coding_style.md b/Documentation/contributing/coding_style.md index a8c7356..4980659 100644 --- a/Documentation/contributing/coding_style.md +++ b/Documentation/contributing/coding_style.md @@ -801,7 +801,7 @@ A reasonable rule of thumb is to not put inline at functions that have more than 3 lines of code in them. An exception to this rule are the -cases where a parameter is known to be a compiletime constant, and as a +cases where a parameter is known to be a compile time constant, and as a result of this constantness you *know* the compiler will be able to optimize most of your function away at compile time. For a good example of this later case, see the kmalloc() inline function. diff --git a/Documentation/contributing/project_ideas.md b/Documentation/contributing/project_ideas.md index 2f6f738..75c78ca 100644 --- a/Documentation/contributing/project_ideas.md +++ b/Documentation/contributing/project_ideas.md @@ -202,9 +202,9 @@ and libraries, consisting of a backend, a frontend and client side scripts. The backend should connect to an SQL database with can be controlled using a RESTful API. The RESTful API should have basic authentication -for managment tasks and new board status uploads. +for management tasks and new board status uploads. -At least one older test result should be keept in the database. +At least one older test result should be kept in the database. The frontend should use established UI libraries or frameworks (for example Angular) to display the current board status, that is if it's working or not diff --git a/Documentation/drivers/index.md b/Documentation/drivers/index.md index 40d747d..1b8539d 100644 --- a/Documentation/drivers/index.md +++ b/Documentation/drivers/index.md @@ -2,7 +2,7 @@ The drivers can be found in `src/drivers`. They are intended for onboard and plugin devices, significantly reducing integration complexity and -they allow to easily reuse existing code accross platforms. +they allow to easily reuse existing code across platforms. * [Intel DPTF](dptf.md) * [IPMI KCS](ipmi_kcs.md) diff --git a/Documentation/flash_tutorial/index.md b/Documentation/flash_tutorial/index.md index 4338297..da3d7f0 100644 --- a/Documentation/flash_tutorial/index.md +++ b/Documentation/flash_tutorial/index.md @@ -7,7 +7,7 @@ ## Contents -* [Flashing internaly](int_flashrom.md) +* [Flashing internally](int_flashrom.md) * [Flashing firmware standalone](ext_standalone.md) * [Flashing firmware externally supplying direct power](ext_power.md) * [Flashing firmware externally without supplying direct power](no_ext_power.md) diff --git a/Documentation/gcov.txt b/Documentation/gcov.txt index 896ec93..750e883 100644 --- a/Documentation/gcov.txt +++ b/Documentation/gcov.txt @@ -19,7 +19,7 @@ +#define BITS_PER_UNIT 8 +#define LONG_LONG_TYPE_SIZE 64 + -+/* There are many gcc_assertions. Set the vaule to 1 if we want a warning ++/* There are many gcc_assertions. Set the value to 1 if we want a warning + message if the assertion fails. */ +#ifndef ENABLE_ASSERT_CHECKING +#define ENABLE_ASSERT_CHECKING 1 diff --git a/Documentation/getting_started/architecture.md b/Documentation/getting_started/architecture.md index 8d63ac2..09fb960 100644 --- a/Documentation/getting_started/architecture.md +++ b/Documentation/getting_started/architecture.md @@ -41,7 +41,7 @@ ### Cache-As-Ram The *Cache-As-Ram*, also called Non-Eviction mode, or *CAR* allows to use the -CPU cache like regular SRAM. This is particullary usefull for high level +CPU cache like regular SRAM. This is particullary useful for high level languages like `C`, which need RAM for heap and stack. The CAR needs to be activated using vendor specific CPU instructions. @@ -85,7 +85,7 @@ * CPU init (like set up SMM) After initialization tables are written to inform the payload or operating system -about the current hardware existance and state. That includes: +about the current hardware existence and state. That includes: * ACPI tables (x86 specific) * SMBIOS tables (x86 specific) diff --git a/Documentation/getting_started/writing_documentation.md b/Documentation/getting_started/writing_documentation.md index 384fc6d..480ad78 100644 --- a/Documentation/getting_started/writing_documentation.md +++ b/Documentation/getting_started/writing_documentation.md @@ -6,7 +6,7 @@ That said please always try to write documentation! One problem in the firmware development is the missing documentation. In this document you will get a brief introduction how to write, submit and publish -documenation to coreboot. +documentation to coreboot. ## Preparations diff --git a/Documentation/lib/payloads/fit.md b/Documentation/lib/payloads/fit.md index ef5e892..ac3c183 100644 --- a/Documentation/lib/payloads/fit.md +++ b/Documentation/lib/payloads/fit.md @@ -25,7 +25,7 @@ ## Architecture specifics -The FIT parser needs architecure support. +The FIT parser needs architecture support. ### aarch32 The source code can be found in `src/arch/arm/fit_payload.c`. diff --git a/Documentation/lib/timestamp.md b/Documentation/lib/timestamp.md index d5dc8fa..a769f99 100644 --- a/Documentation/lib/timestamp.md +++ b/Documentation/lib/timestamp.md @@ -99,7 +99,7 @@ ### entries -This field holds the details of each timestamp entry, upto a maximum +This field holds the details of each timestamp entry, up to a maximum of `MAX_TIMESTAMP_CACHE` which is defined as 16 entries. Each entry is defined by: diff --git a/Documentation/mainboard/amd/padmelon/padmelon.md b/Documentation/mainboard/amd/padmelon/padmelon.md index 20b1b13..975426d 100644 --- a/Documentation/mainboard/amd/padmelon/padmelon.md +++ b/Documentation/mainboard/amd/padmelon/padmelon.md @@ -43,7 +43,7 @@ +---------------------+--------------------+ | Size | 8 MiB | +---------------------+--------------------+ -| Flash programing | dediprog header | +| Flash programming | dediprog header | +---------------------+--------------------+ | Package | SOIC-8 | +---------------------+--------------------+ diff --git a/Documentation/mainboard/asus/p8c_ws.md b/Documentation/mainboard/asus/p8c_ws.md index a9aa589..7b4296f 100644 --- a/Documentation/mainboard/asus/p8c_ws.md +++ b/Documentation/mainboard/asus/p8c_ws.md @@ -56,7 +56,7 @@ - Native raminit - Integrated graphics with libgfxinit (both analog and digital output from DVI-I) - Nvidia Quadro 600 in all PCIe-16x slots -- Compex WLM200NX (Qualcomm Atheros AR9220) in PCI slot +- Complex WLM200NX (Qualcomm Atheros AR9220) in PCI slot - Onboard IEEE1394 controller under PCI bus - Debug output from serial port diff --git a/Documentation/mainboard/emulation/qemu-aarch64.md b/Documentation/mainboard/emulation/qemu-aarch64.md index 4df36a9..6db8cef 100644 --- a/Documentation/mainboard/emulation/qemu-aarch64.md +++ b/Documentation/mainboard/emulation/qemu-aarch64.md @@ -1,5 +1,5 @@ # QEMU AArch64 emulator -This page discribes how to build and run coreboot for QEMU/AArch64. +This page describes how to build and run coreboot for QEMU/AArch64. You can use LinuxBoot via `make menuconfig` or an arbitrary FIT image as a payload for QEMU/AArch64. diff --git a/Documentation/mainboard/lenovo/Ivy_Bridge_series.md b/Documentation/mainboard/lenovo/Ivy_Bridge_series.md index 0f3e4c3..ca02b3c 100644 --- a/Documentation/mainboard/lenovo/Ivy_Bridge_series.md +++ b/Documentation/mainboard/lenovo/Ivy_Bridge_series.md @@ -76,7 +76,7 @@ [fl]: flashlayout_Ivy_Bridge.svg -## Reducing Intel Managment Engine firmware size +## Reducing Intel Management Engine firmware size It is possible to reduce the Intel ME firmware size to free additional space for the `bios` region. This is usually referred to as *cleaning the ME* or diff --git a/Documentation/mainboard/lenovo/Sandy_Bridge_series.md b/Documentation/mainboard/lenovo/Sandy_Bridge_series.md index 84bae40..e1d9c77 100644 --- a/Documentation/mainboard/lenovo/Sandy_Bridge_series.md +++ b/Documentation/mainboard/lenovo/Sandy_Bridge_series.md @@ -48,7 +48,7 @@ [fl]: flashlayout_Sandy_Bridge.svg -## Reducing Intel Managment Engine firmware size +## Reducing Intel Management Engine firmware size It is possible to reduce the Intel ME firmware size to free additional space for the `bios` region. This is usually referred to as *cleaning the ME* or diff --git a/Documentation/mainboard/lenovo/vboot.md b/Documentation/mainboard/lenovo/vboot.md index 3f15360..0a451ab 100644 --- a/Documentation/mainboard/lenovo/vboot.md +++ b/Documentation/mainboard/lenovo/vboot.md @@ -28,7 +28,7 @@ ## 8 MiB ROM limitation *Lenovo* devices with 8 MiB ROM only have a `RO`+`A` partition enabled in the -default FMAP. They are missing the `B` partition, due to size constaints. +default FMAP. They are missing the `B` partition, due to size constraints. You can still provide your own FMAP if you need `RO`+`A`+`B` partitions. ## CMOS diff --git a/Documentation/mainboard/ocp/tiogapass.md b/Documentation/mainboard/ocp/tiogapass.md index 6d6afb1..8c49923 100644 --- a/Documentation/mainboard/ocp/tiogapass.md +++ b/Documentation/mainboard/ocp/tiogapass.md @@ -51,7 +51,7 @@ ## Known issues / feature gaps - C6 state is not supported. Workaround is to disable C6 support through - target OS and Linuxboot kernel paramter, such as "cpuidle.off=1". + target OS and Linuxboot kernel parameter, such as "cpuidle.off=1". - SMI handlers are not implemented. - xSDT tables are not fully populated, such as processor/socket devices, PCIe bridge devices. diff --git a/Documentation/mainboard/supermicro/x9sae.md b/Documentation/mainboard/supermicro/x9sae.md index ddc5ac7..85fae53 100644 --- a/Documentation/mainboard/supermicro/x9sae.md +++ b/Documentation/mainboard/supermicro/x9sae.md @@ -60,7 +60,7 @@ ## Working (on my X9SAE-V) - Intel Xeon E3-1225 V2 with 4 M391B1G73BH0-YK0 UDIMMs, ECC confirmed active - PS/2 keyboard with SeaBIOS 1.14.0 and Debian GNU/Linux with kernel 5.10.46 -- Use PS/2 keyboard and mouse simutaneously with a PS/2 Y-cable +- Use PS/2 keyboard and mouse simultaneously with a PS/2 Y-cable - Both Onboard NIC - S3 Suspend to RAM - USB2 on rear and front panel connectors @@ -71,7 +71,7 @@ - Native raminit - Integrated graphics with libgfxinit - Nvidia Quadro 600 in all PCIe-16x slots -- Compex WLM200NX (Qualcomm Atheros AR9220) in PCI slot +- Complex WLM200NX (Qualcomm Atheros AR9220) in PCI slot - Debug output from serial port ## Untested diff --git a/Documentation/mainboard/up/squared/index.md b/Documentation/mainboard/up/squared/index.md index d07f111..2895e1f 100644 --- a/Documentation/mainboard/up/squared/index.md +++ b/Documentation/mainboard/up/squared/index.md @@ -48,7 +48,7 @@ +---------------------+------------+ | Internal flashing | No | +---------------------+------------+ -| In curcuit flashing | Yes | +| In circuit flashing | Yes | +---------------------+------------+ ``` @@ -67,8 +67,8 @@ The SPI header is located on the **bottom** side (see [here][overview_bottom_link]). ![][header_cn22] -### Preperations -In order to build coreboot, it's neccessary to extract some files from the vendor firmware. Make sure that you have a fully working dump. +### Preparations +In order to build coreboot, it's necessary to extract some files from the vendor firmware. Make sure that you have a fully working dump. ```bash [upsquared]$ ls firmware_vendor.rom diff --git a/Documentation/northbridge/intel/sandybridge/nri.md b/Documentation/northbridge/intel/sandybridge/nri.md index bf0b89f..1cd5fb4 100644 --- a/Documentation/northbridge/intel/sandybridge/nri.md +++ b/Documentation/northbridge/intel/sandybridge/nri.md @@ -40,7 +40,7 @@ +---------+-------------------------------------------------------------------+------------+--------------+ ``` -## (Unoffical) register documentation +## (Unofficial) register documentation - [Sandy Bridge - Register documentation](nri_registers.md) ## Frequency selection @@ -101,7 +101,7 @@ As of writing the only supported error handling is to disable the failing channel and restart the memory training sequence. It's very likely to succeed, as memory channels operate independent of each other. -In case no DIMM could be initilized coreboot will halt. The screen will stay +In case no DIMM could be initialized coreboot will halt. The screen will stay black until you power of your device. On some platforms there's additional feedback to indicate such an event. diff --git a/Documentation/northbridge/intel/sandybridge/nri_freq.md b/Documentation/northbridge/intel/sandybridge/nri_freq.md index 208c1cb..8d66b5c 100644 --- a/Documentation/northbridge/intel/sandybridge/nri_freq.md +++ b/Documentation/northbridge/intel/sandybridge/nri_freq.md @@ -42,7 +42,7 @@ * 1.5V operating voltage * The channel's installed DIMM count doesn't exceed the XMP coded limit -In case the XMP profile doesn't fullfill those limits, the regular SPD will be +In case the XMP profile doesn't fulfill those limits, the regular SPD will be used. > **Note:** XMP Profiles are supported since coreboot 4.4. diff --git a/Documentation/northbridge/intel/sandybridge/nri_registers.md b/Documentation/northbridge/intel/sandybridge/nri_registers.md index aae1205..32bd3d1 100644 --- a/Documentation/northbridge/intel/sandybridge/nri_registers.md +++ b/Documentation/northbridge/intel/sandybridge/nri_registers.md @@ -1947,7 +1947,7 @@ +-----------+------------------------------------------------------------------+ | Bit | Description | +===========+==================================================================+ -| 0:7| OREF_RI, Rank idle period that defines an oppertunity for | +| 0:7| OREF_RI, Rank idle period that defines an opportunity for | | | refresh | +-----------+------------------------------------------------------------------+ | 8:11| Refresh_HP_WM, tREFI count level that turns the refresh | diff --git a/Documentation/releases/coreboot-4.13-relnotes.md b/Documentation/releases/coreboot-4.13-relnotes.md index 971d438..600bf67 100644 --- a/Documentation/releases/coreboot-4.13-relnotes.md +++ b/Documentation/releases/coreboot-4.13-relnotes.md @@ -200,7 +200,7 @@ ### Resource allocator v4 A new revision of resource allocator v4 is now added to coreboot that supports -mutiple ranges for allocating resources. Unlike the previous allocator (v3), it does +multiple ranges for allocating resources. Unlike the previous allocator (v3), it does not use the topmost available window for allocation. Instead, it uses the first window within the address space that is available and satisfies the resource request. This allows utilization of the entire available address space and also allows diff --git a/Documentation/releases/coreboot-4.3-relnotes.md b/Documentation/releases/coreboot-4.3-relnotes.md index c33c48a..c0dda6e 100644 --- a/Documentation/releases/coreboot-4.3-relnotes.md +++ b/Documentation/releases/coreboot-4.3-relnotes.md @@ -124,7 +124,7 @@ Areas with significant work on updates and fixes ------------------------------------------------ * cpu/amd/model_fxx -* intel/fsp1_x: Fix timestanps & postcodes, add native CAR & microcode +* intel/fsp1_x: Fix timestamps & postcodes, add native CAR & microcode * nb/amd/amdfam10: Add S3, voltage & ACPI, speed fixes & MANY other changes * nb/amd/amdmct: Add S3, mem voltage, Fix performance & MANY other diff --git a/Documentation/security/intel/txt.md b/Documentation/security/intel/txt.md index f80a731..7a746ec 100644 --- a/Documentation/security/intel/txt.md +++ b/Documentation/security/intel/txt.md @@ -37,7 +37,7 @@ ### Measurements The IBBs (Initial Boot Blocks) are measured into TPM's PCR0 by the BIOS [ACM] -before the CPU reset vector is executed. To indentify the regions that need +before the CPU reset vector is executed. To identify the regions that need to be measured, the [FIT] contains one ore multiple *Type 7* entries, that point to the IBBs. diff --git a/Documentation/security/smm.md b/Documentation/security/smm.md index 4e95427..397b7af 100644 --- a/Documentation/security/smm.md +++ b/Documentation/security/smm.md @@ -1,4 +1,4 @@ -# x86 System Managment Mode +# x86 System Management Mode ## Introduction @@ -6,7 +6,7 @@ to applications running in [ring0]. It has a higher privilege level than [ring0] and resides in the SMRAM region which cannot be accessed from [ring0]. -SMM can be entered by issuing System Managment Interrupts (SMIs). +SMM can be entered by issuing System Management Interrupts (SMIs). ## Secure data exchange diff --git a/Documentation/security/vboot/measured_boot.md b/Documentation/security/vboot/measured_boot.md index df4cc68..adfae46 100644 --- a/Documentation/security/vboot/measured_boot.md +++ b/Documentation/security/vboot/measured_boot.md @@ -9,7 +9,7 @@ code block loaded at reset vector and measured by a DRTM solution. In case SRTM mode is active, the IBB measures itself before measuring the next code block. In coreboot, cbfs files which are part of the IBB are identified -by a metatdata tag. This makes it possible to have platform specific IBB +by a metadata tag. This makes it possible to have platform specific IBB measurements without hardcoding them. ## Known Limitations diff --git a/Documentation/soc/cavium/cn81xx/index.md b/Documentation/soc/cavium/cn81xx/index.md index 3063b94..684948c 100644 --- a/Documentation/soc/cavium/cn81xx/index.md +++ b/Documentation/soc/cavium/cn81xx/index.md @@ -21,7 +21,7 @@ * Secondary CPUs * PCI -All other hardware is initilized by the BDK code, which is invoked from +All other hardware is initialized by the BDK code, which is invoked from ramstage. ## Notes about the hardware diff --git a/Documentation/superio/common/ssdt.md b/Documentation/superio/common/ssdt.md index 2f4049e..5f9e2f6 100644 --- a/Documentation/superio/common/ssdt.md +++ b/Documentation/superio/common/ssdt.md @@ -50,7 +50,7 @@ The following methods are generated for each SuperIO: ## AMTX() Acquire the global mutex and enter config mode. -It's called this at the begining of an atomic operation to make sure +It's called this at the beginning of an atomic operation to make sure no other ACPI code messes with the config space while working on it. ## RMTX() @@ -63,7 +63,7 @@ ## DLDN(Arg0) Disables the (virtual) LDN given as Arg0. -This method aquires the global mutex. +This method acquires the global mutex. ## QLDN(Arg0) Queries the state of the (virtual) LDN given as Arg0. diff --git a/Documentation/superio/nuvoton/npcd378.md b/Documentation/superio/nuvoton/npcd378.md index f7fe1a5..11a0a88 100644 --- a/Documentation/superio/nuvoton/npcd378.md +++ b/Documentation/superio/nuvoton/npcd378.md @@ -4,7 +4,7 @@ mainboards. As no datasheet is available most of the functions have been reverse engineered and -might be inacurate or wrong. +might be inaccurate or wrong. ## LDNs diff --git a/Documentation/technotes/2020-03-unit-testing-coreboot.md b/Documentation/technotes/2020-03-unit-testing-coreboot.md index 02c2e30..a4d283f 100644 --- a/Documentation/technotes/2020-03-unit-testing-coreboot.md +++ b/Documentation/technotes/2020-03-unit-testing-coreboot.md @@ -83,7 +83,7 @@ Compiler for the host _must_ support the same language standards as the target compiler. Ideally the same toolchain should be used for building firmware - executables and test binaries, however the host complier will be used to build + executables and test binaries, however the host compiler will be used to build unit tests, whereas the coreboot toolchain will be used for building the firmware executables. For some targets, the host compiler and the target compiler could be the same, but this is not a requirement. diff --git a/Documentation/tutorial/part1.md b/Documentation/tutorial/part1.md index e02812b..8702488 100644 --- a/Documentation/tutorial/part1.md +++ b/Documentation/tutorial/part1.md @@ -123,7 +123,7 @@ of the same version. If you started with a different distribution or package management system you -might need to install other packages. Most likely they are named sightly +might need to install other packages. Most likely they are named slightly different. If that is the case for you, we'd like to encourage you to contribute to the project and submit a pull request with an update for this documentation for your system. diff --git a/Documentation/util.md b/Documentation/util.md index 083401f..8c6bcb7 100644 --- a/Documentation/util.md +++ b/Documentation/util.md @@ -57,7 +57,7 @@ hardware configuration (register contents, MSRs, etc). `C` * __intelvbttool__ - Parse VBT from VGA BIOS `C` * __ipqheader__ - * _createxbl.py_ - Concatentates XBL segments into one ELF + * _createxbl.py_ - Concatenates XBL segments into one ELF image `Python` * _ipqheader.py_ - Returns a packed MBN header image with the specified base and size `Python` -- To view, visit https://review.coreboot.org/c/coreboot/+/58078 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If2a8e97911420c19e9365d5c28810b998f2c2ac8 Gerrit-Change-Number: 58078 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: driver/intel/pmc_mux/conn: Add type-c port info to cbmem
by Tim Wawrzynczak (Code Review) 01 Oct '21

01 Oct '21

Attention is currently required from: Furquan Shaikh, Nick Vaccaro, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57345 ) Change subject: driver/intel/pmc_mux/conn: Add type-c port info to cbmem ...................................................................... Patch Set 12: (2 comments) Patchset: PS12: this patch train is looking really nice! 😊 File src/drivers/intel/pmc_mux/conn/conn.c: https://review.coreboot.org/c/coreboot/+/57345/comment/049b26eb_c63e1106 PS12, Line 129: = noop_read_resources, : .set_resources = noop_set_resources, : .acpi_name = conn_acpi_name, : .acpi_fill_ssdt = conn_fill_ssdt, : .init = conn_init, : .final = nit: align using tabs -- To view, visit https://review.coreboot.org/c/coreboot/+/57345 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic56a1ad1b617e3af000664147d21165e6ea3a742 Gerrit-Change-Number: 57345 Gerrit-PatchSet: 12 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 01 Oct 2021 20:10:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Skip setting D0I3 bit for HECI devices
by Tim Wawrzynczak (Code Review) 01 Oct '21

01 Oct '21

Attention is currently required from: Maulik V Vaghela, Subrata Banik, Angel Pons, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57815 ) Change subject: soc/intel/alderlake: Skip setting D0I3 bit for HECI devices ...................................................................... Patch Set 8: (1 comment) File src/soc/intel/alderlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/57815/comment/7cbccb4b_de00275e PS8, Line 657: CONFIG(SOC_INTEL_CSE_SET_EOP); As mentioned in previous patch, I think we can just set this to `1` if we leave the `heci_finalize` call in. -- To view, visit https://review.coreboot.org/c/coreboot/+/57815 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I86d61c49b8f187611efd495712ad901184665f31 Gerrit-Change-Number: 57815 Gerrit-PatchSet: 8 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 01 Oct 2021 20:05:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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