coreboot-gerrit October 2021

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Change in coreboot[master]: src/mainboard to src/security: Fix spelling errors.
by Martin Roth (Code Review) 01 Oct '21

01 Oct '21

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58081 ) Change subject: src/mainboard to src/security: Fix spelling errors. ...................................................................... src/mainboard to src/security: Fix spelling errors. These issues were found and fixed by codespell, a useful tool for finding spelling errors. Signed-off-by: Martin Roth <martin(a)coreboot.org> Change-Id: Ie34003a9fdfe9f3b1b8ec0789aeca8b9435c9c79 --- M src/mainboard/amd/bilby/devicetree.cb M src/mainboard/amd/mandolin/variants/cereme/devicetree.cb M src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb M src/mainboard/asrock/b75pro3-m/devicetree.cb M src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb M src/mainboard/asrock/g41c-gs/variants/g41c-gs/devicetree.cb M src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb M src/mainboard/asus/p5qpl-am/variants/p5qpl-am/overridetree.cb M src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/early_init.c M src/mainboard/emulation/qemu-armv7/memlayout.ld M src/mainboard/emulation/qemu-i440fx/fw_cfg_if.h M src/mainboard/emulation/qemu-q35/bootblock.c M src/mainboard/facebook/fbg1701/ramstage.c M src/mainboard/facebook/fbg1701/spd/KINGSTON_B5116ECMDXGGB.spd.hex M src/mainboard/facebook/fbg1701/spd/MICRON_MT41K512M16HA-125A.spd.hex M src/mainboard/facebook/fbg1701/spd/SAMSUNG_K4B8G1646D-MYKO.spd.hex M src/mainboard/google/daisy/mainboard.c M src/mainboard/google/foster/bct/jtag.cfg M src/mainboard/google/gru/pwm_regulator.c M src/mainboard/google/guybrush/variants/baseboard/devicetree.cb M src/mainboard/google/hatch/variants/baseboard/devicetree.cb M src/mainboard/google/kahlee/mainboard.c M src/mainboard/google/mistral/romstage.c M src/mainboard/google/oak/mainboard.c M src/mainboard/google/octopus/mainboard.c M src/mainboard/google/octopus/variants/baseboard/gpio.c M src/mainboard/google/octopus/variants/yorp/gpio.c M src/mainboard/google/peach_pit/mainboard.c M src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/camera_pmic.asl M src/mainboard/google/smaug/bct/jtag.cfg M src/mainboard/google/stout/dsdt.asl M src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb M src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb M src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h M src/mainboard/intel/dcp847ske/devicetree.cb M src/mainboard/intel/dg41wv/devicetree.cb M src/mainboard/intel/kblrvp/acpi/mipi_camera.asl M src/mainboard/jetway/nf81-t56n-lf/OemCustomize.c M src/mainboard/lenovo/s230u/acpi/ec.asl M src/mainboard/lippert/frontrunner-af/dsdt.asl M src/mainboard/portwell/m107/spd/KINGSTON_B5116ECMDXGGB.spd.hex M src/mainboard/portwell/m107/spd/MICRON_MT41K512M16HA-125A.spd.hex M src/mainboard/portwell/m107/spd/SAMSUNG_K4B8G1646D-MYKO.spd.hex M src/mainboard/protectli/vault_bsw/romstage.c M src/mainboard/razer/blade_stealth_kbl/acpi/ec.asl M src/mainboard/roda/rk9/acpi/ec.asl M src/mainboard/roda/rk9/acpi/thermal.asl M src/northbridge/intel/haswell/northbridge.c M src/northbridge/intel/i945/Kconfig M src/northbridge/intel/ironlake/bootblock.c M src/northbridge/intel/sandybridge/raminit_common.c M src/security/intel/cbnt/logging.c M src/security/intel/stm/SmmStm.c M src/security/intel/txt/common.c M src/security/memory/memory_clear.c M src/security/tpm/tspi.h M src/security/tpm/tss/tcg-2.0/tss.c M src/security/tpm/tss/tcg-2.0/tss_marshaling.h 58 files changed, 64 insertions(+), 64 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/58081/1 diff --git a/src/mainboard/amd/bilby/devicetree.cb b/src/mainboard/amd/bilby/devicetree.cb index 6ecdaf4..c3ba99c 100644 --- a/src/mainboard/amd/bilby/devicetree.cb +++ b/src/mainboard/amd/bilby/devicetree.cb @@ -127,7 +127,7 @@ .flash_ch_en = 0, }" - # genral purpose PCIe clock output configuration + # general purpose PCIe clock output configuration register "gpp_clk_config[0]" = "GPP_CLK_OFF" register "gpp_clk_config[1]" = "GPP_CLK_OFF" register "gpp_clk_config[2]" = "GPP_CLK_REQ" diff --git a/src/mainboard/amd/mandolin/variants/cereme/devicetree.cb b/src/mainboard/amd/mandolin/variants/cereme/devicetree.cb index 6342c29..167c366 100644 --- a/src/mainboard/amd/mandolin/variants/cereme/devicetree.cb +++ b/src/mainboard/amd/mandolin/variants/cereme/devicetree.cb @@ -118,7 +118,7 @@ .flash_ch_en = 0, }" - # genral purpose PCIe clock output configuration + # general purpose PCIe clock output configuration register "gpp_clk_config[0]" = "GPP_CLK_REQ" register "gpp_clk_config[1]" = "GPP_CLK_REQ" register "gpp_clk_config[2]" = "GPP_CLK_REQ" diff --git a/src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb b/src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb index 035bb70..1bc5498 100644 --- a/src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb +++ b/src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb @@ -118,7 +118,7 @@ .flash_ch_en = 0, }" - # genral purpose PCIe clock output configuration + # general purpose PCIe clock output configuration register "gpp_clk_config[0]" = "GPP_CLK_REQ" register "gpp_clk_config[1]" = "GPP_CLK_REQ" register "gpp_clk_config[2]" = "GPP_CLK_REQ" diff --git a/src/mainboard/asrock/b75pro3-m/devicetree.cb b/src/mainboard/asrock/b75pro3-m/devicetree.cb index 83b6597..93d37dc 100644 --- a/src/mainboard/asrock/b75pro3-m/devicetree.cb +++ b/src/mainboard/asrock/b75pro3-m/devicetree.cb @@ -129,7 +129,7 @@ irq 0xe9 = 0x02 irq 0xf0 = 0x20 end - device pnp 2e.b off end # HWM, front pannel LED + device pnp 2e.b off end # HWM, front panel LED device pnp 2e.d on end # VID device pnp 2e.e off end # CIR WAKE-UP device pnp 2e.f on end # GPIO Push-Pull or Open-drain diff --git a/src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb b/src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb index a50c2ac..ff05030 100644 --- a/src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb +++ b/src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb @@ -105,7 +105,7 @@ irq 0xe9 = 0x02 irq 0xf0 = 0x20 end - device pnp 2e.b on # HWM, front pannel LED + device pnp 2e.b on # HWM, front panel LED io 0x60 = 0x290 io 0x62 = 0x200 irq 0x70 = 0 diff --git a/src/mainboard/asrock/g41c-gs/variants/g41c-gs/devicetree.cb b/src/mainboard/asrock/g41c-gs/variants/g41c-gs/devicetree.cb index 7ceefaa..89e6ebb 100644 --- a/src/mainboard/asrock/g41c-gs/variants/g41c-gs/devicetree.cb +++ b/src/mainboard/asrock/g41c-gs/variants/g41c-gs/devicetree.cb @@ -99,7 +99,7 @@ device pnp 2e.a on # ACPI irq 0xe4 = 0x10 # Power dram during s3 end - device pnp 2e.b on # HWM, front pannel LED + device pnp 2e.b on # HWM, front panel LED io 0x60 = 0x290 irq 0x70 = 0 end diff --git a/src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb b/src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb index e583f7f..c3c6b1b 100644 --- a/src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb +++ b/src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb @@ -100,7 +100,7 @@ device pnp 2e.a on # ACPI irq 0xe4 = 0x10 # Power dram during s3 end - device pnp 2e.b on # HWM, front pannel LED + device pnp 2e.b on # HWM, front panel LED io 0x60 = 0x290 irq 0x70 = 0 end diff --git a/src/mainboard/asus/p5qpl-am/variants/p5qpl-am/overridetree.cb b/src/mainboard/asus/p5qpl-am/variants/p5qpl-am/overridetree.cb index 48376ff..5efb749 100644 --- a/src/mainboard/asus/p5qpl-am/variants/p5qpl-am/overridetree.cb +++ b/src/mainboard/asus/p5qpl-am/variants/p5qpl-am/overridetree.cb @@ -34,7 +34,7 @@ irq 0x70 = 0 irq 0xe4 = 0x10 # VSBGATE# to power dram during S3 end - device pnp 2e.b on # HWM, front pannel LED + device pnp 2e.b on # HWM, front panel LED io 0x60 = 0x290 irq 0x70 = 0 end diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/early_init.c b/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/early_init.c index 78ad877..8653cec 100644 --- a/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/early_init.c +++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/early_init.c @@ -106,9 +106,9 @@ { 1, 0, 0x0080 }, /* USB3 front internal header */ { 1, 0, 0x0080 }, /* USB3 front internal header */ { 1, 1, 0x0080 }, /* USB3 ETH top connector */ - { 1, 1, 0x0080 }, /* USB3 ETH botton connector */ + { 1, 1, 0x0080 }, /* USB3 ETH bottom connector */ { 1, 2, 0x0080 }, /* USB2 PS2 top connector */ - { 1, 2, 0x0080 }, /* USB2 PS2 botton connector */ + { 1, 2, 0x0080 }, /* USB2 PS2 bottom connector */ { 1, 3, 0x0080 }, /* USB2 internal header (USB78) */ { 1, 3, 0x0080 }, /* USB2 internal header (USB78) */ { 1, 4, 0x0080 }, /* USB2 internal header (USB910) */ diff --git a/src/mainboard/emulation/qemu-armv7/memlayout.ld b/src/mainboard/emulation/qemu-armv7/memlayout.ld index 5f32d8b..387a667 100644 --- a/src/mainboard/emulation/qemu-armv7/memlayout.ld +++ b/src/mainboard/emulation/qemu-armv7/memlayout.ld @@ -18,7 +18,7 @@ * with -bios option which neatly puts coreboot into flash and so payloads * can find CBFS and we don't risk overwriting CBFS. * - * Prior to Jul 2014 qemu aliased 0 to begining of RAM instead of flash + * Prior to Jul 2014 qemu aliased 0 to beginning of RAM instead of flash * and -bios was unusable as $pc pointed to 0 which was zero-filled as a * workaround we suggested using -kernel but this still had all the issues * of having fake-ROM in RAM. In fact it was even worse as fake ROM ends diff --git a/src/mainboard/emulation/qemu-i440fx/fw_cfg_if.h b/src/mainboard/emulation/qemu-i440fx/fw_cfg_if.h index a239590..e972f54 100644 --- a/src/mainboard/emulation/qemu-i440fx/fw_cfg_if.h +++ b/src/mainboard/emulation/qemu-i440fx/fw_cfg_if.h @@ -2,7 +2,7 @@ /* * These are the qemu firmware config interface defines and structs. - * Copied over from qemu soure tree, + * Copied over from qemu source tree, * include/standard-headers/linux/qemu_fw_cfg.h and modified accordingly. */ #ifndef FW_CFG_IF_H diff --git a/src/mainboard/emulation/qemu-q35/bootblock.c b/src/mainboard/emulation/qemu-q35/bootblock.c index 4a9a52f..ec86c70a 100644 --- a/src/mainboard/emulation/qemu-q35/bootblock.c +++ b/src/mainboard/emulation/qemu-q35/bootblock.c @@ -16,7 +16,7 @@ * MCFG. This code also assumes that bootblock_northbridge_init() is * the first thing called in the non-asm boot block code. The final * assumption is that no assembly code is using the - * CONFIG(MMCONF_SUPPORT) option to do PCI config acceses. + * CONFIG(MMCONF_SUPPORT) option to do PCI config accesses. * * The PCIEXBAR is assumed to live in the memory mapped IO space under * 4GiB. diff --git a/src/mainboard/facebook/fbg1701/ramstage.c b/src/mainboard/facebook/fbg1701/ramstage.c index be99573..cdd34a4 100644 --- a/src/mainboard/facebook/fbg1701/ramstage.c +++ b/src/mainboard/facebook/fbg1701/ramstage.c @@ -181,7 +181,7 @@ {6, 0x68, {0x41, 0xC0, 0x30, 0x00, 0x00, 0x00} }, {6, 0x68, {0x10, 0x14, 0x03, 0x00, 0x00, 0x00} }, {6, 0x68, {0x10, 0x18, 0xFF, 0xFF, 0xFF, 0xFF} }, - /* Additional Settng for eDP */ + /* Additional Setting for eDP */ {3, 0x68, {0x80, 0x03, 0x41, 0x00, 0x00, 0x00} }, {3, 0x68, {0xB4, 0x00, 0x0D, 0x00, 0x00, 0x00} }, /* DPRX CAD Register Setting */ diff --git a/src/mainboard/facebook/fbg1701/spd/KINGSTON_B5116ECMDXGGB.spd.hex b/src/mainboard/facebook/fbg1701/spd/KINGSTON_B5116ECMDXGGB.spd.hex index c51a5b901..5a81678 100644 --- a/src/mainboard/facebook/fbg1701/spd/KINGSTON_B5116ECMDXGGB.spd.hex +++ b/src/mainboard/facebook/fbg1701/spd/KINGSTON_B5116ECMDXGGB.spd.hex @@ -39,7 +39,7 @@ # 4 SDRAM CHIP Density and Banks # bits[3:0]: 5 = 8 Gigabits Total SDRAM capacity per chip # bits[6:4]: 0 = 3 (8 banks) -# bits[7]: reserverd +# bits[7]: reserved 05 # 5 SDRAM Addressing diff --git a/src/mainboard/facebook/fbg1701/spd/MICRON_MT41K512M16HA-125A.spd.hex b/src/mainboard/facebook/fbg1701/spd/MICRON_MT41K512M16HA-125A.spd.hex index 5007a26..f0dc7fb 100644 --- a/src/mainboard/facebook/fbg1701/spd/MICRON_MT41K512M16HA-125A.spd.hex +++ b/src/mainboard/facebook/fbg1701/spd/MICRON_MT41K512M16HA-125A.spd.hex @@ -39,7 +39,7 @@ # 4 SDRAM CHIP Density and Banks # bits[3:0]: 5 = 8 Gigabits Total SDRAM capacity per chip # bits[6:4]: 0 = 3 (8 banks) -# bits[7]: reserverd +# bits[7]: reserved 05 # 5 SDRAM Addressing diff --git a/src/mainboard/facebook/fbg1701/spd/SAMSUNG_K4B8G1646D-MYKO.spd.hex b/src/mainboard/facebook/fbg1701/spd/SAMSUNG_K4B8G1646D-MYKO.spd.hex index c3b71d6..2a03e04 100644 --- a/src/mainboard/facebook/fbg1701/spd/SAMSUNG_K4B8G1646D-MYKO.spd.hex +++ b/src/mainboard/facebook/fbg1701/spd/SAMSUNG_K4B8G1646D-MYKO.spd.hex @@ -38,7 +38,7 @@ # 4 SDRAM CHIP Density and Banks # bits[3:0]: 4 = 4 Gigabits Total SDRAM capacity per chip # bits[6:4]: 0 = 3 (8 banks) -# bits[7]: reserverd +# bits[7]: reserved 04 # 5 SDRAM Addressing diff --git a/src/mainboard/google/daisy/mainboard.c b/src/mainboard/google/daisy/mainboard.c index 1df786d..8e2bbe8 100644 --- a/src/mainboard/google/daisy/mainboard.c +++ b/src/mainboard/google/daisy/mainboard.c @@ -202,7 +202,7 @@ static void gpio_init(void) { - /* Set up the I2C busses. */ + /* Set up the I2C buses. */ exynos_pinmux_i2c0(); exynos_pinmux_i2c1(); exynos_pinmux_i2c2(); @@ -222,7 +222,7 @@ gpio_direction_output(GPIO_X17, 1); gpio_direction_output(GPIO_X15, 1); - /* Set up the I2S busses. */ + /* Set up the I2S buses. */ exynos_pinmux_i2s0(); exynos_pinmux_i2s1(); } diff --git a/src/mainboard/google/foster/bct/jtag.cfg b/src/mainboard/google/foster/bct/jtag.cfg index e9bbd02..58186b2 100644 --- a/src/mainboard/google/foster/bct/jtag.cfg +++ b/src/mainboard/google/foster/bct/jtag.cfg @@ -1,5 +1,5 @@ # -# Set DebugCtrl to 1 to reenable Jtag +# Set DebugCtrl to 1 to re-enable Jtag # DebugCtrl = 0; # diff --git a/src/mainboard/google/gru/pwm_regulator.c b/src/mainboard/google/gru/pwm_regulator.c index 5dddab5..3aafa9e 100644 --- a/src/mainboard/google/gru/pwm_regulator.c +++ b/src/mainboard/google/gru/pwm_regulator.c @@ -60,7 +60,7 @@ void pwm_regulator_configure(enum pwm_regulator pwm, int millivolt) { int duty_ns, voltage_max, voltage_min; - int voltage = millivolt * 10; /* for higer calculation accuracy */ + int voltage = millivolt * 10; /* for higher calculation accuracy */ int pwm_number = pwm_enum_to_pwm_number[pwm]; voltage_min = pwm_design_voltage[pwm][0]; diff --git a/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb b/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb index 260e934..381cbaa 100644 --- a/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb @@ -80,7 +80,7 @@ register "i2c_pad_ctrl_rx_sel[2]" = "I2C_PAD_CTRL_RX_SEL_3_3V" # Audio/SAR register "i2c_pad_ctrl_rx_sel[3]" = "I2C_PAD_CTRL_RX_SEL_1_8V" # GSC - # genral purpose PCIe clock output configuration + # general purpose PCIe clock output configuration register "gpp_clk_config[0]" = "GPP_CLK_REQ" register "gpp_clk_config[1]" = "GPP_CLK_REQ" register "gpp_clk_config[2]" = "GPP_CLK_REQ" diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index f78d420..a84eabd 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -44,7 +44,7 @@ register "tcc_offset" = "10" # TCC of 90C # Unlock GPIO pads register "PchUnlockGpioPads" = "1" - # SD card WP pin confguration + # SD card WP pin configuration register "ScsSdCardWpPinEnabled" = "0" # NOTE: if any variant wants to override this value, use the same format diff --git a/src/mainboard/google/kahlee/mainboard.c b/src/mainboard/google/kahlee/mainboard.c index 59c4959..ffec6a5 100644 --- a/src/mainboard/google/kahlee/mainboard.c +++ b/src/mainboard/google/kahlee/mainboard.c @@ -117,7 +117,7 @@ gpios = variant_gpio_table(&num_gpios); gpio_configure_pads(gpios, num_gpios); - /* Initialize i2c busses that were not initialized in bootblock */ + /* Initialize i2c buses that were not initialized in bootblock */ i2c_soc_init(); /* Set GenIntDisable so that GPIO 90 is configured as a GPIO. */ diff --git a/src/mainboard/google/mistral/romstage.c b/src/mainboard/google/mistral/romstage.c index 1816daf..728487a 100644 --- a/src/mainboard/google/mistral/romstage.c +++ b/src/mainboard/google/mistral/romstage.c @@ -7,7 +7,7 @@ { /* * Do DWC3 core and phy reset. Kick these resets off early - * so they get atleast 1msec to settle. + * so they get at least 1msec to settle. */ reset_usb(HSUSB_HS_PORT_1); } diff --git a/src/mainboard/google/oak/mainboard.c b/src/mainboard/google/oak/mainboard.c index 0e9dc13..afbea9c 100644 --- a/src/mainboard/google/oak/mainboard.c +++ b/src/mainboard/google/oak/mainboard.c @@ -231,7 +231,7 @@ static void mainboard_init(struct device *dev) { /* TP_SHIFT_EN: Enables the level shifter for I2C bus 4 (TPAD), which - * also contains the PS8640 eDP brige and the USB hub. + * also contains the PS8640 eDP bridge and the USB hub. */ if (board_id() + CONFIG_BOARD_ID_ADJUSTMENT < 5) mt6391_gpio_output(MT6391_KP_ROW2, 1); diff --git a/src/mainboard/google/octopus/mainboard.c b/src/mainboard/google/octopus/mainboard.c index 65bf286..9ffd633 100644 --- a/src/mainboard/google/octopus/mainboard.c +++ b/src/mainboard/google/octopus/mainboard.c @@ -69,7 +69,7 @@ /* * Currently we only have the case of RT5682 as the second source. And * in case of Ampton which used RT5682 as the default source, it didn't - * provide override_table right now so it will be returned ealier since + * provide override_table right now so it will be returned earlier since * table above is NULL. */ if (ssfc_get_audio_codec() != SSFC_AUDIO_CODEC_RT5682) diff --git a/src/mainboard/google/octopus/variants/baseboard/gpio.c b/src/mainboard/google/octopus/variants/baseboard/gpio.c index 85b0cc0..6878cad 100644 --- a/src/mainboard/google/octopus/variants/baseboard/gpio.c +++ b/src/mainboard/google/octopus/variants/baseboard/gpio.c @@ -324,7 +324,7 @@ PAD_CFG_GPO(GPIO_164, 0, DEEP), /* WLAN_PE_RST */ /* - * ESPI_IO1 acts as ALERT# (which is open-drain) and requies a weak + * ESPI_IO1 acts as ALERT# (which is open-drain) and requires a weak * pull-up for proper operation. Since there is no external pull present * on this platform, configure an internal weak pull-up. */ diff --git a/src/mainboard/google/octopus/variants/yorp/gpio.c b/src/mainboard/google/octopus/variants/yorp/gpio.c index e6b8359..63763b3 100644 --- a/src/mainboard/google/octopus/variants/yorp/gpio.c +++ b/src/mainboard/google/octopus/variants/yorp/gpio.c @@ -25,7 +25,7 @@ PAD_CFG_GPO(GPIO_164, 0, DEEP), /* WLAN_PE_RST */ /* - * ESPI_IO1 acts as ALERT# (which is open-drain) and requies a weak + * ESPI_IO1 acts as ALERT# (which is open-drain) and requires a weak * pull-up for proper operation. Since there is no external pull present * on this platform, configure an internal weak pull-up. */ diff --git a/src/mainboard/google/peach_pit/mainboard.c b/src/mainboard/google/peach_pit/mainboard.c index c279777..9cefb81 100644 --- a/src/mainboard/google/peach_pit/mainboard.c +++ b/src/mainboard/google/peach_pit/mainboard.c @@ -330,7 +330,7 @@ static void gpio_init(void) { - /* Set up the I2C busses. */ + /* Set up the I2C buses. */ exynos_pinmux_i2c2(); exynos_pinmux_i2c4(); exynos_pinmux_i2c7(); diff --git a/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/camera_pmic.asl b/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/camera_pmic.asl index 4b1254d..d588d57 100644 --- a/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/camera_pmic.asl +++ b/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/camera_pmic.asl @@ -262,7 +262,7 @@ * AX1V: Auxiliary LDO1 VR voltage value * AX2V: Auxiliary LDO2 VR voltage value * ACVA: Analog LDO VR voltage - * DCVA: Core buck VR volatage + * DCVA: Core buck VR voltage */ OperationRegion (PWR2, 0xB1, Zero, 0x0100) Field (PWR2, DWordAcc, NoLock, Preserve) diff --git a/src/mainboard/google/smaug/bct/jtag.cfg b/src/mainboard/google/smaug/bct/jtag.cfg index 4f2c36c..c48e54a 100644 --- a/src/mainboard/google/smaug/bct/jtag.cfg +++ b/src/mainboard/google/smaug/bct/jtag.cfg @@ -1,5 +1,5 @@ # -# Set JtagCtrl to 1 to reenable Jtag +# Set JtagCtrl to 1 to re-enable Jtag # JtagCtrl = 0; # diff --git a/src/mainboard/google/stout/dsdt.asl b/src/mainboard/google/stout/dsdt.asl index 8e2d859..89958c9 100644 --- a/src/mainboard/google/stout/dsdt.asl +++ b/src/mainboard/google/stout/dsdt.asl @@ -17,7 +17,7 @@ #include "acpi/platform.asl" #include "acpi/mainboard.asl" - // Thermal handeler + // Thermal handler #include "acpi/thermal.asl" // global NVS and variables diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb b/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb index 9476723..68eb6ea 100644 --- a/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb +++ b/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb @@ -21,7 +21,7 @@ }" # Start : OPN Performance Configuration - # (Configuratin that is common for all variants) + # (Configuration that is common for all variants) # For the below fields, 0 indicates use SOC default # PROCHOT_L de-assertion Ramp Time @@ -232,7 +232,7 @@ register "i2c_scl_reset" = "GPIO_I2C2_SCL | GPIO_I2C3_SCL" - # genral purpose PCIe clock output configuration + # general purpose PCIe clock output configuration register "gpp_clk_config[0]" = "GPP_CLK_REQ" # WLAN register "gpp_clk_config[1]" = "GPP_CLK_REQ" # SD Reader register "gpp_clk_config[2]" = "GPP_CLK_REQ" # NVME SSD diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb b/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb index ce01215..4bb42de 100644 --- a/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb +++ b/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb @@ -19,7 +19,7 @@ }" # Start : OPN Performance Configuration - # (Configuratin that is common for all variants) + # (Configuration that is common for all variants) # For the below fields, 0 indicates use SOC default # PROCHOT_L de-assertion Ramp Time @@ -230,7 +230,7 @@ register "i2c_scl_reset" = "GPIO_I2C2_SCL | GPIO_I2C3_SCL" - # genral purpose PCIe clock output configuration + # general purpose PCIe clock output configuration register "gpp_clk_config[0]" = "GPP_CLK_REQ" # WLAN register "gpp_clk_config[1]" = "GPP_CLK_REQ" # SD Reader register "gpp_clk_config[2]" = "GPP_CLK_OFF" diff --git a/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h index 43ae715..3f7e5d1 100644 --- a/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h @@ -49,7 +49,7 @@ void variant_pcie_gpio_configure(void); /* Per variant FSP-S initialization, default implementation in baseboard and - * overrideable by the variant. */ + * overridable by the variant. */ void variant_get_dxio_ddi_descriptors(const fsp_dxio_descriptor **dxio_descs, size_t *dxio_num, const fsp_ddi_descriptor **ddi_descs, diff --git a/src/mainboard/intel/dcp847ske/devicetree.cb b/src/mainboard/intel/dcp847ske/devicetree.cb index 389b44e..f7821d0 100644 --- a/src/mainboard/intel/dcp847ske/devicetree.cb +++ b/src/mainboard/intel/dcp847ske/devicetree.cb @@ -81,7 +81,7 @@ device pnp 4e.609 off end # GPIO6 device pnp 4e.709 off end # GPIO7 device pnp 4e.a on end # ACPI - device pnp 4e.b on # HWM, front pannel LED + device pnp 4e.b on # HWM, front panel LED io 0x60 = 0xa30 io 0x62 = 0 # unused end diff --git a/src/mainboard/intel/dg41wv/devicetree.cb b/src/mainboard/intel/dg41wv/devicetree.cb index 9b1aeb0..5f945c1 100644 --- a/src/mainboard/intel/dg41wv/devicetree.cb +++ b/src/mainboard/intel/dg41wv/devicetree.cb @@ -129,7 +129,7 @@ irq 0xe4 = 0x10 # Power dram during s3 irq 0xe6 = 0x8c end - device pnp 2e.b on # HWM, front pannel LED + device pnp 2e.b on # HWM, front panel LED io 0x60 = 0xa00 irq 0x70 = 0 end diff --git a/src/mainboard/intel/kblrvp/acpi/mipi_camera.asl b/src/mainboard/intel/kblrvp/acpi/mipi_camera.asl index 26108a2..0d1158d 100644 --- a/src/mainboard/intel/kblrvp/acpi/mipi_camera.asl +++ b/src/mainboard/intel/kblrvp/acpi/mipi_camera.asl @@ -108,7 +108,7 @@ * AX1V: Auxiliary LDO1 VR voltage value * AX2V: Auxiliary LDO2 VR voltage value * ACVA: Analog LDO VR voltage - * DCVA: Core buck VR volatage + * DCVA: Core buck VR voltage */ OperationRegion (PWR2, 0xB1, Zero, 0x0100) Field (PWR2, DWordAcc, NoLock, Preserve) @@ -613,7 +613,7 @@ * AX1V: Auxiliary LDO1 VR voltage value * AX2V: Auxiliary LDO2 VR voltage value * ACVA: Analog LDO VR voltage - * DCVA: Core buck VR volatage + * DCVA: Core buck VR voltage */ OperationRegion (PWR2, 0xB1, Zero, 0x0100) Field (PWR2, DWordAcc, NoLock, Preserve) diff --git a/src/mainboard/jetway/nf81-t56n-lf/OemCustomize.c b/src/mainboard/jetway/nf81-t56n-lf/OemCustomize.c index 4d4b578..3f420c0 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/OemCustomize.c +++ b/src/mainboard/jetway/nf81-t56n-lf/OemCustomize.c @@ -104,7 +104,7 @@ } /** - * @brief Customer Overides Memory Table + * @brief Customer Overrides Memory Table * * Platform Specific Overriding Table allows IBV/OEM to pass in platform * information to AGESA diff --git a/src/mainboard/lenovo/s230u/acpi/ec.asl b/src/mainboard/lenovo/s230u/acpi/ec.asl index 7365d74..22c88e0 100644 --- a/src/mainboard/lenovo/s230u/acpi/ec.asl +++ b/src/mainboard/lenovo/s230u/acpi/ec.asl @@ -144,7 +144,7 @@ ^HKEY.MHKQ (0x6040) } - /* Lid openend */ + /* Lid opened */ Method (_Q2A, 0, NotSerialized) { LIDS = 1 diff --git a/src/mainboard/lippert/frontrunner-af/dsdt.asl b/src/mainboard/lippert/frontrunner-af/dsdt.asl index 5d1e261..e35a70b 100644 --- a/src/mainboard/lippert/frontrunner-af/dsdt.asl +++ b/src/mainboard/lippert/frontrunner-af/dsdt.asl @@ -535,7 +535,7 @@ * The Secondary bus range for PCI0 lets the system * know what bus values are allowed on the downstream * side of this PCI bus if there is a PCI-PCI bridge. - * PCI busses can have 256 secondary busses which + * PCI buses can have 256 secondary buses which * range from [0-0xFF] but they do not need to be * sequential. */ diff --git a/src/mainboard/portwell/m107/spd/KINGSTON_B5116ECMDXGGB.spd.hex b/src/mainboard/portwell/m107/spd/KINGSTON_B5116ECMDXGGB.spd.hex index c51a5b901..5a81678 100644 --- a/src/mainboard/portwell/m107/spd/KINGSTON_B5116ECMDXGGB.spd.hex +++ b/src/mainboard/portwell/m107/spd/KINGSTON_B5116ECMDXGGB.spd.hex @@ -39,7 +39,7 @@ # 4 SDRAM CHIP Density and Banks # bits[3:0]: 5 = 8 Gigabits Total SDRAM capacity per chip # bits[6:4]: 0 = 3 (8 banks) -# bits[7]: reserverd +# bits[7]: reserved 05 # 5 SDRAM Addressing diff --git a/src/mainboard/portwell/m107/spd/MICRON_MT41K512M16HA-125A.spd.hex b/src/mainboard/portwell/m107/spd/MICRON_MT41K512M16HA-125A.spd.hex index 5007a26..f0dc7fb 100644 --- a/src/mainboard/portwell/m107/spd/MICRON_MT41K512M16HA-125A.spd.hex +++ b/src/mainboard/portwell/m107/spd/MICRON_MT41K512M16HA-125A.spd.hex @@ -39,7 +39,7 @@ # 4 SDRAM CHIP Density and Banks # bits[3:0]: 5 = 8 Gigabits Total SDRAM capacity per chip # bits[6:4]: 0 = 3 (8 banks) -# bits[7]: reserverd +# bits[7]: reserved 05 # 5 SDRAM Addressing diff --git a/src/mainboard/portwell/m107/spd/SAMSUNG_K4B8G1646D-MYKO.spd.hex b/src/mainboard/portwell/m107/spd/SAMSUNG_K4B8G1646D-MYKO.spd.hex index c3b71d6..2a03e04 100644 --- a/src/mainboard/portwell/m107/spd/SAMSUNG_K4B8G1646D-MYKO.spd.hex +++ b/src/mainboard/portwell/m107/spd/SAMSUNG_K4B8G1646D-MYKO.spd.hex @@ -38,7 +38,7 @@ # 4 SDRAM CHIP Density and Banks # bits[3:0]: 4 = 4 Gigabits Total SDRAM capacity per chip # bits[6:4]: 0 = 3 (8 banks) -# bits[7]: reserverd +# bits[7]: reserved 04 # 5 SDRAM Addressing diff --git a/src/mainboard/protectli/vault_bsw/romstage.c b/src/mainboard/protectli/vault_bsw/romstage.c index 0745352..33519b9 100644 --- a/src/mainboard/protectli/vault_bsw/romstage.c +++ b/src/mainboard/protectli/vault_bsw/romstage.c @@ -12,7 +12,7 @@ void mainboard_after_memory_init(void) { /* - * FSP enables internal UART. Disable it and reenable Super I/O UART to + * FSP enables internal UART. Disable it and re-enable Super I/O UART to * prevent loss of debug information on serial. */ pci_write_config32(PCI_DEV(0, LPC_DEV, 0), UART_CONT, (u32) 0); diff --git a/src/mainboard/razer/blade_stealth_kbl/acpi/ec.asl b/src/mainboard/razer/blade_stealth_kbl/acpi/ec.asl index 72eaca4..7325562 100644 --- a/src/mainboard/razer/blade_stealth_kbl/acpi/ec.asl +++ b/src/mainboard/razer/blade_stealth_kbl/acpi/ec.asl @@ -32,7 +32,7 @@ BIF0, 16, BDCP, 16, // BAT Design Capacity BFCP, 16, // BAT Full Capacity - BRCH, 16, // BAT Rechargable + BRCH, 16, // BAT Rechargeable BDVT, 16, // BAT Design Voltage BIF5, 16, BIF6, 16, diff --git a/src/mainboard/roda/rk9/acpi/ec.asl b/src/mainboard/roda/rk9/acpi/ec.asl index 720f92f..fbe4173 100644 --- a/src/mainboard/roda/rk9/acpi/ec.asl +++ b/src/mainboard/roda/rk9/acpi/ec.asl @@ -42,7 +42,7 @@ FDDI, 1, // floppy on lpt indicator? LIDC, 1, // LID switch Offset(0xd0), - TCPU, 8, // T_CPU in deg Celcius + TCPU, 8, // T_CPU in deg Celsius Offset(0xd6), /* exact purpose of these three is guessed, but it's something about cooling */ diff --git a/src/mainboard/roda/rk9/acpi/thermal.asl b/src/mainboard/roda/rk9/acpi/thermal.asl index 907edc1..5c29846 100644 --- a/src/mainboard/roda/rk9/acpi/thermal.asl +++ b/src/mainboard/roda/rk9/acpi/thermal.asl @@ -4,7 +4,7 @@ Scope (\_TZ) { - /* degree Celcius to deci-Kelvin (ACPI temperature unit) */ + /* degree Celsius to deci-Kelvin (ACPI temperature unit) */ Method(C2dK, 1) { Add (2732, Multiply (Arg0, 10), Local0) Return (Local0) diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index 02799d3..2322097 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -35,7 +35,7 @@ } /* - * TODO: We could determine how many PCIe busses we need in the bar. + * TODO: We could determine how many PCIe buses we need in the bar. * For now, that number is hardcoded to a max of 64. */ static struct device_operations pci_domain_ops = { diff --git a/src/northbridge/intel/i945/Kconfig b/src/northbridge/intel/i945/Kconfig index 51ee320..ac19fcc 100644 --- a/src/northbridge/intel/i945/Kconfig +++ b/src/northbridge/intel/i945/Kconfig @@ -63,7 +63,7 @@ config CHECK_SLFRCS_ON_RESUME def_bool n help - On some boards it may be neccessary to hard reset early + On some boards it may be necessary to hard reset early during resume from S3 if the SLFRCS register indicates that a memory channel is not guaranteed to be in self-refresh. On other boards the check always creates a false positive, diff --git a/src/northbridge/intel/ironlake/bootblock.c b/src/northbridge/intel/ironlake/bootblock.c index 6610a3e..241eb43 100644 --- a/src/northbridge/intel/ironlake/bootblock.c +++ b/src/northbridge/intel/ironlake/bootblock.c @@ -22,7 +22,7 @@ { /* * The QuickPath bus number is the topmost bus number, as per the value - * of the SAD_PCIEXBAR register. The register defaults to 256 busses on + * of the SAD_PCIEXBAR register. The register defaults to 256 buses on * reset. Thus, hardcode the bus number when first setting up PCIEXBAR. */ const pci_devfn_t qpi_sad = PCI_DEV(255, 0, 1); diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 4b5f2b3..9ef491b 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -2437,7 +2437,7 @@ if (enable_iosav_opt) mchbar_write32(MCMNTS_SPARE, 1); - printram("Aggresive write training:\n"); + printram("Aggressive write training:\n"); for (i = 0; i < ARRAY_SIZE(wr_vref_offsets); i++) { FOR_ALL_POPULATED_CHANNELS { diff --git a/src/security/intel/cbnt/logging.c b/src/security/intel/cbnt/logging.c index 55354b4..514e5ac 100644 --- a/src/security/intel/cbnt/logging.c +++ b/src/security/intel/cbnt/logging.c @@ -123,7 +123,7 @@ LOG("SACM INFO MSR (0x13A) raw: 0x%016llx\n", acm_info.raw); LOG(" NEM status: %u\n", acm_info.nem_enabled); LOG(" TPM type: %s\n", tpm_type[acm_info.tpm_type]); - LOG(" TPM succes: %u\n", acm_info.tpm_success); + LOG(" TPM success: %u\n", acm_info.tpm_success); LOG(" FACB: %u\n", acm_info.facb); LOG(" measured boot: %u\n", acm_info.measured_boot); LOG(" verified boot: %u\n", acm_info.verified_boot); diff --git a/src/security/intel/stm/SmmStm.c b/src/security/intel/stm/SmmStm.c index e2fab0c..1ebe77d 100644 --- a/src/security/intel/stm/SmmStm.c +++ b/src/security/intel/stm/SmmStm.c @@ -668,7 +668,7 @@ /* * This function return BIOS STM resource. * Produced by SmmStm. - * Comsumed by SmmMpService when Init. + * Consumed by SmmMpService when Init. * * @return BIOS STM resource */ diff --git a/src/security/intel/txt/common.c b/src/security/intel/txt/common.c index 2b7d926..e3e2f5c 100644 --- a/src/security/intel/txt/common.c +++ b/src/security/intel/txt/common.c @@ -150,7 +150,7 @@ } /** - * Validate that the provided ACM is useable on this platform. + * Validate that the provided ACM is usable on this platform. */ static int validate_acm(const void *ptr) { diff --git a/src/security/memory/memory_clear.c b/src/security/memory/memory_clear.c index 557125d..03c6f8b 100644 --- a/src/security/memory/memory_clear.c +++ b/src/security/memory/memory_clear.c @@ -98,7 +98,7 @@ __func__, (void *)pgtbl, (void *)vmem_addr); } - /* Now clear all useable DRAM */ + /* Now clear all usable DRAM */ memranges_each_entry(r, &mem) { if (range_entry_tag(r) != BM_MEM_RAM) continue; diff --git a/src/security/tpm/tspi.h b/src/security/tpm/tspi.h index e040d80..ed642c3 100644 --- a/src/security/tpm/tspi.h +++ b/src/security/tpm/tspi.h @@ -55,7 +55,7 @@ const char *name); /** - * Issue a TPM_Clear and reenable/reactivate the TPM. + * Issue a TPM_Clear and re-enable/reactivate the TPM. * @return TPM_SUCCESS on success. If not a tpm error is returned */ uint32_t tpm_clear_and_reenable(void); diff --git a/src/security/tpm/tss/tcg-2.0/tss.c b/src/security/tpm/tss/tcg-2.0/tss.c index f464fe1..cfa533b 100644 --- a/src/security/tpm/tss/tcg-2.0/tss.c +++ b/src/security/tpm/tss/tcg-2.0/tss.c @@ -273,7 +273,7 @@ uint32_t tlcl_lock_nv_write(uint32_t index) { struct tpm2_response *response; - /* TPM Wll reject attempts to write at non-defined index. */ + /* TPM Will reject attempts to write at non-defined index. */ struct tpm2_nv_write_lock_cmd nv_wl = { .nvIndex = HR_NV_INDEX + index, }; @@ -372,7 +372,7 @@ if (!response) return TPM_E_NO_DEVICE; - /* Map TPM2 retrun codes into common vboot represenation. */ + /* Map TPM2 return codes into common vboot representation. */ switch (response->hdr.tpm_code) { case TPM2_RC_SUCCESS: return TPM_SUCCESS; diff --git a/src/security/tpm/tss/tcg-2.0/tss_marshaling.h b/src/security/tpm/tss/tcg-2.0/tss_marshaling.h index ae0b7fd..3ae48eb 100644 --- a/src/security/tpm/tss/tcg-2.0/tss_marshaling.h +++ b/src/security/tpm/tss/tcg-2.0/tss_marshaling.h @@ -28,7 +28,7 @@ * tpm_unmarshal_response * * Given a buffer received from the TPM in response to a certain command, - * deserialize the buffer into the expeced response structure. + * deserialize the buffer into the expected response structure. * * struct tpm2_response is a union of all possible responses. * -- To view, visit https://review.coreboot.org/c/coreboot/+/58081 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie34003a9fdfe9f3b1b8ec0789aeca8b9435c9c79 Gerrit-Change-Number: 58081 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: coreboot tables: Add type-c port info to coreboot table
by Nick Vaccaro (Code Review) 01 Oct '21

01 Oct '21

Attention is currently required from: Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Nick Vaccaro. Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57069 ) Change subject: coreboot tables: Add type-c port info to coreboot table ...................................................................... Patch Set 29: (4 comments) File payloads/libpayload/include/coreboot_tables.h: https://review.coreboot.org/c/coreboot/+/57069/comment/b2f0221a_6a748894 PS26, Line 173: struct cb_type_c_info { > This is not needed as well. Done File payloads/libpayload/include/sysinfo.h: https://review.coreboot.org/c/coreboot/+/57069/comment/8af9f7f6_98ddb5cb PS26, Line 153: typec_orientation > type_c_orientation. […] Done File payloads/libpayload/libc/coreboot.c: https://review.coreboot.org/c/coreboot/+/57069/comment/467fe689_3405f070 PS26, Line 251: get_cbmem_addr > (void *) Done File src/commonlib/include/commonlib/coreboot_tables.h: https://review.coreboot.org/c/coreboot/+/57069/comment/842e85dc_7428d8ad PS27, Line 431: enum type_c_orientation { > You will have to pull in the change to src/drivers/intel/pmc_mux/conn/chip. […] I would also have to bring in a change to conn.c as well. To avoid that, I removed the add of enum of type_c_orientation from this CL and added the change to move and convert the enum typec_orientation into the connector CL. Is that ok, or is it better to bring in two changes from driver in this CL instead? -- To view, visit https://review.coreboot.org/c/coreboot/+/57069 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ice732be2fa634dbf31ec620552b383c4a5b41451 Gerrit-Change-Number: 57069 Gerrit-PatchSet: 29 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Fri, 01 Oct 2021 20:33:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: src/acpi to src/lib: Fix spelling errors.
by build bot (Jenkins) (Code Review) 01 Oct '21

01 Oct '21

Attention is currently required from: Lance Zhao, Philipp Hug, Tim Wawrzynczak, Christian Walter, Julius Werner, Ron Minnich. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58080 ) Change subject: src/acpi to src/lib: Fix spelling errors. ...................................................................... Patch Set 1: (1 comment) File src/device/oprom/x86emu/prim_ops.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-129632): https://review.coreboot.org/c/coreboot/+/58080/comment/d5a6793b_5d272ada PS1, Line 2461: * will only support up to feature 1, which we set in register EAX. code indent should use tabs where possible -- To view, visit https://review.coreboot.org/c/coreboot/+/58080 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5b8ecdfe75d99028fee820a2034466a8ad1c5e63 Gerrit-Change-Number: 58080 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Ron Minnich <rminnich(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Lance Zhao Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Ron Minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Fri, 01 Oct 2021 20:32:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: coreboot tables: Add type-c port info to coreboot table
by Nick Vaccaro (Code Review) 01 Oct '21

01 Oct '21

Attention is currently required from: Nico Huber, Furquan Shaikh, Tim Wawrzynczak. Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Zhuohao Lee, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/57069 to look at the new patch set (#30). Change subject: coreboot tables: Add type-c port info to coreboot table ...................................................................... coreboot tables: Add type-c port info to coreboot table This change adds type-c port information for USB Type-C ports to the coreboot table. This allows depthcharge to know the usb2 and usb3 port number assignments for each available port, as well as the SBU and data line orientation for the board. BUG=b:149830546 TEST='emerge-volteer coreboot chromeos-bootimage' and verify it builds successfully. Cherry-pick CL to enable this feature for volteer, flash and boot volteer2 to kernel, log in and check cbmem for type-c info exported to the payload: localhost ~ # cbmem -c | grep type-c added type-c port0 info to cbmem: usb2:9 usb3:1 sbu:0 data:0 added type-c port1 info to cbmem: usb2:4 usb3:2 sbu:1 data:0 Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com> Change-Id: Ice732be2fa634dbf31ec620552b383c4a5b41451 --- M payloads/libpayload/include/coreboot_tables.h M payloads/libpayload/include/sysinfo.h M payloads/libpayload/libc/coreboot.c M src/commonlib/include/commonlib/cbmem_id.h M src/commonlib/include/commonlib/coreboot_tables.h M src/lib/coreboot_table.c 6 files changed, 54 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/57069/30 -- To view, visit https://review.coreboot.org/c/coreboot/+/57069 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ice732be2fa634dbf31ec620552b383c4a5b41451 Gerrit-Change-Number: 57069 Gerrit-PatchSet: 30 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel: deduplicate acpi_fill_soc_wake
by Michael Niewöhner (Code Review) 01 Oct '21

01 Oct '21

Attention is currently required from: Felix Singer, Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Paul Menzel, Duncan Laurie, Angel Pons, Andrey Petrov, Kyösti Mälkki, Patrick Rudolph. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58043 ) Change subject: soc/intel: deduplicate acpi_fill_soc_wake ...................................................................... Patch Set 2: (1 comment) File src/soc/intel/common/block/acpi/acpi.c: https://review.coreboot.org/c/coreboot/+/58043/comment/77d8afb1_0cf9f2ce PS1, Line 220: RTC_EN > Separate change? Yes, sure, but I'm unsure if it should be dropped or not -- To view, visit https://review.coreboot.org/c/coreboot/+/58043 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I06628aeb5b82b30142a383b87c82a1e22a073ef5 Gerrit-Change-Number: 58043 Gerrit-PatchSet: 2 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Duncan Laurie Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Duncan Laurie Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 01 Oct 2021 20:32:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/skylake: switch to common ACPI code
by Michael Niewöhner (Code Review) 01 Oct '21

01 Oct '21

Attention is currently required from: Felix Singer, Tim Crawford, Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Matt DeVillier, Paul Menzel, Angel Pons, Subrata Banik, Arthur Heymans, Patrick Rudolph, Aaron Durbin. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44138 ) Change subject: soc/intel/skylake: switch to common ACPI code ...................................................................... Patch Set 14: (1 comment) This change is ready for review. Patchset: PS14: Testers welcome! -- To view, visit https://review.coreboot.org/c/coreboot/+/44138 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1ec804ae4006a2d9b69c0d93a658eb3b84d60b40 Gerrit-Change-Number: 44138 Gerrit-PatchSet: 14 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Comment-Date: Fri, 01 Oct 2021 20:29:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common: add possiblity to override GPE0 to acpi_fill_soc_wake
by Michael Niewöhner (Code Review) 01 Oct '21

01 Oct '21

Attention is currently required from: Felix Singer, Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Matt DeVillier, Paul Menzel, Angel Pons, Subrata Banik, Arthur Heymans, Patrick Rudolph, Aaron Durbin. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58071 ) Change subject: soc/intel/common: add possiblity to override GPE0 to acpi_fill_soc_wake ...................................................................... Patch Set 6: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/58071 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If9f28cf054ae8b602c0587e4dd4a13a4aba810c7 Gerrit-Change-Number: 58071 Gerrit-PatchSet: 6 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Comment-Date: Fri, 01 Oct 2021 20:29:10 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: src/acpi to src/lib: Fix spelling errors.
by Martin Roth (Code Review) 01 Oct '21

01 Oct '21

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58080 ) Change subject: src/acpi to src/lib: Fix spelling errors. ...................................................................... src/acpi to src/lib: Fix spelling errors. These issues were found and fixed by codespell, a useful tool for finding spelling errors. Signed-off-by: Martin Roth <martin(a)coreboot.org> Change-Id: I5b8ecdfe75d99028fee820a2034466a8ad1c5e63 --- M src/acpi/acpi.c M src/acpi/device.c M src/arch/arm/armv7/cpu.S M src/arch/arm64/include/arch/asm.h M src/arch/riscv/fit_payload.c M src/arch/riscv/opensbi.c M src/arch/x86/c_start.S M src/commonlib/bsd/include/commonlib/bsd/compiler.h M src/commonlib/include/commonlib/iobuf.h M src/console/Kconfig M src/cpu/x86/64bit/exit32.inc M src/cpu/x86/pae/pgtbl.c M src/cpu/x86/sipi_vector.S M src/device/Kconfig M src/device/azalia_device.c M src/device/dram/ddr4.c M src/device/oprom/include/x86emu/regs.h M src/device/oprom/x86emu/LICENSE M src/device/oprom/x86emu/prim_ops.c M src/device/pci_early.c M src/device/pnp_device.c M src/device/resource_allocator_v4.c M src/drivers/amd/agesa/cache_as_ram.S M src/drivers/crb/tpm.c M src/drivers/generic/gpio_keys/chip.h M src/drivers/i2c/lm96000/chip.h M src/drivers/i2c/nct7802y/chip.h M src/drivers/i2c/tpm/cr50.c M src/drivers/i2c/tpm/tpm.c M src/drivers/i2c/ww_ring/ww_ring_programs.c M src/drivers/i2c/ww_ring/ww_ring_programs.h M src/drivers/ipmi/ipmi_fru.c M src/drivers/ipmi/supermicro_oem.c M src/drivers/net/Kconfig M src/drivers/net/atl1e.c M src/drivers/net/r8168.c M src/drivers/spi/spi_sdcard.c M src/drivers/spi/tpm/tpm.c M src/ec/compal/ene932/acpi/ec.asl M src/ec/google/chromeec/ec.h M src/ec/google/chromeec/ec_commands.h M src/ec/google/wilco/commands.h M src/ec/quanta/ene_kb3940q/acpi/ec.asl M src/ec/quanta/it8518/acpi/battery.asl M src/ec/quanta/it8518/acpi/ec.asl M src/include/acpi/acpi.h M src/include/cpu/x86/save_state.h M src/include/device/i2c_simple.h M src/lib/device_tree.c M src/lib/edid.c M src/lib/nhlt.c M src/lib/region_file.c 52 files changed, 68 insertions(+), 68 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/58080/1 diff --git a/src/acpi/acpi.c b/src/acpi/acpi.c index 2e15ea9..6417ef8 100644 --- a/src/acpi/acpi.c +++ b/src/acpi/acpi.c @@ -1937,15 +1937,15 @@ return 2; case TPM2: return 4; - case SSDT: /* ACPI 3.0 upto 6.3: 2 */ + case SSDT: /* ACPI 3.0 up to 6.3: 2 */ return 2; - case SRAT: /* ACPI 2.0: 1, ACPI 3.0: 2, ACPI 4.0 upto 6.3: 3 */ + case SRAT: /* ACPI 2.0: 1, ACPI 3.0: 2, ACPI 4.0 up to 6.3: 3 */ return 1; /* TODO Should probably be upgraded to 2 */ case HMAT: /* ACPI 6.4: 2 */ return 2; case DMAR: return 1; - case SLIT: /* ACPI 2.0 upto 6.3: 1 */ + case SLIT: /* ACPI 2.0 up to 6.3: 1 */ return 1; case SPMI: /* IMPI 2.0 */ return 5; @@ -1957,13 +1957,13 @@ return IVRS_FORMAT_MIXED; case DBG2: return 0; - case FACS: /* ACPI 2.0/3.0: 1, ACPI 4.0 upto 6.3: 2 */ + case FACS: /* ACPI 2.0/3.0: 1, ACPI 4.0 up to 6.3: 2 */ return 1; - case RSDT: /* ACPI 1.0 upto 6.3: 1 */ + case RSDT: /* ACPI 1.0 up to 6.3: 1 */ return 1; - case XSDT: /* ACPI 2.0 upto 6.3: 1 */ + case XSDT: /* ACPI 2.0 up to 6.3: 1 */ return 1; - case RSDP: /* ACPI 2.0 upto 6.3: 2 */ + case RSDP: /* ACPI 2.0 up to 6.3: 2 */ return 2; case EINJ: return 1; diff --git a/src/acpi/device.c b/src/acpi/device.c index 4b59990..1df179b 100644 --- a/src/acpi/device.c +++ b/src/acpi/device.c @@ -139,7 +139,7 @@ /* * Warning: just as with dev_path() this uses a static buffer - * so should not be called mulitple times in one statement + * so should not be called multiple times in one statement */ const char *acpi_device_path(const struct device *dev) { diff --git a/src/arch/arm/armv7/cpu.S b/src/arch/arm/armv7/cpu.S index c53119c..bc3ebd9 100644 --- a/src/arch/arm/armv7/cpu.S +++ b/src/arch/arm/armv7/cpu.S @@ -16,7 +16,7 @@ * the LSB of the set field, but the latter contains the LSB of the way field * minus the highest valid set field... such that when you subtract it from a * [way:0:level] field you end up with a [way - 1:highest_set:level] field - * through the magic of double subtraction. It's quite ingenius, really. + * through the magic of double subtraction. It's quite ingenious, really. * Takes care to only use r0-r3 and ip so it's pefectly ABI-compatible without * needing to write to memory. * diff --git a/src/arch/arm64/include/arch/asm.h b/src/arch/arm64/include/arch/asm.h index e6246c3..df5952a 100644 --- a/src/arch/arm64/include/arch/asm.h +++ b/src/arch/arm64/include/arch/asm.h @@ -19,7 +19,7 @@ .size name, .-name /* - * Certain SoCs have an alignment requiremnt for the CPU reset vector. + * Certain SoCs have an alignment requirement for the CPU reset vector. * Align to a 64 byte typical cacheline for now. */ #define CPU_RESET_ENTRY(name) ENTRY_WITH_ALIGN(name, 6) diff --git a/src/arch/riscv/fit_payload.c b/src/arch/riscv/fit_payload.c index abce57e..f7f4106 100644 --- a/src/arch/riscv/fit_payload.c +++ b/src/arch/riscv/fit_payload.c @@ -7,7 +7,7 @@ #include <fit.h> #include <endian.h> -/* Implements a Berkley Boot Loader (BBL) compatible payload loading */ +/* Implements a Berkeley Boot Loader (BBL) compatible payload loading */ #define MAX_KERNEL_SIZE (64*MiB) diff --git a/src/arch/riscv/opensbi.c b/src/arch/riscv/opensbi.c index e719560..3a738ec 100644 --- a/src/arch/riscv/opensbi.c +++ b/src/arch/riscv/opensbi.c @@ -2,7 +2,7 @@ #include <sbi/fw_dynamic.h> #include <arch/boot.h> -/* DO NOT INLCUDE COREBOOT HEADERS HERE */ +/* DO NOT INCLUDE COREBOOT HEADERS HERE */ void run_opensbi(const int hart_id, const void *fdt, diff --git a/src/arch/x86/c_start.S b/src/arch/x86/c_start.S index a4a7b28..cb7d504 100644 --- a/src/arch/x86/c_start.S +++ b/src/arch/x86/c_start.S @@ -217,7 +217,7 @@ # use iret to jump to a 64-bit offset in a new code segment # iret will pop cs:rip, flags, then ss:rsp mov %ss, %ax # need to push ss.. - push %rax # push ss instuction not valid in x64 mode, + push %rax # push ss instruction not valid in x64 mode, # so use ax push %rsp pushfq diff --git a/src/commonlib/bsd/include/commonlib/bsd/compiler.h b/src/commonlib/bsd/include/commonlib/bsd/compiler.h index ee2ff88..4dd09bc 100644 --- a/src/commonlib/bsd/include/commonlib/bsd/compiler.h +++ b/src/commonlib/bsd/include/commonlib/bsd/compiler.h @@ -36,7 +36,7 @@ #endif /* This evaluates to the type of the first expression, unless that is constant - in which case it evalutates to the type of the second. This is useful when + in which case it evaluates to the type of the second. This is useful when assigning macro parameters to temporary variables, because that would normally circumvent the special loosened type promotion rules for integer literals. By using this macro, the promotion can happen at the time the diff --git a/src/commonlib/include/commonlib/iobuf.h b/src/commonlib/include/commonlib/iobuf.h index 472b368..0de7d3e 100644 --- a/src/commonlib/include/commonlib/iobuf.h +++ b/src/commonlib/include/commonlib/iobuf.h @@ -81,7 +81,7 @@ /* Out-of-band drain of ibuf by returning pointer to data of specified size. */ const void *ibuf_oob_drain(struct ibuf *ib, size_t sz); -/* Read arbitray data from input buffer. */ +/* Read arbitrary data from input buffer. */ int ibuf_read(struct ibuf *ib, void *data, size_t sz); /* Read big endian fixed size values. */ @@ -125,7 +125,7 @@ /* Fill the buffer out-of-band. The size is accounted for. */ void *obuf_oob_fill(struct obuf *ob, size_t sz); -/* Write arbitray data to output buffer. */ +/* Write arbitrary data to output buffer. */ int obuf_write(struct obuf *ob, const void *data, size_t sz); /* Write big endian fixed size values. */ diff --git a/src/console/Kconfig b/src/console/Kconfig index 4125e18..4c2e768 100644 --- a/src/console/Kconfig +++ b/src/console/Kconfig @@ -193,7 +193,7 @@ help Send coreboot debug output to a Ethernet console, it works same way as Linux netconsole, packets are received to UDP - port 6666 on IP/MAC specified with options bellow. + port 6666 on IP/MAC specified with options below. Use following netcat command: nc -u -l -p 6666 config CONSOLE_NE2K_DST_MAC diff --git a/src/cpu/x86/64bit/exit32.inc b/src/cpu/x86/64bit/exit32.inc index 91cccb5..4d1149e 100644 --- a/src/cpu/x86/64bit/exit32.inc +++ b/src/cpu/x86/64bit/exit32.inc @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * For droping from long mode to protected mode. + * For dropping from long mode to protected mode. * * For reference see "AMD64 ArchitectureProgrammer's Manual Volume 2", * Document 24593-Rev. 3.31-July 2019 Chapter 5.3 @@ -47,7 +47,7 @@ # use iret to jump to a 32-bit offset in a new code segment # iret will pop cs:rip, flags, then ss:rsp - mov %ss, %ax # need to push ss, but push ss instuction + mov %ss, %ax # need to push ss, but push ss instruction push %rax # not valid in x64 mode, so use ax push %rdx # the rsp to load pushfq # push rflags diff --git a/src/cpu/x86/pae/pgtbl.c b/src/cpu/x86/pae/pgtbl.c index 814dbf5..c8783d6 100644 --- a/src/cpu/x86/pae/pgtbl.c +++ b/src/cpu/x86/pae/pgtbl.c @@ -104,7 +104,7 @@ * Use PAE to map a page and then memset it with the pattern specified. * In order to use PAE pagetables for virtual addressing are set up and reloaded * on a 2MiB boundary. After the function is done, virtual addressing mode is - * disabled again. The PAT are set to all cachable, but MTRRs still apply. + * disabled again. The PAT are set to all cacheable, but MTRRs still apply. * * Requires a scratch memory for pagetables and a virtual address for * non identity mapped memory. @@ -124,7 +124,7 @@ * Content at physical address isn't preserved. * @param length The length of the memory segment to memset * @param dest Physical memory address to memset - * @param pat The pattern to write to the pyhsical memory + * @param pat The pattern to write to the physical memory * @return 0 on success, 1 on error */ int memset_pae(uint64_t dest, unsigned char pat, uint64_t length, void *pgtbl, diff --git a/src/cpu/x86/sipi_vector.S b/src/cpu/x86/sipi_vector.S index 44b772b..496fd34 100644 --- a/src/cpu/x86/sipi_vector.S +++ b/src/cpu/x86/sipi_vector.S @@ -57,7 +57,7 @@ movw %cs, %ax movw %ax, %ds - /* The gdtaddr needs to be releative to the data segment in order + /* The gdtaddr needs to be relative to the data segment in order * to properly dereference it. The .text section comes first in an * rmodule so _start can be used as a proxy for the load address. */ movl $(gdtaddr), %ebx diff --git a/src/device/Kconfig b/src/device/Kconfig index 5ae3466..ea3e241 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -166,7 +166,7 @@ def_bool n depends on VGA_ROM_RUN && ALWAYS_LOAD_OPROM help - Always uncondtionally run the option regardless of other + Always unconditionally run the option regardless of other policies. config ON_DEVICE_ROM_LOAD diff --git a/src/device/azalia_device.c b/src/device/azalia_device.c index 9202f72..70f8348 100644 --- a/src/device/azalia_device.c +++ b/src/device/azalia_device.c @@ -289,7 +289,7 @@ if (!res) return; - // NOTE this will break as soon as the azalia_audio get's a bar above 4G. + // NOTE this will break as soon as the azalia_audio gets a bar above 4G. // Is there anything we can do about it? base = res2mmio(res, 0, 0); printk(BIOS_DEBUG, "azalia_audio: base = %p\n", base); diff --git a/src/device/dram/ddr4.c b/src/device/dram/ddr4.c index 83beeaf..c5a8d13 100644 --- a/src/device/dram/ddr4.c +++ b/src/device/dram/ddr4.c @@ -205,7 +205,7 @@ /* Verify CRC of blocks that have them, do not step over 'used' length */ for (int i = 0; i < ARRAY_SIZE(spd_blocks); i++) { - /* this block is not checksumed */ + /* this block is not checksummed */ if (spd_blocks[i].crc_start == 0) continue; /* we shouldn't have this block */ diff --git a/src/device/oprom/include/x86emu/regs.h b/src/device/oprom/include/x86emu/regs.h index 7640c78..52f599d 100644 --- a/src/device/oprom/include/x86emu/regs.h +++ b/src/device/oprom/include/x86emu/regs.h @@ -54,7 +54,7 @@ * EAX & 0xff === AL * EAX & 0xffff == AX * - * etc. The result is that alot of the calculations can then be + * etc. The result is that a lot of the calculations can then be * done using the native instruction set fully. */ diff --git a/src/device/oprom/x86emu/LICENSE b/src/device/oprom/x86emu/LICENSE index f13d418..f1c26cc 100644 --- a/src/device/oprom/x86emu/LICENSE +++ b/src/device/oprom/x86emu/LICENSE @@ -1,7 +1,7 @@ License information ------------------- -The x86emu library is under a BSD style license, comaptible +The x86emu library is under a BSD style license, compatible with the XFree86 and X licenses used by XFree86. The original x86emu libraries were under the GNU General Public License. Due to license incompatibilities between the GPL diff --git a/src/device/oprom/x86emu/prim_ops.c b/src/device/oprom/x86emu/prim_ops.c index d794ecb..2350ac1 100644 --- a/src/device/oprom/x86emu/prim_ops.c +++ b/src/device/oprom/x86emu/prim_ops.c @@ -2458,7 +2458,7 @@ switch (feature) { case 0: /* Regardless if we have real data from the hardware, the emulator - * will only support upto feature 1, which we set in register EAX. + * will only support up to feature 1, which we set in register EAX. * Registers EBX:EDX:ECX contain a string identifying the CPU. */ M.x86.R_EAX = 1; diff --git a/src/device/pci_early.c b/src/device/pci_early.c index 3a4d2e0..590b170 100644 --- a/src/device/pci_early.c +++ b/src/device/pci_early.c @@ -104,7 +104,7 @@ } /* FIXME: A lot of issues using the following, please avoid. - * Assumes 256 PCI busses, scans them all even when PCI bridges are still + * Assumes 256 PCI buses, scans them all even when PCI bridges are still * disabled. Probes all functions even if 0 is not present. */ pci_devfn_t pci_locate_device(unsigned int pci_id, pci_devfn_t dev) diff --git a/src/device/pnp_device.c b/src/device/pnp_device.c index 699007d..88072b9 100644 --- a/src/device/pnp_device.c +++ b/src/device/pnp_device.c @@ -238,7 +238,7 @@ resource->limit = (1 << (bit + 1)) - 1; /* The block of ones in the mask is expected to be continuous. - If there is any zero inbetween the block of ones, it is ignored + If there is any zero in between the block of ones, it is ignored in the calculation of the resource size and limit. */ if (mask != (resource->limit ^ (resource->size - 1))) printk(BIOS_WARNING, diff --git a/src/device/resource_allocator_v4.c b/src/device/resource_allocator_v4.c index b94c295..6f8159e 100644 --- a/src/device/resource_allocator_v4.c +++ b/src/device/resource_allocator_v4.c @@ -637,7 +637,7 @@ * order to accomplish best fit for the resources, a list of ranges is maintained by each * resource type (i/o and mem). Domain does not differentiate between mem and prefmem. Since * they are allocated space from the same window, the resource allocator at the domain level - * ensures that the biggest requirement is selected indepedent of the prefetch type. Once the + * ensures that the biggest requirement is selected independent of the prefetch type. Once the * resource allocation for all immediate downstream devices is complete at the domain level, * resource allocator walks down the subtree for each downstream bridge to continue the * allocation process at the bridge level. Since bridges have separate windows for i/o, mem and diff --git a/src/drivers/amd/agesa/cache_as_ram.S b/src/drivers/amd/agesa/cache_as_ram.S index 1e15eda..0d678d1 100644 --- a/src/drivers/amd/agesa/cache_as_ram.S +++ b/src/drivers/amd/agesa/cache_as_ram.S @@ -5,7 +5,7 @@ * * $Workfile:: cache_as_ram.S * - * Description: cache_as_ram.S - AGESA Module Entry Point for GCC complier + * Description: cache_as_ram.S - AGESA Module Entry Point for GCC compiler * ****************************************************************************** */ diff --git a/src/drivers/crb/tpm.c b/src/drivers/crb/tpm.c index fcefe96..9c8f249 100644 --- a/src/drivers/crb/tpm.c +++ b/src/drivers/crb/tpm.c @@ -6,7 +6,7 @@ * * TPM starts in IDLE Mode * - * IDLE --> READY --> Command Receiption + * IDLE --> READY --> Command Reception * ^ | * | v -- Cmd Complete <-- Command Execution diff --git a/src/drivers/generic/gpio_keys/chip.h b/src/drivers/generic/gpio_keys/chip.h index 88dfe2e..01f4a12 100644 --- a/src/drivers/generic/gpio_keys/chip.h +++ b/src/drivers/generic/gpio_keys/chip.h @@ -81,7 +81,7 @@ struct acpi_gpio gpio; /* Is this a polled GPIO button? - Optional */ bool is_polled; - /* Poll inverval - Mandatory only if GPIO is polled. */ + /* Poll interval - Mandatory only if GPIO is polled. */ uint32_t poll_interval; /* Details about the key - Mandatory */ struct key_info key; diff --git a/src/drivers/i2c/lm96000/chip.h b/src/drivers/i2c/lm96000/chip.h index 128d1ec..bb86f4e 100644 --- a/src/drivers/i2c/lm96000/chip.h +++ b/src/drivers/i2c/lm96000/chip.h @@ -90,7 +90,7 @@ enum { /* turn fan off below `low_temp - hysteresis` */ LM96000_LOW_TEMP_OFF = 0, - /* keep PWM at mininum duty cycle */ + /* keep PWM at minimum duty cycle */ LM96000_LOW_TEMP_MIN = 1, } min_off; u8 hysteresis; diff --git a/src/drivers/i2c/nct7802y/chip.h b/src/drivers/i2c/nct7802y/chip.h index 03c464a..c4a767d 100644 --- a/src/drivers/i2c/nct7802y/chip.h +++ b/src/drivers/i2c/nct7802y/chip.h @@ -37,7 +37,7 @@ enum nct7802y_fan_smartmode { SMART_FAN_DUTY = 0, /* Target values given in duty cycle %. */ - SMART_FAN_RPM, /* Target valuse given in RPM. */ + SMART_FAN_RPM, /* Target values given in RPM. */ }; enum nct7802y_fan_speed { diff --git a/src/drivers/i2c/tpm/cr50.c b/src/drivers/i2c/tpm/cr50.c index 8e12d1f..a8a310f 100644 --- a/src/drivers/i2c/tpm/cr50.c +++ b/src/drivers/i2c/tpm/cr50.c @@ -3,7 +3,7 @@ /* Based on Linux Kernel TPM driver */ /* - * cr50 is a TPM 2.0 capable device that requries special + * cr50 is a TPM 2.0 capable device that requires special * handling for the I2C interface. * * - Use an interrupt for transaction status instead of hardcoded delays diff --git a/src/drivers/i2c/tpm/tpm.c b/src/drivers/i2c/tpm/tpm.c index ee23ea7..b96099c 100644 --- a/src/drivers/i2c/tpm/tpm.c +++ b/src/drivers/i2c/tpm/tpm.c @@ -35,7 +35,7 @@ /* max. number of iterations after I2C NAK for 'long' commands * we need this especially for sending TPM_READY, since the cleanup after the - * transtion to the ready state may take some time, but it is unpredictable + * transition to the ready state may take some time, but it is unpredictable * how long it will take. */ #define MAX_COUNT_LONG 50 diff --git a/src/drivers/i2c/ww_ring/ww_ring_programs.c b/src/drivers/i2c/ww_ring/ww_ring_programs.c index 7576a3b..73dd4da 100644 --- a/src/drivers/i2c/ww_ring/ww_ring_programs.c +++ b/src/drivers/i2c/ww_ring/ww_ring_programs.c @@ -91,7 +91,7 @@ * * When solid patterns are deployed with instanteneous color intensity * changes, all three LEDs can be controlled by one engine in sequential - * accesses. But the controllers still neeed to be synchronized. + * accesses. But the controllers still need to be synchronized. * * The maximum timer duration of lp55231 is .48 seconds. To achieve longer * blinking intervals the loops delays are deployed. Only the first controller diff --git a/src/drivers/i2c/ww_ring/ww_ring_programs.h b/src/drivers/i2c/ww_ring/ww_ring_programs.h index 4f93651..47d1c77 100644 --- a/src/drivers/i2c/ww_ring/ww_ring_programs.h +++ b/src/drivers/i2c/ww_ring/ww_ring_programs.h @@ -21,7 +21,7 @@ #include <stdint.h> #include "drivers/i2c/ww_ring/ww_ring.h" -/* There are threee independent engines/cores in the controller. */ +/* There are three independent engines/cores in the controller. */ #define LP55231_NUM_OF_ENGINES 3 /* Number of lp55321 controllers on the ring */ @@ -29,7 +29,7 @@ /* * Structure to describe an lp55231 program: pointer to the text of the - * program, its size and load address (load addr + size sould not exceed + * program, its size and load address (load addr + size should not exceed * LP55231_MAX_PROG_SIZE), and start addresses for all of the three * engines. */ diff --git a/src/drivers/ipmi/ipmi_fru.c b/src/drivers/ipmi/ipmi_fru.c index 976df1c..31ac6c0 100644 --- a/src/drivers/ipmi/ipmi_fru.c +++ b/src/drivers/ipmi/ipmi_fru.c @@ -525,7 +525,7 @@ if (prod_info.product_name != NULL) printk(BIOS_DEBUG, "product name: %s\n", prod_info.product_name); if (prod_info.product_partnumber != NULL) - printk(BIOS_DEBUG, "product part numer: %s\n", prod_info.product_partnumber); + printk(BIOS_DEBUG, "product part number: %s\n", prod_info.product_partnumber); if (prod_info.product_version != NULL) printk(BIOS_DEBUG, "product version: %s\n", prod_info.product_version); if (prod_info.serial_number != NULL) diff --git a/src/drivers/ipmi/supermicro_oem.c b/src/drivers/ipmi/supermicro_oem.c index 87b7fe2..9d5ffc7 100644 --- a/src/drivers/ipmi/supermicro_oem.c +++ b/src/drivers/ipmi/supermicro_oem.c @@ -26,7 +26,7 @@ int ret; size_t i; - /* Only 8 charactars are visible in UI. Cut of on first dash */ + /* Only 8 characters are visible in UI. Cut of on first dash */ for (i = 0; i < 15; i++) { if (coreboot_ver[i] == '-') break; diff --git a/src/drivers/net/Kconfig b/src/drivers/net/Kconfig index 282075b..7e111f6 100644 --- a/src/drivers/net/Kconfig +++ b/src/drivers/net/Kconfig @@ -33,7 +33,7 @@ select REALTEK_8168_RESET help This is to set a customized LED mode to distinguish 10/100/1000 - link and speed status with limited LEDs avaiable on a board. + link and speed status with limited LEDs available on a board. Please refer to RTL811x datasheet section 7.2 Customizable LED Configuration for details. With this flag enabled, the customized_leds variable will be read from devicetree setting. diff --git a/src/drivers/net/atl1e.c b/src/drivers/net/atl1e.c index 9b1b2ab..97ad140 100644 --- a/src/drivers/net/atl1e.c +++ b/src/drivers/net/atl1e.c @@ -127,7 +127,7 @@ /* Check if the base is invalid */ if (!mem_base) { - printk(BIOS_ERR, "atl1e: Error cant find MEM resource\n"); + printk(BIOS_ERR, "atl1e: Error can't find MEM resource\n"); return; } /* Enable but do not set bus master */ diff --git a/src/drivers/net/r8168.c b/src/drivers/net/r8168.c index 398b15d..1fd6edd 100644 --- a/src/drivers/net/r8168.c +++ b/src/drivers/net/r8168.c @@ -280,7 +280,7 @@ /* Check if the base is invalid */ if (!io_base) { - printk(BIOS_ERR, "r8168: Error cant find IO resource\n"); + printk(BIOS_ERR, "r8168: Error can't find IO resource\n"); return; } /* Enable but do not set bus master */ diff --git a/src/drivers/spi/spi_sdcard.c b/src/drivers/spi/spi_sdcard.c index a670111..0a18953 100644 --- a/src/drivers/spi/spi_sdcard.c +++ b/src/drivers/spi/spi_sdcard.c @@ -683,7 +683,7 @@ spi_sdcard_sendbyte(card, 0xff & (c >> 8)); spi_sdcard_sendbyte(card, 0xff & (c >> 0)); - /* recevie and verify data response token */ + /* receive and verify data response token */ c = spi_sdcard_recvbyte(card); if ((c & CT_RESPONSE_MASK) != CT_RESPONSE_ACCEPTED) { spi_sdcard_disable_cs(card); @@ -742,7 +742,7 @@ spi_sdcard_sendbyte(card, 0xff & (c >> 8)); spi_sdcard_sendbyte(card, 0xff & (c >> 0)); - /* recevie and verify data response token */ + /* receive and verify data response token */ c = spi_sdcard_recvbyte(card); if ((c & CT_RESPONSE_MASK) != CT_RESPONSE_ACCEPTED) break; diff --git a/src/drivers/spi/tpm/tpm.c b/src/drivers/spi/tpm/tpm.c index 1ad1eaa..30b1876 100644 --- a/src/drivers/spi/tpm/tpm.c +++ b/src/drivers/spi/tpm/tpm.c @@ -3,7 +3,7 @@ * * It assumes that the required SPI interface has been initialized before the * driver is started. A 'sruct spi_slave' pointer passed at initialization is - * used to direct traffic to the correct SPI interface. This dirver does not + * used to direct traffic to the correct SPI interface. This driver does not * provide a way to instantiate multiple TPM devices. Also, to keep things * simple, the driver unconditionally uses of TPM locality zero. * @@ -159,7 +159,7 @@ /* * The first byte of the frame header encodes the transaction type - * (read or write) and transfer size (set to lentgh - 1), limited to + * (read or write) and transfer size (set to length - 1), limited to * 64 bytes. */ header.body[0] = (read_write ? 0x80 : 0) | 0x40 | (bytes - 1); @@ -188,7 +188,7 @@ * the last clock of the byte) is set to 1. * * Due to some SPI controllers' shortcomings (Rockchip comes to - * mind...) we trasmit the 4 byte header without checking the byte + * mind...) we transmit the 4 byte header without checking the byte * transmitted by the TPM during the transaction's last byte. * * We know that cr50 is guaranteed to set the flow control bit to 0 diff --git a/src/ec/compal/ene932/acpi/ec.asl b/src/ec/compal/ene932/acpi/ec.asl index f3fb997..3242cce 100644 --- a/src/ec/compal/ene932/acpi/ec.asl +++ b/src/ec/compal/ene932/acpi/ec.asl @@ -118,7 +118,7 @@ SWTO, 1, // SW Throttling (1=Active) ; AEh.6 TTHR, 1, // HW (THRM#) Throttling (1=Active) ; AEh.7 TTHM, 1, // TS_THERMAL(1:Throttling for thermal) ; AFh.0 - THTL, 1, // THROTTLING(1:Ctrl H/W throtting act) ; AFh.1 + THTL, 1, // THROTTLING(1:Ctrl H/W throttling act); AFh.1 , 2, // Reserved ; AFh.2-3 NPST, 4, // Number of P-State level ; AFh.4-7 CTMP, 8, // Current CPU Temperature ; B0h diff --git a/src/ec/google/chromeec/ec.h b/src/ec/google/chromeec/ec.h index ed9f4e4..743651b 100644 --- a/src/ec/google/chromeec/ec.h +++ b/src/ec/google/chromeec/ec.h @@ -161,7 +161,7 @@ crosec_io_t crosec_io, void *context); /** - * Performs light verification of the EC<->AP communcation channel. + * Performs light verification of the EC<->AP communication channel. * * @return 0 on success, -1 on error */ @@ -330,7 +330,7 @@ * Get role-based capabilities for a USB-PD port * * @param port Which port to get information about - * @param *power_role_cap The power-role capabillity of the port + * @param *power_role_cap The power-role capability of the port * @param *try_power_role_cap The Try-power-role capability of the port * @param *data_role_cap The data role capability of the port * @param *port_location Location of the port on the device diff --git a/src/ec/google/chromeec/ec_commands.h b/src/ec/google/chromeec/ec_commands.h index e8b028f..5fb4596 100644 --- a/src/ec/google/chromeec/ec_commands.h +++ b/src/ec/google/chromeec/ec_commands.h @@ -2856,7 +2856,7 @@ */ struct __ec_todo_unpacked { /* Data to set or EC_MOTION_SENSE_NO_VALUE to read. - * kb_wake_angle: angle to wakup AP. + * kb_wake_angle: angle to wakeup AP. */ int16_t data; } kb_wake_angle; diff --git a/src/ec/google/wilco/commands.h b/src/ec/google/wilco/commands.h index a216345..b70f949 100644 --- a/src/ec/google/wilco/commands.h +++ b/src/ec/google/wilco/commands.h @@ -10,7 +10,7 @@ KB_POWER_SMI = 0x04, /* Read but do not clear power state information */ KB_POWER_STATUS = 0x05, - /* Inform the EC aboout the reason host is turning off */ + /* Inform the EC about the reason host is turning off */ KB_POWER_OFF = 0x08, /* Control wireless radios */ KB_RADIO_CONTROL = 0x2b, diff --git a/src/ec/quanta/ene_kb3940q/acpi/ec.asl b/src/ec/quanta/ene_kb3940q/acpi/ec.asl index 9d8cc28..a14c737 100644 --- a/src/ec/quanta/ene_kb3940q/acpi/ec.asl +++ b/src/ec/quanta/ene_kb3940q/acpi/ec.asl @@ -75,7 +75,7 @@ KBID, 1, // 0=EN KBD, 1=JP KBD ; 80h.1 , 6, // Reserved ; 80h.2-7 NPST, 8, // Number of P-State level ; 81h - MPST, 8, // Maxumum P-State ; 82h + MPST, 8, // Maximum P-State ; 82h KWAK, 1, // Keyboard WAKE(0=Disable,1=Enable) ; 83h.0 TWAK, 1, // TouchPad WAKE(0=Disable,1=Enable) ; 83h.1 , 1, // Reserved ; 83h.2 diff --git a/src/ec/quanta/it8518/acpi/battery.asl b/src/ec/quanta/it8518/acpi/battery.asl index 79a1da3..768f2b1 100644 --- a/src/ec/quanta/it8518/acpi/battery.asl +++ b/src/ec/quanta/it8518/acpi/battery.asl @@ -23,7 +23,7 @@ 0, // 0: Power Unit 0xFFFFFFFF, // 1: Design Capacity 0xFFFFFFFF, // 2: Last Full Charge Capacity - 1, // 3: Battery Technology(Rechargable) + 1, // 3: Battery Technology(Rechargeable) 10800, // 4: Design Voltage 10.8V 0, // 5: Design capacity of warning 0, // 6: Design capacity of low diff --git a/src/ec/quanta/it8518/acpi/ec.asl b/src/ec/quanta/it8518/acpi/ec.asl index 093593c..36f966f 100644 --- a/src/ec/quanta/it8518/acpi/ec.asl +++ b/src/ec/quanta/it8518/acpi/ec.asl @@ -444,7 +444,7 @@ MBTH, 4, // bit 3-0: battery 0 highest level SBTH, 4, // bit 7-4: battery 1 highest level // note: if highest level is 0 or 0xF, it means not defined - // (in this case, use default hightest level, it is 6) + // (in this case, use default highest level, it is 6) Offset(0xEF), // [EC Function Specification Major Version] Offset(0xF0), // [Build ID]~ offset:0F7h diff --git a/src/include/acpi/acpi.h b/src/include/acpi/acpi.h index 01d10c2..2c9af3a 100644 --- a/src/include/acpi/acpi.h +++ b/src/include/acpi/acpi.h @@ -1267,7 +1267,7 @@ * proximimity domain for the memory. */ int acpi_create_hmat_mpda(acpi_hmat_mpda_t *mpda, u32 initiator, u32 memory); -/* Create Heterogenous Memory Attribute Table */ +/* Create Heterogeneous Memory Attribute Table */ void acpi_create_hmat(acpi_hmat_t *hmat, unsigned long (*acpi_fill_hmat)(unsigned long current)); diff --git a/src/include/cpu/x86/save_state.h b/src/include/cpu/x86/save_state.h index d6fcf63..139a5fa 100644 --- a/src/include/cpu/x86/save_state.h +++ b/src/include/cpu/x86/save_state.h @@ -26,7 +26,7 @@ /* Return -1 on failure, otherwise returns which CPU node issued an APMC IO write */ int get_apmc_node(u8 cmd); -/* Return -1 on failure, 0 on succes. +/* Return -1 on failure, 0 on success. Accessors for the SMM save state CPU registers RAX, RBX, RCX and RDX */ int get_save_state_reg(const enum cpu_reg reg, const int node, void *out, const uint8_t length); int set_save_state_reg(const enum cpu_reg reg, const int node, void *in, const uint8_t length); diff --git a/src/include/device/i2c_simple.h b/src/include/device/i2c_simple.h index de1c0eb..8f389b3 100644 --- a/src/include/device/i2c_simple.h +++ b/src/include/device/i2c_simple.h @@ -35,7 +35,7 @@ /* * software_i2c is supposed to be a debug feature. It's usually not compiled in, - * but when it is it can be dynamically enabled at runtime for certain busses. + * but when it is it can be dynamically enabled at runtime for certain buses. * Need this ugly stub to arbitrate since I2C device drivers hardcode * 'i2c_transfer()' as their entry point. */ diff --git a/src/lib/device_tree.c b/src/lib/device_tree.c index 1fd8874..3821e5c 100644 --- a/src/lib/device_tree.c +++ b/src/lib/device_tree.c @@ -758,7 +758,7 @@ } /* - * Find the next compatible child of a given parent. All children upto the + * Find the next compatible child of a given parent. All children up to the * child passed in by caller are ignored. If child is NULL, it considers all the * children to find the first child which is compatible. * diff --git a/src/lib/edid.c b/src/lib/edid.c index cd7a47a..55876e8 100644 --- a/src/lib/edid.c +++ b/src/lib/edid.c @@ -433,7 +433,7 @@ /* * Slightly weird to return a global, but I've never - * seen any EDID block wth two range descriptors, so + * seen any EDID block with two range descriptors, so * it's harmless. */ return 1; @@ -481,7 +481,7 @@ We have no samples between those values, so put a threshold at 95000 kHz. If we get anything over 95000 kHz with single channel, we can make this - more sofisticated but it's currently not needed. + more sophisticated but it's currently not needed. */ out->mode.lvds_dual_channel = (out->mode.pixel_clock >= 95000); extra_info.x_mm = (x[12] + ((x[14] & 0xF0) << 4)); @@ -1094,7 +1094,7 @@ } /* - * Given a raw edid bloc, decode it into a form + * Given a raw edid block, decode it into a form * that other parts of coreboot can use -- mainly * graphics bringup functions. The raw block is * required to be 128 bytes long, per the standard, diff --git a/src/lib/nhlt.c b/src/lib/nhlt.c index 90a6cd9..a061b82 100644 --- a/src/lib/nhlt.c +++ b/src/lib/nhlt.c @@ -126,7 +126,7 @@ wave->channel_mask = speaker_mask; memcpy(&wave->sub_format, &pcm_subformat, sizeof(wave->sub_format)); - /* Calculate the dervied fields. */ + /* Calculate the derived fields. */ wave->block_align = wave->num_channels * wave->bits_per_sample / 8; wave->bytes_per_second = wave->block_align * wave->samples_per_second; diff --git a/src/lib/region_file.c b/src/lib/region_file.c index 4fe91b6..f3e66bf 100644 --- a/src/lib/region_file.c +++ b/src/lib/region_file.c @@ -9,7 +9,7 @@ * A region file provides generic support for appending new data * within a storage region. The book keeping is tracked in metadata * blocks where an offset pointer points to the last byte of a newly - * allocated byte sequence. Thus, by taking 2 block offets one can + * allocated byte sequence. Thus, by taking 2 block offsets one can * determine start and size of the latest update. The data does not * have to be the same consistent size, but the data size has be small * enough to fit a metadata block and one data write within the region. -- To view, visit https://review.coreboot.org/c/coreboot/+/58080 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5b8ecdfe75d99028fee820a2034466a8ad1c5e63 Gerrit-Change-Number: 58080 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/skl: mark C-state C2 as insupported in FADT
by Michael Niewöhner (Code Review) 01 Oct '21

01 Oct '21

Attention is currently required from: Felix Singer, Nico Huber, Furquan Shaikh, Paul Menzel, Angel Pons, Subrata Banik, Patrick Rudolph. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58079 ) Change subject: soc/intel/skl: mark C-state C2 as insupported in FADT ...................................................................... Patch Set 1: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/58079 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifdbf770941dbdf757e7189e999d222a72412002d Gerrit-Change-Number: 58079 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 01 Oct 2021 20:28:39 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/pmc: add a note about legacy OSes/payloads to PM Timer Kconfig
by Tim Wawrzynczak (Code Review) 01 Oct '21

01 Oct '21

Attention is currently required from: Felix Singer, Lance Zhao, Furquan Shaikh, Tim Wawrzynczak, Paul Menzel, Angel Pons, Subrata Banik, Michael Niewöhner, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58018 ) Change subject: soc/intel/pmc: add a note about legacy OSes/payloads to PM Timer Kconfig ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/58018 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I53f1814113902124779ed85da030374439570688 Gerrit-Change-Number: 58018 Gerrit-PatchSet: 4 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Lance Zhao Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 01 Oct 2021 20:28:09 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit October 2021