coreboot-gerrit October 2021

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Change in coreboot[master]: soc/intel/alderlake: Perform `heci_finalize` prior to booting to OS
by Subrata Banik (Code Review) 02 Oct '21

02 Oct '21

Attention is currently required from: Furquan Shaikh, Subrata Banik, Angel Pons, Patrick Rudolph. Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Angel Pons, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/58040 to look at the new patch set (#8). Change subject: soc/intel/alderlake: Perform `heci_finalize` prior to booting to OS ...................................................................... soc/intel/alderlake: Perform `heci_finalize` prior to booting to OS `heci_finalize` ensures to put all heci devices to D3 by setting the D0i3 bit prior to booting to the OS. TEST=Verified D0i3 bit is set for all HECI devices prior to booting to OS. BUG=b:200644229 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> Change-Id: I86d5959646522f9a2169bf13ae04d88b8f685e14 --- M src/soc/intel/alderlake/finalize.c 1 file changed, 19 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/58040/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/58040 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I86d5959646522f9a2169bf13ae04d88b8f685e14 Gerrit-Change-Number: 58040 Gerrit-PatchSet: 8 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common/../cse: Helper function to check CSE device `devfn` ...
by Subrata Banik (Code Review) 02 Oct '21

02 Oct '21

Attention is currently required from: Furquan Shaikh, Angel Pons, Patrick Rudolph. Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Angel Pons, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/58064 to look at the new patch set (#4). Change subject: soc/intel/common/../cse: Helper function to check CSE device `devfn` status ...................................................................... soc/intel/common/../cse: Helper function to check CSE device `devfn` status This patch creates a helper function in cse common code block to check the status of all CSE `devfn`. Example: CSE, CSE_2, IDER, KT, CSE_3 and CSE_4. Currently cse common code is only able to read the device state of `PCH_DEVFN_CSE` CSE device alone. Additionally, print `slot` and 'func' number of CSE devices in case the device is either disable or hidden. BUG=b:200644229 TEST=Able to build and boot ADLRVP-P with this patch where the serial message listed the CSE devices that are disabled in the device tree as below: HECI: CSE device 16.01 is disabled HECI: CSE device 16.04 is disabled HECI: CSE device 16.05 is disabled Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> Change-Id: I208b07e89e3aa9d682837380809fbff01ea225b0 --- M src/soc/intel/common/block/cse/cse.c M src/soc/intel/common/block/include/intelblocks/cse.h 2 files changed, 18 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/58064/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/58064 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I208b07e89e3aa9d682837380809fbff01ea225b0 Gerrit-Change-Number: 58064 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common/../cse: Allow D0i3 enable/disable for all CSE devices
by Subrata Banik (Code Review) 02 Oct '21

02 Oct '21

Attention is currently required from: Furquan Shaikh, Angel Pons, Patrick Rudolph. Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Angel Pons, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/58039 to look at the new patch set (#7). Change subject: soc/intel/common/../cse: Allow D0i3 enable/disable for all CSE devices ...................................................................... soc/intel/common/../cse: Allow D0i3 enable/disable for all CSE devices This patch ensures to pass cse device function number as argument for `set_cse_device_state()` to allow coreboot to perform enable/disable of D0i3 bit for all CSE devices to put the CSE device to Idle state or Active state. BUG=b:200644229 TEST= Able to build and boot ADLRVP where `set_cse_device_state()` is able to put the CSE device toidle state or active state based on `devfn` as argument. Change-Id: Ibe819e690c47453eaee02e435525a25b576232b5 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/common/block/cse/cse.c M src/soc/intel/common/block/cse/cse_eop.c M src/soc/intel/common/block/include/intelblocks/cse.h 3 files changed, 41 insertions(+), 41 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/58039/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/58039 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibe819e690c47453eaee02e435525a25b576232b5 Gerrit-Change-Number: 58039 Gerrit-PatchSet: 7 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common/../cse: Allow D0i3 enable/disable for all CSE devices
by Subrata Banik (Code Review) 02 Oct '21

02 Oct '21

Attention is currently required from: Furquan Shaikh, Subrata Banik, Angel Pons, Patrick Rudolph. Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Angel Pons, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/58039 to look at the new patch set (#6). Change subject: soc/intel/common/../cse: Allow D0i3 enable/disable for all CSE devices ...................................................................... soc/intel/common/../cse: Allow D0i3 enable/disable for all CSE devices This patch ensures to pass cse device function number as argument for `set_cse_device_state()` to allow coreboot to perform enable/disable of D0i3 bit for all CSE devices to put the CSE device to Idle state or Active state. Change-Id: Ibe819e690c47453eaee02e435525a25b576232b5 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/common/block/cse/cse.c M src/soc/intel/common/block/cse/cse_eop.c M src/soc/intel/common/block/include/intelblocks/cse.h 3 files changed, 41 insertions(+), 41 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/58039/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/58039 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibe819e690c47453eaee02e435525a25b576232b5 Gerrit-Change-Number: 58039 Gerrit-PatchSet: 6 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common/../cse: Avoid caching of CSE BAR
by Subrata Banik (Code Review) 02 Oct '21

02 Oct '21

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58062 ) Change subject: soc/intel/common/../cse: Avoid caching of CSE BAR ...................................................................... soc/intel/common/../cse: Avoid caching of CSE BAR This patch ensures all attempts to read CSE BAR is performing PCI config space read and returning the BAR value rather than using cached value. This refactoring is useful to read BAR of all CSE devices rather than just HECI 1 alone. Additionally, change the return type of get_cse_bar() from `uintptr_t` to `void *` to avoid typecasting while calling read32/write32 functions. BUG=b:200644229 TEST=Able to build and boot ADLRVP where CSE is able to perform PCI enumeration and send the EOP message at post. Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> Change-Id: Id4ecc9006d6323b7c9d7a6af1afa5cfe63d933e5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58062 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/soc/intel/common/block/cse/cse.c 1 file changed, 17 insertions(+), 42 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index ffe10a5..d3b7d9b 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -64,9 +64,19 @@ #define MEI_HDR_CSE_ADDR_START 0 #define MEI_HDR_CSE_ADDR (((1 << 8) - 1) << MEI_HDR_CSE_ADDR_START) -static struct cse_device { - uintptr_t sec_bar; -} cse; +/* Get HECI BAR 0 from PCI configuration space */ +static uintptr_t get_cse_bar(void) +{ + uintptr_t bar; + + bar = pci_read_config32(PCH_DEV_CSE, PCI_BASE_ADDRESS_0); + assert(bar != 0); + /* + * Bits 31-12 are the base address as per EDS for SPI, + * Don't care about 0-11 bit + */ + return bar & ~PCI_BASE_ADDRESS_MEM_ATTR_MASK; +} /* * Initialize the device with provided temporary BAR. If BAR is 0 use a @@ -83,7 +93,7 @@ u16 pcireg; /* Assume it is already initialized, nothing else to do */ - if (cse.sec_bar) + if (get_cse_bar()) return; /* Use default pre-ram bar */ @@ -102,38 +112,16 @@ /* Enable Bus Master and MMIO Space */ pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); - - cse.sec_bar = tempbar; -} - -/* Get HECI BAR 0 from PCI configuration space */ -static uint32_t get_cse_bar(void) -{ - uintptr_t bar; - - bar = pci_read_config32(PCH_DEV_CSE, PCI_BASE_ADDRESS_0); - assert(bar != 0); - /* - * Bits 31-12 are the base address as per EDS for SPI, - * Don't care about 0-11 bit - */ - return bar & ~PCI_BASE_ADDRESS_MEM_ATTR_MASK; } static uint32_t read_bar(uint32_t offset) { - /* Load and cache BAR */ - if (!cse.sec_bar) - cse.sec_bar = get_cse_bar(); - return read32((void *)(cse.sec_bar + offset)); + return read32p(get_cse_bar() + offset); } static void write_bar(uint32_t offset, uint32_t val) { - /* Load and cache BAR */ - if (!cse.sec_bar) - cse.sec_bar = get_cse_bar(); - return write32((void *)(cse.sec_bar + offset), val); + return write32p(get_cse_bar() + offset, val); } static uint32_t read_cse_csr(void) @@ -968,21 +956,8 @@ #if ENV_RAMSTAGE -static void update_sec_bar(struct device *dev) -{ - cse.sec_bar = find_resource(dev, PCI_BASE_ADDRESS_0)->base; -} - -static void cse_set_resources(struct device *dev) -{ - if (dev->path.pci.devfn == PCH_DEVFN_CSE) - update_sec_bar(dev); - - pci_dev_set_resources(dev); -} - static struct device_operations cse_ops = { - .set_resources = cse_set_resources, + .set_resources = pci_dev_set_resources, .read_resources = pci_dev_read_resources, .enable_resources = pci_dev_enable_resources, .init = pci_dev_init, 3 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/58062 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id4ecc9006d6323b7c9d7a6af1afa5cfe63d933e5 Gerrit-Change-Number: 58062 Gerrit-PatchSet: 5 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Subrata Banik <subi.banik(a)gmail.com> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/common/../cse: Append `_MS` with CSE_DELAY_BOOT_TO_RO macro
by Subrata Banik (Code Review) 02 Oct '21

02 Oct '21

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58063 ) Change subject: soc/intel/common/../cse: Append `_MS` with CSE_DELAY_BOOT_TO_RO macro ...................................................................... soc/intel/common/../cse: Append `_MS` with CSE_DELAY_BOOT_TO_RO macro CSE_DELAY_BOOT_TO_RO -> CSE_DELAY_BOOT_TO_RO_MS Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> Change-Id: I4471e4553a081eaf5c8118e9600497a2b2437ac0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58063 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/soc/intel/common/block/cse/cse.c 1 file changed, 3 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index 8d5644c..ffe10a5 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -29,6 +29,8 @@ #define HECI_READ_TIMEOUT_MS (5 * 1000) /* Wait up to 1 ms for CSE CIP */ #define HECI_CIP_TIMEOUT_US 1000 +/* Wait up to 5 seconds for CSE to boot from RO(BP1) */ +#define CSE_DELAY_BOOT_TO_RO_MS (5 * 1000) #define SLOT_SIZE sizeof(uint32_t) @@ -62,9 +64,6 @@ #define MEI_HDR_CSE_ADDR_START 0 #define MEI_HDR_CSE_ADDR (((1 << 8) - 1) << MEI_HDR_CSE_ADDR_START) -/* Wait up to 5 seconds for CSE to boot from RO(BP1) */ -#define CSE_DELAY_BOOT_TO_RO (5 * 1000) - static struct cse_device { uintptr_t sec_bar; } cse; @@ -306,7 +305,7 @@ uint8_t cse_wait_com_soft_temp_disable(void) { struct stopwatch sw; - stopwatch_init_msecs_expire(&sw, CSE_DELAY_BOOT_TO_RO); + stopwatch_init_msecs_expire(&sw, CSE_DELAY_BOOT_TO_RO_MS); while (!cse_is_hfs1_com_soft_temp_disable()) { udelay(HECI_DELAY_US); if (stopwatch_expired(&sw)) { 4 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/58063 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4471e4553a081eaf5c8118e9600497a2b2437ac0 Gerrit-Change-Number: 58063 Gerrit-PatchSet: 6 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/common/../cse: Avoid caching of CSE BAR
by Subrata Banik (Code Review) 02 Oct '21

02 Oct '21

Attention is currently required from: Furquan Shaikh, Subrata Banik, Angel Pons, Patrick Rudolph. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58062 ) Change subject: soc/intel/common/../cse: Avoid caching of CSE BAR ...................................................................... Patch Set 3: (1 comment) File src/soc/intel/common/block/cse/cse.c: https://review.coreboot.org/c/coreboot/+/58062/comment/71c01275_ba275b17 PS2, Line 69: void * > Good catch! that one is one of those that GCC lets through because it has special support. […] SGTM, I will also keep an eye on this. -- To view, visit https://review.coreboot.org/c/coreboot/+/58062 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id4ecc9006d6323b7c9d7a6af1afa5cfe63d933e5 Gerrit-Change-Number: 58062 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Sat, 02 Oct 2021 08:33:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: coreboot tables: Add type-c port info to coreboot table
by Nick Vaccaro (Code Review) 02 Oct '21

02 Oct '21

Attention is currently required from: Nico Huber, Tim Wawrzynczak, Nick Vaccaro. Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Zhuohao Lee, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/57069 to look at the new patch set (#32). Change subject: coreboot tables: Add type-c port info to coreboot table ...................................................................... coreboot tables: Add type-c port info to coreboot table This change adds type-c port information for USB Type-C ports to the coreboot table. This allows depthcharge to know the usb2 and usb3 port number assignments for each available port, as well as the SBU and data line orientation for the board. BUG=b:149830546 TEST='emerge-volteer coreboot chromeos-bootimage' and verify it builds successfully. Cherry-pick CL to enable this feature for volteer, flash and boot volteer2 to kernel, log in and check cbmem for type-c info exported to the payload: localhost ~ # cbmem -c | grep type-c added type-c port0 info to cbmem: usb2:9 usb3:1 sbu:0 data:0 added type-c port1 info to cbmem: usb2:4 usb3:2 sbu:1 data:0 Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com> Change-Id: Ice732be2fa634dbf31ec620552b383c4a5b41451 --- M payloads/libpayload/include/coreboot_tables.h M payloads/libpayload/include/sysinfo.h M payloads/libpayload/libc/coreboot.c M src/commonlib/include/commonlib/cbmem_id.h M src/commonlib/include/commonlib/coreboot_tables.h M src/lib/coreboot_table.c 6 files changed, 54 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/57069/32 -- To view, visit https://review.coreboot.org/c/coreboot/+/57069 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ice732be2fa634dbf31ec620552b383c4a5b41451 Gerrit-Change-Number: 57069 Gerrit-PatchSet: 32 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: driver/intel/pmc_mux/conn: Move typec_orientation enum to coreboot_ta...
by Nick Vaccaro (Code Review) 01 Oct '21

01 Oct '21

Attention is currently required from: Patrick Rudolph. Nick Vaccaro has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58084 ) Change subject: driver/intel/pmc_mux/conn: Move typec_orientation enum to coreboot_tables.h ...................................................................... driver/intel/pmc_mux/conn: Move typec_orientation enum to coreboot_tables.h Move the locally declared typec_orientation enum from chip.h to coreboot_tables.h. Change enum typec_orientation name to type_c_orientation for consistency with contents of coreboot_tables.h. Rename TYPEC_ORIENTATION_FOLLOW_CC to TYPEC_ORIENTATION_NONE. BUG=b:149830546 TEST="emerge-volteer coreboot" and make sure it compiles successfully. Change-Id: I24c9177be72b0c9831791aa7d1f7b1236309c9cd Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com> --- M payloads/libpayload/include/coreboot_tables.h M src/commonlib/include/commonlib/coreboot_tables.h M src/drivers/intel/pmc_mux/conn/chip.h M src/drivers/intel/pmc_mux/conn/conn.c 4 files changed, 25 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/58084/1 diff --git a/payloads/libpayload/include/coreboot_tables.h b/payloads/libpayload/include/coreboot_tables.h index a841e03..914cfa5 100644 --- a/payloads/libpayload/include/coreboot_tables.h +++ b/payloads/libpayload/include/coreboot_tables.h @@ -143,6 +143,12 @@ u8 strings[0]; }; +enum type_c_orientation { + TYPEC_ORIENTATION_NONE, + TYPEC_ORIENTATION_NORMAL, + TYPEC_ORIENTATION_REVERSE, +}; + struct type_c_port_info { /* * usb2_port_number and usb3_port_number are expected to be diff --git a/src/commonlib/include/commonlib/coreboot_tables.h b/src/commonlib/include/commonlib/coreboot_tables.h index ab8da7b..91da8e0 100644 --- a/src/commonlib/include/commonlib/coreboot_tables.h +++ b/src/commonlib/include/commonlib/coreboot_tables.h @@ -426,7 +426,17 @@ * USB Type-C Port Information * This record contains board-specific type-c port information. * There will be one record per type-C port. + * Orientation fields should be of type enum type_c_orientation. */ +enum type_c_orientation { + /* The orientation of the signal follows the orientation of the CC lines. */ + TYPEC_ORIENTATION_NONE, + /* The orientation of the signal is fixed to follow CC1 */ + TYPEC_ORIENTATION_NORMAL, + /* The orientation of the signal is fixed to follow CC2 */ + TYPEC_ORIENTATION_REVERSE, +}; + struct type_c_port_info { uint8_t usb2_port_number; uint8_t usb3_port_number; diff --git a/src/drivers/intel/pmc_mux/conn/chip.h b/src/drivers/intel/pmc_mux/conn/chip.h index 461916e..96347ae 100644 --- a/src/drivers/intel/pmc_mux/conn/chip.h +++ b/src/drivers/intel/pmc_mux/conn/chip.h @@ -3,14 +3,7 @@ #ifndef __DRIVERS_INTEL_PMC_MUX_CONN_H__ #define __DRIVERS_INTEL_PMC_MUX_CONN_H__ -enum typec_orientation { - /* The orientation of the signal follows the orientation of the CC lines. */ - TYPEC_ORIENTATION_FOLLOW_CC = 0, - /* The orientation of the signal is fixed to follow CC1 */ - TYPEC_ORIENTATION_NORMAL, - /* The orientation of the signal is fixed to follow CC2 */ - TYPEC_ORIENTATION_REVERSE, -}; +#include <boot/coreboot_tables.h> struct drivers_intel_pmc_mux_conn_config { /* 1-based port numbers (from SoC point of view) */ @@ -18,9 +11,9 @@ /* 1-based port numbers (from SoC point of view) */ int usb3_port_number; /* Orientation of the sideband signals (SBU) */ - enum typec_orientation sbu_orientation; + enum type_c_orientation sbu_orientation; /* Orientation of the High Speed lines */ - enum typec_orientation hsl_orientation; + enum type_c_orientation hsl_orientation; }; /* diff --git a/src/drivers/intel/pmc_mux/conn/conn.c b/src/drivers/intel/pmc_mux/conn/conn.c index b6bf371..7a622c8 100644 --- a/src/drivers/intel/pmc_mux/conn/conn.c +++ b/src/drivers/intel/pmc_mux/conn/conn.c @@ -1,8 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include <acpi/acpigen.h> +#include <boot/coreboot_tables.h> #include <console/console.h> #include <intelblocks/acpi.h> + #include "chip.h" static const char *conn_acpi_name(const struct device *dev) @@ -12,14 +14,14 @@ return name; } -static const char *orientation_to_str(enum typec_orientation ori) +static const char *orientation_to_str(enum type_c_orientation ori) { switch (ori) { case TYPEC_ORIENTATION_NORMAL: return "normal"; case TYPEC_ORIENTATION_REVERSE: return "reverse"; - case TYPEC_ORIENTATION_FOLLOW_CC: /* Intentional fallthrough */ + case TYPEC_ORIENTATION_NONE: /* Intentional fallthrough */ default: return ""; } @@ -52,11 +54,11 @@ * The kernel assumes that these Type-C signals (SBUs and HSLs) follow the CC lines, * unless they are explicitly called out otherwise. */ - if (config->sbu_orientation != TYPEC_ORIENTATION_FOLLOW_CC) + if (config->sbu_orientation != TYPEC_ORIENTATION_NONE) acpi_dp_add_string(dsd, "sbu-orientation", orientation_to_str(config->sbu_orientation)); - if (config->hsl_orientation != TYPEC_ORIENTATION_FOLLOW_CC) + if (config->hsl_orientation != TYPEC_ORIENTATION_NONE) acpi_dp_add_string(dsd, "hsl-orientation", orientation_to_str(config->hsl_orientation)); -- To view, visit https://review.coreboot.org/c/coreboot/+/58084 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I24c9177be72b0c9831791aa7d1f7b1236309c9cd Gerrit-Change-Number: 58084 Gerrit-PatchSet: 1 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: driver/intel/pmc_mux/conn: Add type-c port info to cbmem
by Nick Vaccaro (Code Review) 01 Oct '21

01 Oct '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Nick Vaccaro, Patrick Rudolph. Hello build bot (Jenkins), Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/57345 to look at the new patch set (#17). Change subject: driver/intel/pmc_mux/conn: Add type-c port info to cbmem ...................................................................... driver/intel/pmc_mux/conn: Add type-c port info to cbmem This change adds type-c port information for USB type-c ports to cbmem. BUG=b:149830546 TEST='emerge-volteer coreboot chromeos-bootimage', flash and boot volteer2 to kernel, log in and check cbmem for type-c info exported to the payload: localhost ~ # cbmem -c | grep type-c added type-c port0 info to cbmem: usb2:9 usb3:1 sbu:0 data:0 added type-c port1 info to cbmem: usb2:4 usb3:2 sbu:1 data:0 Change-Id: Ic56a1ad1b617e3af000664147d21165e6ea3a742 Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com> --- M src/drivers/intel/pmc_mux/conn/conn.c 1 file changed, 56 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/57345/17 -- To view, visit https://review.coreboot.org/c/coreboot/+/57345 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic56a1ad1b617e3af000664147d21165e6ea3a742 Gerrit-Change-Number: 57345 Gerrit-PatchSet: 17 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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coreboot-gerrit October 2021