coreboot-gerrit October 2021

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Change in coreboot[master]: soc/intel/alderlake: add power limits for Alder Lake-M 282 SKU
by Felix Held (Code Review) 01 Oct '21

01 Oct '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/57465 ) Change subject: soc/intel/alderlake: add power limits for Alder Lake-M 282 SKU ...................................................................... soc/intel/alderlake: add power limits for Alder Lake-M 282 SKU There are two different types of 282 SKU available with TDP of 15W and 12W for Alder Lake-M SoC. This patch adds support for these TDP values for 282 SKU as per document 643782. BUG=None BRANCH=None TEST=Build FW and test on adlrvp board Change-Id: I553b2362b7bf811e6bf02fd9d68f78c2caeb7398 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57465 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-by: Selma Bensaid <selma.bensaid(a)intel.com> --- M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/chipset.cb 2 files changed, 11 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved Selma Bensaid: Looks good to me, but someone else must approve diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h index 6308094..3192478 100644 --- a/src/soc/intel/alderlake/chip.h +++ b/src/soc/intel/alderlake/chip.h @@ -25,7 +25,8 @@ ADL_P_482_CORE, ADL_P_682_28W_CORE, ADL_P_682_45W_CORE, - ADL_M_282_CORE, + ADL_M_282_12W_CORE, + ADL_M_282_15W_CORE, ADL_M_242_CORE, ADL_P_242_CORE, ADL_POWER_LIMITS_COUNT @@ -34,6 +35,7 @@ /* TDP values for different SKUs */ enum soc_intel_alderlake_cpu_tdps { TDP_9W = 9, + TDP_12W = 12, TDP_15W = 15, TDP_28W = 28, TDP_45W = 45 @@ -50,7 +52,8 @@ { PCI_DEVICE_ID_INTEL_ADL_P_ID_5, ADL_P_482_CORE, TDP_28W }, { PCI_DEVICE_ID_INTEL_ADL_P_ID_3, ADL_P_682_28W_CORE, TDP_28W }, { PCI_DEVICE_ID_INTEL_ADL_P_ID_3, ADL_P_682_45W_CORE, TDP_45W }, - { PCI_DEVICE_ID_INTEL_ADL_M_ID_1, ADL_M_282_CORE, TDP_15W }, + { PCI_DEVICE_ID_INTEL_ADL_M_ID_1, ADL_M_282_12W_CORE, TDP_12W }, + { PCI_DEVICE_ID_INTEL_ADL_M_ID_1, ADL_M_282_15W_CORE, TDP_15W }, { PCI_DEVICE_ID_INTEL_ADL_M_ID_2, ADL_M_242_CORE, TDP_9W }, }; diff --git a/src/soc/intel/alderlake/chipset.cb b/src/soc/intel/alderlake/chipset.cb index d70d939..9a752dd 100644 --- a/src/soc/intel/alderlake/chipset.cb +++ b/src/soc/intel/alderlake/chipset.cb @@ -26,7 +26,12 @@ .tdp_pl4 = 215, }" - register "power_limits_config[ADL_M_282_CORE]" = "{ + register "power_limits_config[ADL_M_282_12W_CORE]" = "{ + .tdp_pl1_override = 12, + .tdp_pl2_override = 35, + }" + + register "power_limits_config[ADL_M_282_15W_CORE]" = "{ .tdp_pl1_override = 15, .tdp_pl2_override = 45, }" -- To view, visit https://review.coreboot.org/c/coreboot/+/57465 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I553b2362b7bf811e6bf02fd9d68f78c2caeb7398 Gerrit-Change-Number: 57465 Gerrit-PatchSet: 7 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/common/../cse: Avoid caching of CSE BAR
by Tim Wawrzynczak (Code Review) 01 Oct '21

01 Oct '21

Attention is currently required from: Furquan Shaikh, Subrata Banik, Angel Pons, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58062 ) Change subject: soc/intel/common/../cse: Avoid caching of CSE BAR ...................................................................... Patch Set 3: (1 comment) File src/soc/intel/common/block/cse/cse.c: https://review.coreboot.org/c/coreboot/+/58062/comment/9163937e_b53dfd7e PS2, Line 69: void * > Agreed as good practice. […] Good catch! that one is one of those that GCC lets through because it has special support. There are probably more these, I can try to poke around some more and hunt more down. -- To view, visit https://review.coreboot.org/c/coreboot/+/58062 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id4ecc9006d6323b7c9d7a6af1afa5cfe63d933e5 Gerrit-Change-Number: 58062 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 01 Oct 2021 18:44:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/adlrvp: set PL4 value dynamically for thermal
by Felix Held (Code Review) 01 Oct '21

01 Oct '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/57464 ) Change subject: mb/intel/adlrvp: set PL4 value dynamically for thermal ...................................................................... mb/intel/adlrvp: set PL4 value dynamically for thermal Set PL4 value dynamically for adlrvp board based on CPU SKUs which is detectable at runtime. These values are based on platform design specification. BUG=None BRANCH=None TEST=Build FW and test on adlrvp board On 682: Overriding power limits PL1 (4000, 28000) PL2 (64000, 64000) PL4 (140000) Change-Id: I9c0c418e2548cc7f9aa647a5ad98123b33e9f9b8 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57464 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/intel/adlrvp/include/baseboard/variants.h M src/mainboard/intel/adlrvp/ramstage.c 2 files changed, 14 insertions(+), 8 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/intel/adlrvp/include/baseboard/variants.h b/src/mainboard/intel/adlrvp/include/baseboard/variants.h index bd67192..9ab05f6 100644 --- a/src/mainboard/intel/adlrvp/include/baseboard/variants.h +++ b/src/mainboard/intel/adlrvp/include/baseboard/variants.h @@ -45,6 +45,7 @@ unsigned int pl1_max_power; unsigned int pl2_min_power; unsigned int pl2_max_power; + unsigned int pl4_power; }; /* Modify Power Limit devictree settings during ramstage */ void variant_update_power_limits(void); diff --git a/src/mainboard/intel/adlrvp/ramstage.c b/src/mainboard/intel/adlrvp/ramstage.c index 76cf53a..136fa45 100644 --- a/src/mainboard/intel/adlrvp/ramstage.c +++ b/src/mainboard/intel/adlrvp/ramstage.c @@ -13,13 +13,13 @@ #include <intelblocks/power_limit.h> const struct cpu_power_limits limits[] = { - /* SKU_ID, TDP (Watts), pl1_min, pl1_max, pl2_min, pl2_max */ + /* SKU_ID, TDP (Watts), pl1_min, pl1_max, pl2_min, pl2_max, PL4 */ /* PL2 values are for performance configuration */ - { PCI_DEVICE_ID_INTEL_ADL_P_ID_7, 15, 3000, 15000, 55000, 55000 }, - { PCI_DEVICE_ID_INTEL_ADL_P_ID_6, 15, 3000, 15000, 55000, 55000 }, - { PCI_DEVICE_ID_INTEL_ADL_P_ID_5, 28, 4000, 28000, 64000, 64000 }, - { PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 28, 4000, 28000, 64000, 64000 }, - { PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 45, 5000, 45000, 115000, 115000 }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_7, 15, 3000, 15000, 55000, 55000, 123000 }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_6, 15, 3000, 15000, 55000, 55000, 123000 }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_5, 28, 4000, 28000, 64000, 64000, 140000 }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 28, 4000, 28000, 64000, 64000, 140000 }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 45, 5000, 45000, 115000, 115000, 215000 }, }; WEAK_DEV_PTR(dptf_policy); @@ -38,15 +38,20 @@ for (size_t i = 0; i < ARRAY_SIZE(limits); i++) { if (mchid == limits[i].mchid && tdp == limits[i].cpu_tdp) { struct dptf_power_limits *settings = &config->controls.power_limits; + config_t *conf = config_of_soc(); + struct soc_power_limits_config *soc_config = conf->power_limits_config; settings->pl1.min_power = limits[i].pl1_min_power; settings->pl1.max_power = limits[i].pl1_max_power; settings->pl2.min_power = limits[i].pl2_min_power; settings->pl2.max_power = limits[i].pl2_max_power; - printk(BIOS_INFO, "Overriding DPTF power limits PL1 (%u, %u) PL2 (%u, %u)\n", + soc_config->tdp_pl4 = DIV_ROUND_UP(limits[i].pl4_power, + MILLIWATTS_TO_WATTS); + printk(BIOS_INFO, "Overriding power limits PL1 (%u, %u) PL2 (%u, %u) PL4 (%u)\n", limits[i].pl1_min_power, limits[i].pl1_max_power, limits[i].pl2_min_power, - limits[i].pl2_max_power); + limits[i].pl2_max_power, + limits[i].pl4_power); } } } -- To view, visit https://review.coreboot.org/c/coreboot/+/57464 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9c0c418e2548cc7f9aa647a5ad98123b33e9f9b8 Gerrit-Change-Number: 57464 Gerrit-PatchSet: 7 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brya: move MILLIWATTS_TO_WATTS macro in header file
by Felix Held (Code Review) 01 Oct '21

01 Oct '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/57463 ) Change subject: mb/google/brya: move MILLIWATTS_TO_WATTS macro in header file ...................................................................... mb/google/brya: move MILLIWATTS_TO_WATTS macro in header file Move MILLIWATTS_TO_WATTS macro in power_limit header file so all other files can use the same macro. BUG=None BRANCH=None TEST=Build FW and test on brya0 board Change-Id: Ic7ecba06b0e0a47546f7307cbfbc3ce0fc634bc3 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57463 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/brya/variants/baseboard/brya/ramstage.c M src/soc/intel/common/block/include/intelblocks/power_limit.h 2 files changed, 2 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/baseboard/brya/ramstage.c b/src/mainboard/google/brya/variants/baseboard/brya/ramstage.c index 1328213..9c2d4aa 100644 --- a/src/mainboard/google/brya/variants/baseboard/brya/ramstage.c +++ b/src/mainboard/google/brya/variants/baseboard/brya/ramstage.c @@ -9,8 +9,6 @@ #include <drivers/intel/dptf/chip.h> #include <intelblocks/power_limit.h> -#define MILLIWATTS_TO_WATTS 1000 - WEAK_DEV_PTR(dptf_policy); void variant_update_power_limits(const struct cpu_power_limits *limits, size_t num_entries) diff --git a/src/soc/intel/common/block/include/intelblocks/power_limit.h b/src/soc/intel/common/block/include/intelblocks/power_limit.h index 934eaa4..3f18126 100644 --- a/src/soc/intel/common/block/include/intelblocks/power_limit.h +++ b/src/soc/intel/common/block/include/intelblocks/power_limit.h @@ -15,6 +15,8 @@ /* Default power limit value in secs */ #define MOBILE_SKU_PL1_TIME_SEC 28 +#define MILLIWATTS_TO_WATTS 1000 + struct soc_power_limits_config { /* PL1 Override value in Watts */ uint16_t tdp_pl1_override; -- To view, visit https://review.coreboot.org/c/coreboot/+/57463 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic7ecba06b0e0a47546f7307cbfbc3ce0fc634bc3 Gerrit-Change-Number: 57463 Gerrit-PatchSet: 7 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/intel/adlrvp: set power limits dynamically for thermal
by Felix Held (Code Review) 01 Oct '21

01 Oct '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/57462 ) Change subject: mb/intel/adlrvp: set power limits dynamically for thermal ...................................................................... mb/intel/adlrvp: set power limits dynamically for thermal Set power limit values dynamically based on CPU TDP and PCI ID of SKU. These values are as per platform design specification. BUG=None BRANCH=None TEST=Build FW and test on adlrvp board Change-Id: I8ba901fe7c978aad43b85a860c71b33bfbff2ff5 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57462 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/intel/adlrvp/include/baseboard/variants.h M src/mainboard/intel/adlrvp/ramstage.c 2 files changed, 11 insertions(+), 6 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/intel/adlrvp/include/baseboard/variants.h b/src/mainboard/intel/adlrvp/include/baseboard/variants.h index bc2a57e..bd67192 100644 --- a/src/mainboard/intel/adlrvp/include/baseboard/variants.h +++ b/src/mainboard/intel/adlrvp/include/baseboard/variants.h @@ -40,6 +40,7 @@ void variant_devtree_update(void); struct cpu_power_limits { uint16_t mchid; + u8 cpu_tdp; unsigned int pl1_min_power; unsigned int pl1_max_power; unsigned int pl2_min_power; diff --git a/src/mainboard/intel/adlrvp/ramstage.c b/src/mainboard/intel/adlrvp/ramstage.c index 99ce52e..76cf53a 100644 --- a/src/mainboard/intel/adlrvp/ramstage.c +++ b/src/mainboard/intel/adlrvp/ramstage.c @@ -10,14 +10,16 @@ #include <soc/soc_chip.h> #include <drivers/intel/dptf/chip.h> #include "board_id.h" +#include <intelblocks/power_limit.h> const struct cpu_power_limits limits[] = { - /* SKU_ID, pl1_min, pl1_max, pl2_min, pl2_max */ + /* SKU_ID, TDP (Watts), pl1_min, pl1_max, pl2_min, pl2_max */ /* PL2 values are for performance configuration */ - { PCI_DEVICE_ID_INTEL_ADL_P_ID_7, 3000, 15000, 55000, 55000 }, - { PCI_DEVICE_ID_INTEL_ADL_P_ID_6, 3000, 15000, 55000, 55000 }, - { PCI_DEVICE_ID_INTEL_ADL_P_ID_5, 4000, 28000, 64000, 64000 }, - { PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 5000, 45000, 115000, 115000 }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_7, 15, 3000, 15000, 55000, 55000 }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_6, 15, 3000, 15000, 55000, 55000 }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_5, 28, 4000, 28000, 64000, 64000 }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 28, 4000, 28000, 64000, 64000 }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 45, 5000, 45000, 115000, 115000 }, }; WEAK_DEV_PTR(dptf_policy); @@ -31,8 +33,10 @@ uint16_t mchid = pci_s_read_config16(PCI_DEV(0, 0, 0), PCI_DEVICE_ID); + u8 tdp = get_cpu_tdp(); + for (size_t i = 0; i < ARRAY_SIZE(limits); i++) { - if (mchid == limits[i].mchid) { + if (mchid == limits[i].mchid && tdp == limits[i].cpu_tdp) { struct dptf_power_limits *settings = &config->controls.power_limits; settings->pl1.min_power = limits[i].pl1_min_power; settings->pl1.max_power = limits[i].pl1_max_power; -- To view, visit https://review.coreboot.org/c/coreboot/+/57462 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8ba901fe7c978aad43b85a860c71b33bfbff2ff5 Gerrit-Change-Number: 57462 Gerrit-PatchSet: 7 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/intel/adlrvp: set power limits dynamically for thermal
by Felix Held (Code Review) 01 Oct '21

01 Oct '21

Attention is currently required from: Bora Guvendik, Furquan Shaikh, Paul Menzel, Sumeet R Pawnikar, Karthik Ramasubramanian. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57462 ) Change subject: mb/intel/adlrvp: set power limits dynamically for thermal ...................................................................... Patch Set 6: (1 comment) Patchset: PS6: are those board- or soc-specific? only had a very brief look at the code, but if those settings are soc-specific and not board-specific, i'd move that out of the mainboard code into the soc code in a follow-up patch to not need the table and code in every mainboard -- To view, visit https://review.coreboot.org/c/coreboot/+/57462 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8ba901fe7c978aad43b85a860c71b33bfbff2ff5 Gerrit-Change-Number: 57462 Gerrit-PatchSet: 6 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Fri, 01 Oct 2021 18:42:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/../cse: Avoid caching of CSE BAR
by Tim Wawrzynczak (Code Review) 01 Oct '21

01 Oct '21

Attention is currently required from: Furquan Shaikh, Subrata Banik, Angel Pons, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58062 ) Change subject: soc/intel/common/../cse: Avoid caching of CSE BAR ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/58062 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id4ecc9006d6323b7c9d7a6af1afa5cfe63d933e5 Gerrit-Change-Number: 58062 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 01 Oct 2021 18:42:23 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/adlrvp{p,m}: Enable dynamic GPIO PM
by Nick Vaccaro (Code Review) 01 Oct '21

01 Oct '21

Attention is currently required from: Maulik V Vaghela, Meera Ravindranath, Tim Wawrzynczak, Angel Pons. Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57411 ) Change subject: mb/intel/adlrvp{p,m}: Enable dynamic GPIO PM ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: Meera, I believe all comments need to be resolved first before this CL can be submitted as coreboot.org is not presenting me with a "submit" option for this CL even though it has CR +2 and Verified +1. -- To view, visit https://review.coreboot.org/c/coreboot/+/57411 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0b7b66b5525d8b80775ab7578ce6b12181af7882 Gerrit-Change-Number: 57411 Gerrit-PatchSet: 2 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Angel Pons <angel.pons(a)9elements.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Attention: Angel Pons <angel.pons(a)9elements.com> Gerrit-Comment-Date: Fri, 01 Oct 2021 18:41:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/../cse: Append `_MS` with CSE_DELAY_BOOT_TO_RO macro
by Tim Wawrzynczak (Code Review) 01 Oct '21

01 Oct '21

Attention is currently required from: Furquan Shaikh, Subrata Banik, Angel Pons, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58063 ) Change subject: soc/intel/common/../cse: Append `_MS` with CSE_DELAY_BOOT_TO_RO macro ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/58063 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4471e4553a081eaf5c8118e9600497a2b2437ac0 Gerrit-Change-Number: 58063 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 01 Oct 2021 18:41:53 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: acpi/acpigen_dptf: Add TPCH participant for dptf
by Felix Held (Code Review) 01 Oct '21

01 Oct '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/57924 ) Change subject: acpi/acpigen_dptf: Add TPCH participant for dptf ...................................................................... acpi/acpigen_dptf: Add TPCH participant for dptf Add TPCH as participant for dptf control functionality. BUG=b:198582766 BRANCH=None TEST=Build FW and test on brya0 board Change-Id: I17c0c6cfb7804dd2caa188acc93f1a63b47cab36 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57924 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/acpi/acpigen_dptf.c M src/include/acpi/acpigen_dptf.h 2 files changed, 3 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/acpi/acpigen_dptf.c b/src/acpi/acpigen_dptf.c index 3877daa..ea1efcf 100644 --- a/src/acpi/acpigen_dptf.c +++ b/src/acpi/acpigen_dptf.c @@ -70,6 +70,8 @@ return "TSR2"; case DPTF_TEMP_SENSOR_3: return "TSR3"; + case DPTF_TPCH: + return "TPCH"; default: return ""; } diff --git a/src/include/acpi/acpigen_dptf.h b/src/include/acpi/acpigen_dptf.h index b173bb8..de57adc 100644 --- a/src/include/acpi/acpigen_dptf.h +++ b/src/include/acpi/acpigen_dptf.h @@ -24,6 +24,7 @@ DPTF_TEMP_SENSOR_1, DPTF_TEMP_SENSOR_2, DPTF_TEMP_SENSOR_3, + DPTF_TPCH, DPTF_PARTICIPANT_COUNT, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/57924 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I17c0c6cfb7804dd2caa188acc93f1a63b47cab36 Gerrit-Change-Number: 57924 Gerrit-PatchSet: 6 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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coreboot-gerrit October 2021