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Change subject: mb/siemens/mc_ehl: Add variant_mainboard_final()
......................................................................
mb/siemens/mc_ehl: Add variant_mainboard_final()
In upcoming patches, we need mainboard specific adjustments.
Change-Id: Icf9d829b19b2d26a39ad34be4658064083e9da6d
Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com>
---
M src/mainboard/siemens/mc_ehl/mainboard.c
M src/mainboard/siemens/mc_ehl/variants/baseboard/include/baseboard/variants.h
2 files changed, 11 insertions(+), 0 deletions(-)
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Change subject: mb/google/guybrush: Add GPIO EC in RW to early GPIO tables
......................................................................
mb/google/guybrush: Add GPIO EC in RW to early GPIO tables
Before attempting another commit 6260bf71, ensure that guybrush programs
GPIO_EC_IN_RW (GPIO_91) as an early GPIO so that it can be read from in
verstage.
Signed-off-by: Hsuan Ting Chen <roccochen(a)chromium.org>
Change-Id: Ia6dcb225bbca89f3a873aad75a7d67625cdd3742
---
M src/mainboard/google/guybrush/variants/baseboard/gpio.c
1 file changed, 4 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/58192/1
diff --git a/src/mainboard/google/guybrush/variants/baseboard/gpio.c b/src/mainboard/google/guybrush/variants/baseboard/gpio.c
index 9878040..2fa5254 100644
--- a/src/mainboard/google/guybrush/variants/baseboard/gpio.c
+++ b/src/mainboard/google/guybrush/variants/baseboard/gpio.c
@@ -226,6 +226,10 @@
PAD_NF(GPIO_141, UART0_RXD, PULL_NONE),
/* UART0_TXD */
PAD_NF(GPIO_143, UART0_TXD, PULL_NONE),
+
+/* Support EC trusted */
+ /* SD_EX_PRSNT_L(Guybrush BoardID 1 only) / EC_IN_RW_OD */
+ PAD_GPI(GPIO_91, PULL_NONE),
};
/* Power-on timing requirements:
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Change subject: mb/siemens/mc_ehl2: Enable LPC ComB
......................................................................
mb/siemens/mc_ehl2: Enable LPC ComB
Enable LPC ComB on this mainboard.
TEST:
- Boot Linux and check with 'dmesg | grep tty'
Change-Id: I7ec58685a723c177df18144011934b206e6425d0
Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com>
---
M src/mainboard/siemens/mc_ehl/variants/mc_ehl2/Kconfig
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Change subject: mb/siemens/mc_ehl2: Disable INTEL_LPSS_UART_FOR_CONSOLE
......................................................................
mb/siemens/mc_ehl2: Disable INTEL_LPSS_UART_FOR_CONSOLE
This mainboard uses an eSPI-to-LPC bridge for console output. For this
reason, the internal LPSS UART must be disabled.
Change-Id: I86777cf719def331f4d257ddd94e9a87125ebce8
Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com>
---
M src/mainboard/siemens/mc_ehl/variants/mc_ehl2/Kconfig
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Change subject: mb/siemens/mc_ehl2: Adjust GPIOs
......................................................................
mb/siemens/mc_ehl2: Adjust GPIOs
Set the GPIOs according to the circuit diagram for this mainboard.
Change-Id: I19dc24a16ee9f533b45879bf60fb441e24018cc8
Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com>
---
M src/mainboard/siemens/mc_ehl/variants/mc_ehl2/gpio.c
1 file changed, 35 insertions(+), 54 deletions(-)
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Change subject: mb/siemens/mc_ehl2: Disable SATA Port 0
......................................................................
mb/siemens/mc_ehl2: Disable SATA Port 0
This mainboard has only SATA Port 1 available with no device sleep
feature.
Change-Id: I338833f2f9bcb407599cfc676ead0b8a9d7379bd
Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com>
---
M src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb
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Shawn C has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37441 )
Change subject: mb/supermicro/x11-lga1151v2-series: Add support for X11SCH-F
......................................................................
Patch Set 70:
(1 comment)
Patchset:
PS70:
Hi, I've tested it on x11sch-f with a TPMv2 chip (9670H) but found a reproducible bug:
1) The commits for x11sch-f seems missed a patch to enable TPMv2:
diff --git a/src/mainboard/supermicro/x11-lga1151v2-series/Kconfig b/src/mainboard/supermicro/x11-lga1151v2-series/Kconfig ✓
index 802d81fe45..a046828777 100644
--- a/src/mainboard/supermicro/x11-lga1151v2-series/Kconfig
+++ b/src/mainboard/supermicro/x11-lga1151v2-series/Kconfig
@@ -12,7 +12,7 @@ config BOARD_SUPERMICRO_BASEBOARD_X11_LGA1151V2_SERIES
select SUPERIO_ASPEED_AST2400
select SUPERIO_ASPEED_COMMON_PRE_RAM
select SUPERIO_ASPEED_HAS_UART_DELAY_WORKAROUND
-
+ select MAINBOARD_HAS_SPI_TPM
if BOARD_SUPERMICRO_BASEBOARD_X11_LGA1151V2_SERIES
config MAINBOARD_FAMILY
2) Enable the TPM options and build coreboot.
3) Plug in the TPM on the mainboard, the boot process will hang:
----------------------------------
coreboot-4.14-724-gac7779d32c-dirty--xXx Wed Jun 23 14:32:15 UTC 2021 bootblock starting (log level: 7)...
CPU: Intel(R) Xeon(R) E-2186G CPU @ 3.80GHz
CPU: ID 906ea, Coffeelake U0 (6+2), ucode: 000000dd
CPU: AES supported, TXT supported, VT supported
MCH: device id 3ec6 (rev 07) is Coffeelake-S WS(6+2)
PCH: device id a309 (rev 10) is Cannonlake-H C246
IGD: device id 3e96 (rev 00) is Coffeelake-S GT2
PMC: Using default GPE route.
misccfg_mask:fff000ff misccfg_value:43200
FMAP: Found "FLASH" version 1.1 at 0x1610000.
FMAP: base = 0xfe000000 size = 0x2000000 #areas = 4
FMAP: area COREBOOT found @ 1610200 (10419712 bytes)
CBFS: mcache @0xfef21c00 built for 19 files, used 0x418 of 0x4000 bytes
CBFS: Found 'fallback/romstage' @0x80 size 0xe030 in mcache @0xfef21c2c
TCPA: Clearing coreboot TCPA log
FMAP: area FMAP found @ 1610000 (512 bytes)
TPM: Digest of FMAP: FMAP to PCR 2 logged
CBFS: Found 'bootblock' @0x9e8600 size 0x77a0 in mcache @0xfef21fb4
FMAP: area COREBOOT found @ 1610200 (10419712 bytes)
TPM: Digest of FMAP: COREBOOT CBFS: bootblock to PCR 2 logged
CRTM initialized.
FMAP: area COREBOOT found @ 1610200 (10419712 bytes)
TPM: Digest of FMAP: COREBOOT CBFS: fallback/romstage to PCR 2 logged
BS: bootblock times (exec / console): total (unknown) / 108 ms
coreboot-4.14-724-gac7779d32c-dirty--xXx Wed Jun 23 14:32:15 UTC 2021 romstage starting (log level: 7)...
pm1_sts: 0000 pm1_en: 0000 pm1_cnt: 00001c00
gpe0_sts[0]: 00000000 gpe0_en[0]: 00000000
gpe0_sts[1]: 00000000 gpe0_en[1]: 00000000
gpe0_sts[2]: 00000000 gpe0_en[2]: 00000000
gpe0_sts[3]: 00000000 gpe0_en[3]: 00000000
TCO_STS: 0000 0004
GEN_PMCON: e0015008 00000200
GBLRST_CAUSE: 00000000 00000000
prev_sleep_state 5
FMAP: area COREBOOT found @ 1610200 (10419712 bytes)
CBFS: Found 'fspm.bin' @0x9adc0 size 0x88000 in mcache @0xfef21e4c
FMAP: area COREBOOT found @ 1610200 (10419712 bytes)
TPM: Digest of FMAP: COREBOOT CBFS: fspm.bin to PCR 2 logged
POST: 0x34
FMAP: area RW_MRC_CACHE found @ 1600000 (65536 bytes)
POST: 0x36
POST: 0x92
----------------------------------
The system will work without plug in the TPM. It seems a MRC bug in FSP?
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Change subject: mb/siemens/mc_ehl2: Enable SD-Card
......................................................................
mb/siemens/mc_ehl2: Enable SD-Card
This mainboard has SD slot available and therefore it should be enabled.
Change-Id: I0c97e2dc589bf6b89713a473925e42a20278f457
Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com>
---
M src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb
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Change subject: soc/qualcomm: Commonize AOP firmware support
......................................................................
Removed Code-Review+2 by Shelley Chen <shchen(a)google.com>
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