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Change subject: mb/siemens/mc_ehl2: Move RTC RX6110SA from SMBus to I2C2
......................................................................
Patch Set 3:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/58112/comment/d23574ac_739f6f74
PS2, Line 9: have
> has
Done
https://review.coreboot.org/c/coreboot/+/58112/comment/ce31a60d_826ec20f
PS2, Line 12:
> Tested RTC device how?
Done
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Change subject: mb/siemens/mc_ehl2: Update SPD for DDR4 devices
......................................................................
Patch Set 5:
(5 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/58111/comment/3016c7f4_07803544
PS1, Line 9: On this mainboard are Micron MT53D512M32D2NP modules. Since there are
: other DRAM modules on mc_ehl1, the SPD data file must be adjusted here
: accordingly.
> We do not use the traditional DRMA modules here but have memory down with different memory chips. […]
Done
Commit Message:
https://review.coreboot.org/c/coreboot/+/58111/comment/f2db5d1b_710f04e1
PS2, Line 9: Since other LPDDR4X modules with memory down are used on this board
> Yes, you are right, that is better. […]
Done
Commit Message:
https://review.coreboot.org/c/coreboot/+/58111/comment/fb5d1971_40082ad1
PS3, Line 7: mb/siemens/mc_ehl2: Set the suitable SPD data
> Update SPD for DDR4 devices
Done
https://review.coreboot.org/c/coreboot/+/58111/comment/f4b41fd0_4477abe1
PS3, Line 7: mb/siemens/mc_ehl2: Set the suitable SPD data
> Update SPD for DDR4 devices
Done
https://review.coreboot.org/c/coreboot/+/58111/comment/383ea6e3_ddb10e99
PS3, Line 11:
> Could you please add that to the commit message?
Done
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Hello build bot (Jenkins), Werner Zeh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/58111
to look at the new patch set (#5).
Change subject: mb/siemens/mc_ehl2: Update SPD for DDR4 devices
......................................................................
mb/siemens/mc_ehl2: Update SPD for DDR4 devices
Since this variant uses different DDR4 devices compared to mc_ehl1 in a
memory down configuration, the SPD data file must be adapted.
In a first configuration we use Micron MT53D512M32D2NP modules.
Following values were adjusted according to this board characteristic
and with help of Serial Presence Detect (SPD) for LPDDR3 and LPDDR4
SDRAM Modules JEDEC Spec and the Specification for this Micron modules
itself:
- SPD Byte 4 - only 4Gb density instead of 8Gb for mc_ehl1
- SPD Byte 5 - different Row and Column Address Bits
- SPD Byte 29/30 - 4Gb LPDDR4 needs 130ns tRFCab
- SPD Byte 31/32 - 4Gb LPDDR4 needs 60ns tRFCpb
Change-Id: Icb25f418952f0c96117140863d0d9c897d814ac5
Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com>
---
M src/mainboard/siemens/mc_ehl/variants/mc_ehl2/spd/mc_ehl2.spd.hex
1 file changed, 3 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/58111/5
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Hello build bot (Jenkins), Hsuan Ting Chen, Paul Menzel,
I'd like you to reexamine a change. Please visit
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Change subject: mb/google/guybrush: Build chromeos.c in verstage
......................................................................
mb/google/guybrush: Build chromeos.c in verstage
Before attempting another commit 6260bf71 (vboot_logic: Set
VB2_CONTEXT_EC_TRUSTED in verstage_main), ensure that guybrush builds
chromeos.c in verstage to call get_ec_is_trusted() in vboot
verstage_main().
Signed-off-by: Hsuan Ting Chen <roccochen(a)chromium.org>
Change-Id: Ic22519fdde1b18f6ce0237022dee02ca37181a74
---
M src/mainboard/google/guybrush/Makefile.inc
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git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/58193/3
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Change subject: mb/google/guybrush: Add GPIO EC in RW to early GPIO tables
......................................................................
mb/google/guybrush: Add GPIO EC in RW to early GPIO tables
Before attempting another commit 6260bf71 (vboot_logic: Set
VB2_CONTEXT_EC_TRUSTED in verstage_main), ensure that guybrush programs
GPIO_EC_IN_RW (GPIO_91) as an early GPIO so that it can be read from in
verstage.
Signed-off-by: Hsuan Ting Chen <roccochen(a)chromium.org>
Change-Id: Ia6dcb225bbca89f3a873aad75a7d67625cdd3742
---
M src/mainboard/google/guybrush/variants/baseboard/gpio.c
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Change subject: mb/siemens/mc_ehl2: Adjust Legacy IRQ routing for PCI devices
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/58172/comment/d085cf8e_df360b83
PS1, Line 17:
> Tested how? Maybe: Boot board and notice new info log message: […]
Done
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Change subject: mb/siemens/mc_ehl2: Adjust Legacy IRQ routing for PCI devices
......................................................................
Patch Set 2:
(1 comment)
File src/mainboard/siemens/mc_ehl/variants/mc_ehl2/mainboard.c:
https://review.coreboot.org/c/coreboot/+/58172/comment/ec94e372_8fc5283b
PS1, Line 12: */
> Please use one of the recommended multi-line comment styles [1]. […]
Done
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Change subject: mb/siemens/mc_ehl: Add variant_mainboard_final()
......................................................................
Patch Set 2: Code-Review+2
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Change subject: mb/siemens/mc_ehl2: Adjust Legacy IRQ routing for PCI devices
......................................................................
Patch Set 2: Code-Review+2
(1 comment)
File src/mainboard/siemens/mc_ehl/variants/mc_ehl2/mainboard.c:
https://review.coreboot.org/c/coreboot/+/58172/comment/de57a8da_b4e94643
PS1, Line 14: SOC2
> Thanks, could you please add that name to the commit message?
I guess this is nothing for the commit message, it is just an ASIC where the rest of the world is totally unaware of.
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