Attention is currently required from: Cliff Huang, Selma Bensaid, Tim Wawrzynczak, Rizwan Qureshi, Sridhar Siricilla, Bernardo Perez Priego, Patrick Rudolph.
Furquan Shaikh has uploaded a new patch set (#13) to the change originally created by Bernardo Perez Priego. ( https://review.coreboot.org/c/coreboot/+/57353 )
Change subject: soc/intel/common/cse: Add support for stitching CSE components
......................................................................
soc/intel/common/cse: Add support for stitching CSE components
This change adds support for allowing mainboards to stitch CSE
components during build time instead of adding a pre-built CSE
binary. Several Kconfig options are added to allow mainboard to
provide the file names for different CSE region components. This makes
use of the newly added cse_serger and cse_fpt tools to create
following partitions:
1. BP1 - RO
2. BP2 - RW
3. Layout
In addition to this, it accepts CSE data partition as an input using
Kconfig CSE_DATA_FILE. All these partitions are then assembled
together as per the following mainboard FMAP regions:
1. BP1(RO) : CSE_RO
2. BP2(RW) : CSE_RW
3. Layout : CSE_LAYOUT
4. Data : CSE_DATA
Finally, it generates the target $(OBJ_ME_BIN) which is used to put
together the binary in final coreboot.rom image.
Several helper functions are added to soc/intel/Makefile.inc to allow
SoCs to define which components use:
1. Decomposed files: Files decomposed from Intel release CSE binary in
FPT format.
2. Input files: Mainboard provided input files using corresponding
Kconfigs.
3. Dummy: Components that are required to have dummy entries in
BPDT header.
These helpers are added to soc/intel/Makefile.inc to ensure that the
functions are defined by the time the invocations are encountered in
SoC Makefile.inc.
Change-Id: I8359cd49ad256703285e55bc4319c6e9c9fccb67
Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com>
Signed-off-by: Furquan Shaikh <furquan(a)google.com>
---
A src/soc/intel/Makefile.inc
M src/soc/intel/common/block/cse/Kconfig
M src/soc/intel/common/block/cse/Makefile.inc
3 files changed, 170 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/57353/13
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Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57628 )
Change subject: lib/thread: Switch to using CPU_INFO_V2
......................................................................
Patch Set 7:
(1 comment)
File src/lib/thread.c:
https://review.coreboot.org/c/coreboot/+/57628/comment/b27cd4ff_0cc4ca69
PS7, Line 49: return cpu_info()->thread;
> (Sorry for being late, patch itself looks fine to me, just have some furthergoing theoretical questi […]
You bring up a very good point.
x86 has PARALLEL_MP_AP_WORK: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/thi…
But I don't think it really gets used.
We already have boot_cpu(): https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/thi…
So we could just switch to using that. This will allow us to keep cpu_info() as a ramstage only construct.
Thanks for the suggestion. I'll get a CL pushed up.
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Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58150 )
Change subject: Documentation: Explain how to join Slack
......................................................................
Documentation: Explain how to join Slack
Change-Id: I6a4d5011ea47576c9a459f20e0b368cff8a326c2
Signed-off-by: Patrick Georgi <pgeorgi(a)google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58150
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Angel Pons <th3fanbus(a)gmail.com>
Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org>
---
M Documentation/community/forums.md
1 file changed, 3 insertions(+), 1 deletion(-)
Approvals:
build bot (Jenkins): Verified
Paul Menzel: Looks good to me, but someone else must approve
Angel Pons: Looks good to me, approved
diff --git a/Documentation/community/forums.md b/Documentation/community/forums.md
index 2ad69e1..91cadca 100644
--- a/Documentation/community/forums.md
+++ b/Documentation/community/forums.md
@@ -17,7 +17,9 @@
also bridged to [Matrix](https://matrix.to/#/#coreboot:libera.chat) and a
[Discord](https://discord.gg/JqT8NM5Zbg) presence. You can also find us on
[OSF Slack](https://osfw.slack.com/), which has channels on many open source
-firmware related topics.
+firmware related topics. Slack requires that people come from specific domains
+or are explicitly invited. To work around that, there's an
+[invite bot](https://slack.osfw.dev/) to let people in.
## Fortnightly coreboot leadership meeting
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Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58188 )
Change subject: nb/intel/sandybridge: Populate meminfo when using MRC
......................................................................
Patch Set 5:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/58188/comment/af93cb0b_cc2ac821
PS4, Line 13: needed,
> move to next line
Done
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Hello build bot (Jenkins), Paul Menzel, Angel Pons, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/58188
to look at the new patch set (#5).
Change subject: nb/intel/sandybridge: Populate meminfo when using MRC
......................................................................
nb/intel/sandybridge: Populate meminfo when using MRC
Populate a memory_info struct with PEI and SPD data, in order to inject
the CBMEM_INFO table necessary to populate a type17 SMBIOS table.
On Broadwell, this is done by the MRC binary, but the older Sandy Bridge
MRC binary doesn't populate the pei_data struct with all the info
needed, so we have to pull it from the SPD.
Some values are hardcoded based on platform specifications.
Change-Id: I15e00a01121150b778cfa684b9147d0cac97beb8
Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com>
---
M src/northbridge/intel/sandybridge/raminit.h
M src/northbridge/intel/sandybridge/raminit_mrc.c
2 files changed, 77 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/58188/5
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