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Hello Bora Guvendik, build bot (Jenkins), Selma Bensaid, Hsuan-ting Chen, Tim Wawrzynczak, Bernardo Perez Priego,
I'd like you to reexamine a change. Please visit
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Change subject: mb/adlrvp: Add hook function to return EC in RW status
......................................................................
mb/adlrvp: Add hook function to return EC in RW status
EC_IN_RW signal from EC GPIO is connected to GPIO E7
of SOC. The function reads this GPIO to check if EC is in
RW (un trusted) or RO (trusted)
Branch=none
Bug=none
Test=Issue manual recovery and confirm DUT is entering recovery mode
on ADL-M RVP
Signed-off-by: Anil Kumar <anil.kumar.k(a)intel.com>
Change-Id: I20804db450ab0b3ebe19c51ba2b294a0137d81a7
---
M src/mainboard/intel/adlrvp/chromeos.c
M src/mainboard/intel/adlrvp/early_gpio.c
M src/mainboard/intel/adlrvp/early_gpio_m.c
M src/mainboard/intel/adlrvp/gpio.c
M src/mainboard/intel/adlrvp/include/baseboard/gpio.h
5 files changed, 19 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/58099/7
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Sean Rhodes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58149 )
Change subject: soc/intel/*/me.c: Check more than PCI interface for printing ME info
......................................................................
Patch Set 1:
(1 comment)
File src/soc/intel/alderlake/me.c:
https://review.coreboot.org/c/coreboot/+/58149/comment/808f38a6_90c611c8
PS1, Line 103: !cse_is_hfs1_cws_normal() ||
: !cse_is_hfs1_com_normal() ||
: !cse_is_hfs1_com_soft_temp_disable())
: return;
> I disagree here, this is important status information to have on every boot, especially when it's no […]
I think you agree - unless my brain stopped working and my logic is wrong...
Currently, it won't print the status if the PCI device is not enabled - I think that's irrelevant as that's not how we talk to it.
Removing things doesn't go down too well in coreboot, so I thought the compromise would be to print the status if it's in a known state or the PCI device is enabled.
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Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58198 )
Change subject: mb/google/guybrush: Add PCIe Reset GPIO69 to SD DXIO Descriptor
......................................................................
Patch Set 1:
(1 comment)
File src/mainboard/google/guybrush/port_descriptors.c:
https://review.coreboot.org/c/coreboot/+/58198/comment/41e59932_24db6ead
PS1, Line 54: NVME
Do we need to specify the NVMe pin as well now?
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Change subject: vc/amd/fsp/cezanne: Update Cezanne FSP-M UPD definition
......................................................................
Patch Set 2: Code-Review+2
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Change subject: soc/intel/*/me.c: Check more than PCI interface for printing ME info
......................................................................
Patch Set 1:
(1 comment)
File src/soc/intel/alderlake/me.c:
https://review.coreboot.org/c/coreboot/+/58149/comment/2e648d7c_0ddfd28e
PS1, Line 103: !cse_is_hfs1_cws_normal() ||
: !cse_is_hfs1_com_normal() ||
: !cse_is_hfs1_com_soft_temp_disable())
: return;
I disagree here, this is important status information to have on every boot, especially when it's not in normal states! 😊
If you really need to skip dumping these registers, then perhaps the new CMOS option you added would work here? was it `me_state` ?
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Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57140 )
Change subject: soc/tigerlake: Make IO decode / enable register configurable
......................................................................
Patch Set 19:
(1 comment)
Patchset:
PS19:
> I just wanted to show that it can be much simpler. For instance, we could […]
I absolutely agree 😊
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Hello Felix Singer, Lance Zhao, build bot (Jenkins), Matt Delco, Nico Huber, Furquan Shaikh, Paul Menzel, Tim Wawrzynczak, Ravindra, Subrata Banik, Lean Sheng Tan, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
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Change subject: soc/intel/{icl,tgl,jsl,ehl}: enable ACPI CPPC entries
......................................................................
soc/intel/{icl,tgl,jsl,ehl}: enable ACPI CPPC entries
Enable CPPC entries generation, needed for Intel SpeedShift.
This can be tested by checking sysfs in Linux:
$ grep . /sys/devices/system/cpu/cpu?/acpi_cppc/*perf
The output should look like this, while the values may differ:
/sys/devices/system/cpu/cpu0/acpi_cppc/highest_perf:28
/sys/devices/system/cpu/cpu0/acpi_cppc/lowest_nonlinear_perf:5
/sys/devices/system/cpu/cpu0/acpi_cppc/lowest_perf:1
/sys/devices/system/cpu/cpu0/acpi_cppc/nominal_perf:24
/sys/devices/system/cpu/cpu1/acpi_cppc/highest_perf:28
/sys/devices/system/cpu/cpu1/acpi_cppc/lowest_nonlinear_perf:5
...
Change-Id: I910b4e17d4044f1bf1ecfa0643ac62fc7a8cb51b
Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de>
---
M src/soc/intel/elkhartlake/Kconfig
M src/soc/intel/icelake/Kconfig
M src/soc/intel/jasperlake/Kconfig
M src/soc/intel/tigerlake/Kconfig
4 files changed, 4 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/47543/27
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Hello Felix Singer, build bot (Jenkins), Raul Rangel, Furquan Shaikh, Paul Menzel, Angel Pons, Patrick Rudolph, Lance Zhao, Jason Glenesk, Nico Huber, Marshall Dawson, Tim Wawrzynczak, Tim Wawrzynczak, Felix Held,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#5).
Change subject: acpigen,soc/amd/cezanne,intel/{common,skl}: rework CPPC table passing
......................................................................
acpigen,soc/amd/cezanne,intel/{common,skl}: rework CPPC table passing
Instead of passing around a magic struct with embedded version, use
pointers and pass the CPPC version directly to the ACPI generator.
Change-Id: I26c5e80c2a16a50ed73245c7c32d61b17e45c22a
Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de>
---
M src/acpi/acpigen.c
M src/cpu/intel/common/common.h
M src/cpu/intel/common/common_init.c
M src/include/acpi/acpi.h
M src/include/acpi/acpigen.h
M src/soc/amd/cezanne/cppc.c
M src/soc/amd/cezanne/include/soc/cppc.h
M src/soc/intel/common/block/acpi/acpi.c
M src/soc/intel/skylake/acpi.c
9 files changed, 99 insertions(+), 108 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/58118/5
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Hello Felix Singer, build bot (Jenkins), Raul Rangel, Furquan Shaikh, Paul Menzel, Angel Pons, Subrata Banik, Kyösti Mälkki, Patrick Rudolph, Lance Zhao, Jason Glenesk, Matt Delco, Nico Huber, Marshall Dawson, Tim Wawrzynczak, Tim Wawrzynczak, Felix Held,
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Change subject: acpigen,soc/amd,cpu/intel: rework static DWORD for CPPC table
......................................................................
acpigen,soc/amd,cpu/intel: rework static DWORD for CPPC table
Some elements in the ACPI CPPC table allow static DWORDs. Instead of
using a fake register resource, use a tagged union with the two types
"register" and "DWORD" and respective macros for CPPC table entries.
Change-Id: Ib853261b5c0ea87ae2424fed188f2d1872be9a06
Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de>
---
M src/acpi/acpigen.c
M src/cpu/intel/common/common.h
M src/cpu/intel/common/common_init.c
M src/include/acpi/acpigen.h
M src/soc/amd/cezanne/cppc.c
M src/soc/amd/cezanne/include/soc/cppc.h
6 files changed, 73 insertions(+), 57 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/57886/8
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https://review.coreboot.org/c/coreboot/+/58197
to look at the new patch set (#2).
Change subject: vc/amd/fsp/cezanne: Update Cezanne FSP-M UPD definition
......................................................................
vc/amd/fsp/cezanne: Update Cezanne FSP-M UPD definition
Update UPD to include option for FSP to de-assert PCIe reset GPIOs.
This is already off by default with a newer FSP (unused UPD space
is all 0s). This update bumps PcdImageRevisionBuildNumber to 2
BUG=b:199780346
TEST=Verify toggling this value is reflected in FSP
Change-Id: I0dee05fb0a650f026c2f09581117fa7fb5f6a90a
Signed-off-by: Matt Papageorge <matthewpapa07(a)gmail.com>
---
M src/vendorcode/amd/fsp/cezanne/FspmUpd.h
1 file changed, 2 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/58197/2
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I0dee05fb0a650f026c2f09581117fa7fb5f6a90a
Gerrit-Change-Number: 58197
Gerrit-PatchSet: 2
Gerrit-Owner: Matt Papageorge <matthewpapa07(a)gmail.com>
Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com>
Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com>
Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org>
Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com>
Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org>
Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com>
Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-MessageType: newpatchset