coreboot-gerrit October 2021

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Change in coreboot[master]: arch/x86,cpu/x86,lib/thread: Remove usage of cpu_info from lib/thread
by Raul Rangel (Code Review) 09 Oct '21

09 Oct '21

Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58199 ) Change subject: arch/x86,cpu/x86,lib/thread: Remove usage of cpu_info from lib/thread ...................................................................... arch/x86,cpu/x86,lib/thread: Remove usage of cpu_info from lib/thread We only ever start and execute threads on the BSP. By explicitly checking to see if the CPU is the BSP we can remove the dependency on cpu_info. With this change we can in theory enable threads in bootblock and romstage. BUG=b:194391185, b:179699789 TEST=Boot guybrush to OS and verify coop multithreading still works Suggested-by: Julius Werner <jwerner(a)chromium.org> Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: Iea4622d52c36d529e100b7ea55f32c334acfdf3e --- M src/arch/x86/include/arch/cpu.h M src/cpu/x86/cpu_info.S.inc M src/cpu/x86/lapic/lapic_cpu_init.c M src/cpu/x86/mp_init.c M src/include/thread.h M src/lib/thread.c 6 files changed, 14 insertions(+), 24 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/58199/1 diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h index 8e96fae..9a3b63d 100644 --- a/src/arch/x86/include/arch/cpu.h +++ b/src/arch/x86/include/arch/cpu.h @@ -231,9 +231,6 @@ struct cpu_info { struct device *cpu; size_t index; -#if CONFIG(COOP_MULTITASKING) - struct thread *thread; -#endif }; /* diff --git a/src/cpu/x86/cpu_info.S.inc b/src/cpu/x86/cpu_info.S.inc index dffd1bc..fc3e26d 100644 --- a/src/cpu/x86/cpu_info.S.inc +++ b/src/cpu/x86/cpu_info.S.inc @@ -2,9 +2,6 @@ /* Push struct cpu_info */ .macro push_cpu_info index=$0 -#if CONFIG(COOP_MULTITASKING) - push $0 /* *thread */ -#endif push \index /* index */ push $0 /* *cpu */ .endm diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c index e141ad8..d463c69 100644 --- a/src/cpu/x86/lapic/lapic_cpu_init.c +++ b/src/cpu/x86/lapic/lapic_cpu_init.c @@ -253,7 +253,6 @@ info->index = index; info->cpu = cpu; cpu_add_map_entry(info->index); - thread_init_cpu_info_non_bsp(info); /* Advertise the new stack and index to start_cpu */ secondary_stack = stack_top; diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index 123b2b5..497ed3c 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -193,7 +193,6 @@ info->cpu = cpus_dev[cpu]; cpu_add_map_entry(info->index); - thread_init_cpu_info_non_bsp(info); /* Fix up APIC id with reality. */ info->cpu->path.apic.apic_id = lapicid(); diff --git a/src/include/thread.h b/src/include/thread.h index cb085b5..62c6283 100644 --- a/src/include/thread.h +++ b/src/include/thread.h @@ -73,11 +73,6 @@ void thread_mutex_lock(struct thread_mutex *mutex); void thread_mutex_unlock(struct thread_mutex *mutex); -static inline void thread_init_cpu_info_non_bsp(struct cpu_info *ci) -{ - ci->thread = NULL; -} - /* Architecture specific thread functions. */ asmlinkage void switch_to_thread(uintptr_t new_stack, uintptr_t *saved_stack); /* Set up the stack frame for a new thread so that a switch_to_thread() call @@ -96,8 +91,6 @@ } static inline void thread_coop_enable(void) {} static inline void thread_coop_disable(void) {} -struct cpu_info; -static inline void thread_init_cpu_info_non_bsp(struct cpu_info *ci) { } static inline void thread_mutex_lock(struct thread_mutex *mutex) {} diff --git a/src/lib/thread.c b/src/lib/thread.c index 9008147e..8cc2637 100644 --- a/src/lib/thread.c +++ b/src/lib/thread.c @@ -4,10 +4,10 @@ #include <stddef.h> #include <stdint.h> #include <stdlib.h> -#include <arch/cpu.h> #include <bootstate.h> #include <commonlib/bsd/compiler.h> #include <console/console.h> +#include <smp/node.h> #include <thread.h> #include <timer.h> @@ -27,17 +27,24 @@ static struct thread *runnable_threads; static struct thread *free_threads; +static struct thread *active_thread; + static inline int thread_can_yield(const struct thread *t) { return (t != NULL && t->can_yield > 0); } +static inline void set_current_thread(struct thread *t) +{ + active_thread = t; +} + static inline struct thread *current_thread(void) { - if (!initialized) + if (!initialized || !boot_cpu()) return NULL; - return cpu_info()->thread; + return active_thread; } static inline int thread_list_empty(struct thread **list) @@ -108,7 +115,6 @@ static void schedule(struct thread *t) { struct thread *current = current_thread(); - struct cpu_info *ci = cpu_info(); /* If t is NULL need to find new runnable thread. */ if (t == NULL) { @@ -123,7 +129,7 @@ if (t->handle) t->handle->state = THREAD_STARTED; - ci->thread = t; + set_current_thread(t); switch_to_thread(t->stack_current, &current->stack_current); } @@ -239,18 +245,17 @@ int i; struct thread *t; u8 *stack_top; - struct cpu_info *ci; - if (initialized) + if (initialized || !boot_cpu()) return; t = &all_threads[0]; - ci = cpu_info(); - ci->thread = t; t->stack_orig = (uintptr_t)NULL; /* We never free the main thread */ t->id = 0; t->can_yield = 1; + set_current_thread(t); + stack_top = &thread_stacks[CONFIG_STACK_SIZE]; for (i = 1; i < TOTAL_NUM_THREADS; i++) { t = &all_threads[i]; -- To view, visit https://review.coreboot.org/c/coreboot/+/58199 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iea4622d52c36d529e100b7ea55f32c334acfdf3e Gerrit-Change-Number: 58199 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/*/me.c: Check more than PCI interface for printing ME info
by Sean Rhodes (Code Review) 09 Oct '21

09 Oct '21

Attention is currently required from: Tim Wawrzynczak, Patrick Rudolph. Sean Rhodes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58149 ) Change subject: soc/intel/*/me.c: Check more than PCI interface for printing ME info ...................................................................... Patch Set 1: (1 comment) File src/soc/intel/alderlake/me.c: https://review.coreboot.org/c/coreboot/+/58149/comment/9fc51a17_6f2cbd6b PS1, Line 103: !cse_is_hfs1_cws_normal() || : !cse_is_hfs1_com_normal() || : !cse_is_hfs1_com_soft_temp_disable()) : return; > I think you agree - unless my brain stopped working and my logic is wrong... […] Just realised your point! Think this would account for that? ``` if (!is_cse_enabled() && (!cse_is_hfs1_cws_normal() || !cse_is_hfs1_com_normal() || !cse_is_hfs1_com_soft_temp_disable())) ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/58149 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6ad1215cceb75651b7890f3bab5df39b1b72ecf6 Gerrit-Change-Number: 58149 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 08 Oct 2021 20:14:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sean Rhodes <admin(a)starlabs.systems> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/guybrush: Build chromeos.c in verstage
by Karthik Ramasubramanian (Code Review) 09 Oct '21

09 Oct '21

Attention is currently required from: Hsuan Ting Chen, Hsuan-ting Chen, Paul Menzel. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58193 ) Change subject: mb/google/guybrush: Build chromeos.c in verstage ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/58193 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic22519fdde1b18f6ce0237022dee02ca37181a74 Gerrit-Change-Number: 58193 Gerrit-PatchSet: 3 Gerrit-Owner: Hsuan-ting Chen <roccochen(a)google.com> Gerrit-Reviewer: Hsuan Ting Chen <roccochen(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hsuan Ting Chen <roccochen(a)chromium.org> Gerrit-Attention: Hsuan-ting Chen <roccochen(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Fri, 08 Oct 2021 19:49:56 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/guybrush: Add GPIO EC in RW to early GPIO tables
by Karthik Ramasubramanian (Code Review) 09 Oct '21

09 Oct '21

Attention is currently required from: Hsuan Ting Chen, Hsuan-ting Chen. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58192 ) Change subject: mb/google/guybrush: Add GPIO EC in RW to early GPIO tables ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/58192 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia6dcb225bbca89f3a873aad75a7d67625cdd3742 Gerrit-Change-Number: 58192 Gerrit-PatchSet: 2 Gerrit-Owner: Hsuan-ting Chen <roccochen(a)google.com> Gerrit-Reviewer: Hsuan Ting Chen <roccochen(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hsuan Ting Chen <roccochen(a)chromium.org> Gerrit-Attention: Hsuan-ting Chen <roccochen(a)google.com> Gerrit-Comment-Date: Fri, 08 Oct 2021 19:49:25 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/guybrush: Build chromeos.c in verstage
by Raul Rangel (Code Review) 09 Oct '21

09 Oct '21

Attention is currently required from: Hsuan Ting Chen, Hsuan-ting Chen, Paul Menzel. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58193 ) Change subject: mb/google/guybrush: Build chromeos.c in verstage ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/58193 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic22519fdde1b18f6ce0237022dee02ca37181a74 Gerrit-Change-Number: 58193 Gerrit-PatchSet: 3 Gerrit-Owner: Hsuan-ting Chen <roccochen(a)google.com> Gerrit-Reviewer: Hsuan Ting Chen <roccochen(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hsuan Ting Chen <roccochen(a)chromium.org> Gerrit-Attention: Hsuan-ting Chen <roccochen(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Fri, 08 Oct 2021 19:45:03 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/guybrush: Add GPIO EC in RW to early GPIO tables
by Raul Rangel (Code Review) 09 Oct '21

09 Oct '21

Attention is currently required from: Hsuan Ting Chen, Hsuan-ting Chen, Karthik Ramasubramanian. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58192 ) Change subject: mb/google/guybrush: Add GPIO EC in RW to early GPIO tables ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/58192 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia6dcb225bbca89f3a873aad75a7d67625cdd3742 Gerrit-Change-Number: 58192 Gerrit-PatchSet: 2 Gerrit-Owner: Hsuan-ting Chen <roccochen(a)google.com> Gerrit-Reviewer: Hsuan Ting Chen <roccochen(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hsuan Ting Chen <roccochen(a)chromium.org> Gerrit-Attention: Hsuan-ting Chen <roccochen(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Fri, 08 Oct 2021 19:43:15 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: util/cse_serger: Add a new tool for stitching CSE components
by build bot (Jenkins) (Code Review) 09 Oct '21

09 Oct '21

Attention is currently required from: Cliff Huang, Martin Roth, Tim Wawrzynczak, Rizwan Qureshi, Sridhar Siricilla, Bernardo Perez Priego, Andrew McRae. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55503 ) Change subject: util/cse_serger: Add a new tool for stitching CSE components ...................................................................... Patch Set 21: Verified+1 (3 comments) File util/cbfstool/bpdt_formats/subpart_entry_1.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130067): https://review.coreboot.org/c/coreboot/+/55503/comment/ad4702a2_c32136c5 PS21, Line 49: printf("%-25s%-25s%-25s%-25s%-25s%-25s\n", "Entry #", "Name", "Offset", "Huffman Compressed?", line over 96 characters File util/cbfstool/cse_serger.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130067): https://review.coreboot.org/c/coreboot/+/55503/comment/13fa4008_6b1e8ed2 PS21, Line 272: ERROR("Part(%d) exceeds file size. Part offset=0x%x, Part size = 0x%x, File size = 0x%zx\n", line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130067): https://review.coreboot.org/c/coreboot/+/55503/comment/171b2f44_22b56713 PS21, Line 923: if (c < LONGOPT_START) { braces {} are not necessary for any arm of this statement -- To view, visit https://review.coreboot.org/c/coreboot/+/55503 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I90dd809b47fd16afdc80e66431312721082496aa Gerrit-Change-Number: 55503 Gerrit-PatchSet: 21 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Andrew McRae <amcrae(a)google.com> Gerrit-Reviewer: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Reviewer: Bernardo Perez Priego <bernardo.perez.priego(a)intel.corp-partner.google.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Attention: Bernardo Perez Priego <bernardo.perez.priego(a)intel.corp-partner.google.com> Gerrit-Attention: Andrew McRae <amcrae(a)google.com> Gerrit-Comment-Date: Fri, 08 Oct 2021 19:40:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/cse: Reorganize firmware update checks for CSE Lite
by Sridhar Siricilla (Code Review) 09 Oct '21

09 Oct '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Patrick Rudolph. Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58157 ) Change subject: soc/intel/common/cse: Reorganize firmware update checks for CSE Lite ...................................................................... Patch Set 5: (1 comment) File src/soc/intel/common/block/cse/cse_lite.c: https://review.coreboot.org/c/coreboot/+/58157/comment/c9126773_2518c2e6 PS5, Line 651: (status == CSE_UPDATE_CORRUPTED coreboot need not send DATA CLEAR command when there is an UPDATE CORRUPTED.We can drop the condition. -- To view, visit https://review.coreboot.org/c/coreboot/+/58157 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iabecab8e373e65a11ba7fe1bfc125467571a0588 Gerrit-Change-Number: 58157 Gerrit-PatchSet: 5 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 08 Oct 2021 19:37:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: purism/librem_bdw: add support for ACPI brightness controls
by Michael Niewöhner (Code Review) 09 Oct '21

09 Oct '21

Attention is currently required from: Matt DeVillier. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58187 ) Change subject: purism/librem_bdw: add support for ACPI brightness controls ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/58187 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I27d04655adcd4a5dd42b025cfccb508cfd7aaeae Gerrit-Change-Number: 58187 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Comment-Date: Fri, 08 Oct 2021 19:32:51 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: vc/amd/fsp/cezanne: Update Cezanne FSP-M UPD definition
by Karthik Ramasubramanian (Code Review) 09 Oct '21

09 Oct '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Matt Papageorge, Felix Held. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58197 ) Change subject: vc/amd/fsp/cezanne: Update Cezanne FSP-M UPD definition ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/58197/comment/4f048d43_e1004db8 PS2, Line 15: Nit: Cq-Depend: chrome-internal:4170351 -- To view, visit https://review.coreboot.org/c/coreboot/+/58197 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0dee05fb0a650f026c2f09581117fa7fb5f6a90a Gerrit-Change-Number: 58197 Gerrit-PatchSet: 2 Gerrit-Owner: Matt Papageorge <matthewpapa07(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Matt Papageorge <matthewpapa07(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 08 Oct 2021 19:29:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit October 2021