Raul Rangel has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/58205 )
Change subject: cpu/x86/cpu_info.S: Remove ebx save/restore
......................................................................
cpu/x86/cpu_info.S: Remove ebx save/restore
The push/pop of %ebx was only added because smm_stub saves the canary
value in it. Now that we no longer use cpu_info in smm, we no longer
need to save the register.
BUG=b:179699789
TEST=Boot guybrush to the OS
Signed-off-by: Raul E Rangel <rrangel(a)chromium.org>
Change-Id: I554dbe016db8b1c61246c8ffc7fa252b2542ba92
---
M src/cpu/x86/cpu_info.S.inc
1 file changed, 1 insertion(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/58205/2
--
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Gerrit-Change-Id: I554dbe016db8b1c61246c8ffc7fa252b2542ba92
Gerrit-Change-Number: 58205
Gerrit-PatchSet: 2
Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org>
Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-MessageType: newpatchset
Raul Rangel has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/58204 )
Change subject: cpu/x86/smm/smm_stub: Remove cpu_info
......................................................................
cpu/x86/smm/smm_stub: Remove cpu_info
Now that cpu_info() is no longer used by COOP_MULTITASKING, we no
longer need to setup cpu_info in SMM. When using CPU_INFO_V2, if
something does manage to call cpu_info() while executing in SMM mode, the
%gs segment is disabled, so it will generate an exception.
BUG=b:179699789
TEST=Boot guybrush to OS with threads enabled
Signed-off-by: Raul E Rangel <rrangel(a)chromium.org>
Change-Id: Id64f32cc63082880a92dab6deb473431b2238cd0
---
M src/cpu/x86/smm/smm_stub.S
1 file changed, 1 insertion(+), 31 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/58204/2
--
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Gerrit-Change-Id: Id64f32cc63082880a92dab6deb473431b2238cd0
Gerrit-Change-Number: 58204
Gerrit-PatchSet: 2
Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org>
Gerrit-MessageType: newpatchset
Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58205 )
Change subject: cpu/x86/cpu_info.S: Remove ebx save/restore
......................................................................
cpu/x86/cpu_info.S: Remove ebx save/restore
The push/pop of %ebx was only added because smm_stub saves the canary
value in it. Now that we no longer use cpu_info in smm, we no longer
need to save the register.
BUG=b:179699789
TEST=Boot guybrush to the OS
Signed-off-by: Raul E Rangel <rrangel(a)chromium.org>
Change-Id: I554dbe016db8b1c61246c8ffc7fa252b2542ba92
---
M src/cpu/x86/cpu_info.S.inc
1 file changed, 1 insertion(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/58205/1
diff --git a/src/cpu/x86/cpu_info.S.inc b/src/cpu/x86/cpu_info.S.inc
index fc3e26d..9ffdd84 100644
--- a/src/cpu/x86/cpu_info.S.inc
+++ b/src/cpu/x86/cpu_info.S.inc
@@ -28,12 +28,11 @@
* @desc_index: Index of the descriptor in the table. Defaults to 0. Must be a
* register if specified.
*
- * Clobbers %eax.
+ * Clobbers %eax, %ebx.
*/
.macro set_segment_descriptor_base desc_array:req, base:req, desc_index
mov \base, %eax
- push %ebx /* preserve ebx */
mov \desc_array, %ebx
.ifb \desc_index
@@ -50,5 +49,4 @@
movb %al, 7(%ebx, \desc_index, 8)
.endif
- pop %ebx
.endm
--
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Gerrit-Branch: master
Gerrit-Change-Id: I554dbe016db8b1c61246c8ffc7fa252b2542ba92
Gerrit-Change-Number: 58205
Gerrit-PatchSet: 1
Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org>
Gerrit-MessageType: newchange
Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58204 )
Change subject: cpu/x86/smm/smm_stub: Remove cpu_info
......................................................................
cpu/x86/smm/smm_stub: Remove cpu_info
Now that we cpu_info() is no longer used by COOP_MULTITASKING, we no
longer need to setup cpu_info in SMM. When using CPU_INFO_V2, if
something does manage to call cpu_info() while executing in SMM mode, the
%gs segment is disabled, so it will generate an exception.
BUG=b:179699789
TEST=Boot guybrush to OS with threads enabled
Signed-off-by: Raul E Rangel <rrangel(a)chromium.org>
Change-Id: Id64f32cc63082880a92dab6deb473431b2238cd0
---
M src/cpu/x86/smm/smm_stub.S
1 file changed, 1 insertion(+), 31 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/58204/1
diff --git a/src/cpu/x86/smm/smm_stub.S b/src/cpu/x86/smm/smm_stub.S
index e409983..c83839c 100644
--- a/src/cpu/x86/smm/smm_stub.S
+++ b/src/cpu/x86/smm/smm_stub.S
@@ -9,7 +9,6 @@
* found in smm.h.
*/
-#include <cpu/x86/cpu_info.S.inc>
#include <cpu/x86/cr.h>
#include <cpu/x86/msr.h>
#include <cpu/x86/lapic_def.h>
@@ -83,21 +82,8 @@
/* gdt selector 0x20 tss segment */
.word 0xffff, 0x0000
.byte 0x00, 0x8b, 0x80, 0x00
-
-#if CONFIG(CPU_INFO_V2)
-per_cpu_segment_descriptors:
- .rept CONFIG_MAX_CPUS
- /* selgdt 0x28, flat data segment */
- .word 0xffff, 0x0000
- .byte 0x00, 0x93, 0xcf, 0x00
- .endr
-#endif /* CPU_INFO_V2 */
smm_relocate_gdt_end:
-#if CONFIG(CPU_INFO_V2)
-.set per_cpu_segment_selector, per_cpu_segment_descriptors - smm_relocate_gdt
-#endif /* CPU_INFO_V2 */
-
.align 4
.code32
.global smm_trampoline32
@@ -109,7 +95,7 @@
movw %ax, %ss
xor %ax, %ax /* zero out the gs and fs segment index */
movw %ax, %fs
- movw %ax, %gs /* Will be used for cpu_info */
+ movw %ax, %gs /* Used by cpu_info in ramstage */
/* The CPU number is calculated by reading the initial APIC id. Since
* the OS can manipulate the APIC id use the non-changing cpuid result
@@ -167,22 +153,6 @@
movl $0, 4(%ebx)
#endif
-#if CONFIG(CPU_INFO_V2)
- push_cpu_info index=%ecx
- push_per_cpu_segment_data
-
- /*
- * Update the AP's per_cpu_segment_descriptor to point to the
- * per_cpu_segment_data that was allocated on the stack.
- */
- set_segment_descriptor_base $per_cpu_segment_descriptors, %esp, %ecx
-
- mov %ecx, %eax
- shl $3, %eax /* The index is << 3 in the segment selector */
- add $per_cpu_segment_selector, %eax
- mov %eax, %gs
-#endif
-
/* Create stack frame by pushing a NULL stack base pointer */
pushl $0x0
mov %esp, %ebp
--
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Gerrit-Change-Id: Id64f32cc63082880a92dab6deb473431b2238cd0
Gerrit-Change-Number: 58204
Gerrit-PatchSet: 1
Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org>
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Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58203 )
Change subject: arch/x86/assembly_entry: Remove cpu_info
......................................................................
arch/x86/assembly_entry: Remove cpu_info
Since cpu_info() is no longer required to use threads, we no longer need
to initialize it in romstage or earlier.
BUG=b:179699789
TEST=Boot guybrush to OS
Signed-off-by: Raul E Rangel <rrangel(a)chromium.org>
Change-Id: I615b718e9f035ca68ecca9f57d7f4121db0c83b0
---
M src/arch/x86/assembly_entry.S
1 file changed, 0 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/58203/1
diff --git a/src/arch/x86/assembly_entry.S b/src/arch/x86/assembly_entry.S
index 4e7baf4..6e73027 100644
--- a/src/arch/x86/assembly_entry.S
+++ b/src/arch/x86/assembly_entry.S
@@ -1,6 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-#include <cpu/x86/cpu_info.S.inc>
#include <rules.h>
/*
@@ -36,8 +35,6 @@
/* reset stack pointer to CAR/EARLYRAM stack */
mov $_STACK_TOP, %esp
- push_cpu_info
-
/* clear .bss section as it is not shared */
cld
xor %eax, %eax
--
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Gerrit-Change-Number: 58203
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Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org>
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Attention is currently required from: Julius Werner, Karthik Ramasubramanian.
Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58199 )
Change subject: arch/x86,cpu/x86,lib/thread: Remove usage of cpu_info from lib/thread
......................................................................
Patch Set 1:
(1 comment)
File src/lib/thread.c:
https://review.coreboot.org/c/coreboot/+/58199/comment/983c3863_7ca70e60
PS1, Line 249: !boot_cpu()
> Should we move this check inside set_current_thread. […]
Would you expect it to die in set_current_thread?
I added it here because threads_initialize is the first thing called from thread_run and thread_run_until.
--
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Gerrit-Change-Number: 58199
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Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org>
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Attention is currently required from: Bora Guvendik, Furquan Shaikh, Selma Bensaid, Maulik V Vaghela, Balaji Manigandan, Tim Wawrzynczak.
Hello Bora Guvendik, Furquan Shaikh, Selma Bensaid, Maulik V Vaghela, Balaji Manigandan, Tim Wawrzynczak,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/58202
to look at the new patch set (#2).
Change subject: mb/intel/adlrvp: Add separated VBT binaries for ADL-M
......................................................................
mb/intel/adlrvp: Add separated VBT binaries for ADL-M
ADL-M has its own set of VBT files to pick during execution,
this will avoid any conflict with other ADL variants.
BUG=None
TEST= Boot device on LP5/LP4, corresponding VBT file should be loaded.
Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com>
Change-Id: Ibbf3f11c9277f5dcb3e12f9020f54ec843444c3f
---
M src/mainboard/intel/adlrvp/mainboard.c
1 file changed, 3 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/58202/2
--
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Gerrit-Change-Number: 58202
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Gerrit-MessageType: newpatchset
Bernardo Perez Priego has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58202 )
Change subject: mb/intel/adlrvp: Add separated VBT binaries for ADL-M
......................................................................
mb/intel/adlrvp: Add separated VBT binaries for ADL-M
ADL-M has its own set of VBT files to pick during execution,
this will avoid any conflict with other ADL variants.
Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com>
Change-Id: Ibbf3f11c9277f5dcb3e12f9020f54ec843444c3f
---
M src/mainboard/intel/adlrvp/mainboard.c
1 file changed, 3 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/58202/1
diff --git a/src/mainboard/intel/adlrvp/mainboard.c b/src/mainboard/intel/adlrvp/mainboard.c
index a113683..904673e 100644
--- a/src/mainboard/intel/adlrvp/mainboard.c
+++ b/src/mainboard/intel/adlrvp/mainboard.c
@@ -75,13 +75,14 @@
switch (sku_id) {
case ADL_P_LP5_1:
case ADL_P_LP5_2:
- case ADL_M_LP5:
return "vbt_adlrvp_lp5.bin";
+ case ADL_M_LP5:
+ return "vbt_adlrvp_m_lp5.bin";
case ADL_P_DDR5_1:
case ADL_P_DDR5_2:
return "vbt_adlrvp_ddr5.bin";
case ADL_M_LP4:
- return "vbt_adlrvp_lp4.bin";
+ return "vbt_adlrvp_m_lp4.bin";
default:
return "vbt.bin";
}
--
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Attention is currently required from: Cliff Huang, Tim Wawrzynczak, Sridhar Siricilla, Bernardo Perez Priego, Patrick Rudolph.
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58125 )
Change subject: soc/intel/alderlake: Enable support for CSE stitching
......................................................................
Patch Set 15:
(1 comment)
File src/soc/intel/alderlake/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/58125/comment/f09b3737_6d7dc4ef
PS13, Line 63:
> This currently mimics whatever FIT tool does for adding partitions. […]
Plan to address this as follow-up. So marking this as resolved for now.
--
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Attention is currently required from: Tim Wawrzynczak.
Hello Tim Wawrzynczak,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/58201
to look at the new patch set (#2).
Change subject: util/cse*: Add cse_helpers.{c,h}
......................................................................
util/cse*: Add cse_helpers.{c,h}
This change moves `read_member` and `write_member` helper functions
out of cse_fpt.c and cse_serger.c into cse_helpers.c to avoid
duplication.
BUG=b:189177186,b:189167923
Change-Id: I7b646b29c9058d892bb0fc9824ef1b4340d2510c
Signed-off-by: Furquan Shaikh <furquan(a)google.com>
---
M util/cbfstool/Makefile.inc
M util/cbfstool/cse_fpt.c
M util/cbfstool/cse_fpt.h
A util/cbfstool/cse_helpers.c
A util/cbfstool/cse_helpers.h
M util/cbfstool/cse_serger.c
M util/cbfstool/cse_serger.h
7 files changed, 76 insertions(+), 84 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/58201/2
--
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