Attention is currently required from: Felix Singer, Furquan Shaikh, Mariusz Szafrański, Paul Menzel, Subrata Banik, Angel Pons, Patrick Rudolph, Lance Zhao, Nico Huber, Tim Wawrzynczak, Suresh Bellampalli, Vanessa Eusebio, Michal Motyl.
Hello Felix Singer, build bot (Jenkins), Furquan Shaikh, Mariusz Szafrański, Paul Menzel, Angel Pons, Subrata Banik, Patrick Rudolph, Lance Zhao, Nico Huber, Tim Wawrzynczak, Suresh Bellampalli, Vanessa Eusebio, Michal Motyl,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/57934
to look at the new patch set (#26).
Change subject: soc/intel/{common,skl}: set ACPI_FADT_PLATFORM_CLOCK based on Kconfig
......................................................................
soc/intel/{common,skl}: set ACPI_FADT_PLATFORM_CLOCK based on Kconfig
The FADT contains a flag `ACPI_FADT_PLATFORM_CLOCK` telling the OSPM if
a specification-compliant PM Timer is present. Currently, this flag is
set regardless of the timer being enabled or disabled.
To be specification-compliant, only set that flag, when the hardware PM
Timer is enabled. This changes behaviour of:
- all mainboards defaulting to USE_PM_ACPI_TIMER=n
- Apollo Lake and Gemini Lake, which do not have a hardware PM timer
Note: On platforms supporting uCode PM ACPI Timer emulation, this is
required, too, because emulation does not support `TMR_STS`. Any
OS or software checking this flag and thus relying on the overflow
flag would not work (properly).
Change-Id: Id2e5d69b5515c21e6ce922dab2cb88b494c65ebe
Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de>
---
M src/soc/intel/common/block/acpi/acpi.c
M src/soc/intel/skylake/fadt.c
2 files changed, 8 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/57934/26
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Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58016 )
Change subject: soc/intel: replace dt option PmTimerDisabled by Kconfig
......................................................................
Patch Set 8:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/58016/comment/331f5d8e_02bdd295
PS2, Line 13: *****
:
: Note: This change is the first of 12 changes that aim to transition full
: control over the hardware PM Timer and uCode Timer Emulation to coreboot.
: This series contains the following patches:
:
: * CB:58016 soc/intel: replace dt option PmTimerDisabled by Kconfig
: * CB:57934 soc/intel/{common,skl,dnv}: set ACPI_FADT_PLATFORM_CLOCK based on Kconfig
: * CB:58017 soc/intel: drop Kconfig `PM_ACPI_TIMER_OPTIONAL`
: * CB:57931 soc/intel/{common,apl,glk}: guard PM Timer option on SoCs w/o PM Timer
: * CB:58018 soc/intel/pmc: add a note about legacy OSes/payloads to PM Timer Kconfig
: * CB:57945 soc/intel/dnv_ns: add the Kconfig value for CPU_XTAL_HZ
: * CB:57944 soc/intel/dnv_ns: enable uCode PM Timer emulation
: * CB:58019 soc/intel: move disabling of PM Timer to SoC PMC code
: * CB:58020 soc/intel: implement ACPI timer disabling per SoC and drop common code
: * CB:57932 soc/intel/{skl,cnl,dnv,xeon_sp}: disable PM ACPI timer if chosen
: * CB:57933 soc/intel: transition full control over PM Timer from FSP to coreboot
: * CB:57930 soc/intel/*: only enable PM Timer emulation if the PM Timer is disabled
:
: *****
:
> drop before submit
Done
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Attention is currently required from: Felix Singer, Lance Zhao, Furquan Shaikh, Tim Wawrzynczak, Jeremy Soller, Paul Menzel, Angel Pons, Subrata Banik, Patrick Rudolph.
Hello Felix Singer, build bot (Jenkins), Furquan Shaikh, Jeremy Soller, Paul Menzel, Angel Pons, Subrata Banik, Patrick Rudolph, Lance Zhao, Tim Crawford, Nico Huber, Tim Wawrzynczak, Tim Wawrzynczak,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/58016
to look at the new patch set (#8).
Change subject: soc/intel: replace dt option PmTimerDisabled by Kconfig
......................................................................
soc/intel: replace dt option PmTimerDisabled by Kconfig
Replace the dt option `PmTimerDisabled` with use of the Kconfig option
`USE_PM_ACPI_TIMER` for enabling/disabling the PM Timer.
A default value representing the prior devicetree value was added to the
boards system76/{lemp10,galp5,darp7}, so this change will not alter
behaviour.
Change-Id: If1811c6b98847b22272acfa35ca44f4fbca68947
Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de>
---
M src/mainboard/system76/darp7/Kconfig
M src/mainboard/system76/darp7/devicetree.cb
M src/mainboard/system76/galp5/Kconfig
M src/mainboard/system76/galp5/devicetree.cb
M src/mainboard/system76/lemp10/Kconfig
M src/mainboard/system76/lemp10/devicetree.cb
M src/soc/intel/alderlake/Kconfig
M src/soc/intel/alderlake/chip.h
M src/soc/intel/alderlake/finalize.c
M src/soc/intel/elkhartlake/Kconfig
M src/soc/intel/elkhartlake/chip.h
M src/soc/intel/elkhartlake/finalize.c
M src/soc/intel/icelake/Kconfig
M src/soc/intel/icelake/chip.h
M src/soc/intel/icelake/finalize.c
M src/soc/intel/jasperlake/Kconfig
M src/soc/intel/jasperlake/chip.h
M src/soc/intel/jasperlake/finalize.c
M src/soc/intel/tigerlake/Kconfig
M src/soc/intel/tigerlake/chip.h
M src/soc/intel/tigerlake/finalize.c
21 files changed, 31 insertions(+), 61 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/58016/8
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Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58197 )
Change subject: vc/amd/fsp/cezanne: Update Cezanne FSP-M UPD definition
......................................................................
Patch Set 2:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/58197/comment/2ffeb0c4_4373f2fe
PS2, Line 7: vc/amd/fsp/cezanne: Update Cezanne FSP-M UPD definition
Maybe be more specific:
> Add UPD fsp_owns_pcie_resets to FSP-M
https://review.coreboot.org/c/coreboot/+/58197/comment/049e5c60_9119d32c
PS2, Line 10: newer FSP
If you have a version number, please add it.
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Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58186 )
Change subject: mb/google/caroline: Update _HID for digitizer
......................................................................
Patch Set 1: Code-Review+1
(1 comment)
Patchset:
PS1:
Why does it work in Chromium OS?
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Change subject: lib/spd_bin: Fix for LDDR5
......................................................................
Patch Set 5:
(6 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/58101/comment/aea03dc7_341ee60a
PS5, Line 9: Added LDDR5 for the param
: Fixed SPD name for LDDR5
Please format it as a list, and use imperative mood (Add, Fix).
https://review.coreboot.org/c/coreboot/+/58101/comment/798decd5_2c0f5435
PS5, Line 11: with this change, we won't get this warning message:
Please add a blank line above, and maybe just write:
> This addresses the warning below:
https://review.coreboot.org/c/coreboot/+/58101/comment/fc2f20f9_a568f42f
PS5, Line 11: with
With
File src/lib/spd_bin.c:
https://review.coreboot.org/c/coreboot/+/58101/comment/9e6eeea8_6a770cfe
PS5, Line 27: use_ddr4_params
This name should be updated, if DDR5 is also handled.
https://review.coreboot.org/c/coreboot/+/58101/comment/10dc8e53_39b01162
PS5, Line 37: case SPD_DRAM_LPDDR5:
Please order it one line below.
https://review.coreboot.org/c/coreboot/+/58101/comment/92db4420_83638dac
PS5, Line 169: case SPD_DRAM_LPDDR5:
Please order it below.
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