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Change subject: purism/librem_bdw: add support for ACPI brightness controls
......................................................................
Patch Set 1:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/58187/comment/03c05dd2_b14727e1
PS1, Line 11:
> Did it work under GNU/Linux before already?
The i915 kernel driver in Linux exposes its own brightness control devicec, so I'm pretty sure the answer is yes.
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Change subject: cpu/x86/smm/smm_stub: Remove cpu_info
......................................................................
Patch Set 3: Code-Review+1
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/58204/comment/025d69e3_14b65c18
PS3, Line 10: setup
set up
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Change subject: crossgcc/buildgcc: Fix compilation of IASL on GCC10
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
Build failure seems unrelated to the change:
Building GCC v8.3.0 for target ... failed. Check 'build-i386-elf-GCC/build.log'.
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Change subject: crossgcc/buildgcc: Fix compilation of IASL on GCC10
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Patch Set 1:
(1 comment)
Patchset:
PS1:
Might be fixed by Ia63f2c0655da53a89ee16b0272a685accc5f2baa.
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Change subject: mb/intel/adlrvp: Add separated VBT binaries for ADL-M
......................................................................
Patch Set 2:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/58202/comment/97a97156_877d575d
PS2, Line 7: mb/intel/adlrvp: Add separated VBT binaries for ADL-M
Maybe:
> Use dedicated VBT files for ADL-M
https://review.coreboot.org/c/coreboot/+/58202/comment/df059339_1c6e1998
PS2, Line 11:
Please mention where the files can be found, or when they were added.
https://review.coreboot.org/c/coreboot/+/58202/comment/188dbb33_d3e5b0d7
PS2, Line 13: TEST= Boot device on LP5/LP4, corresponding VBT file should be loaded.
Did you actually verify it?
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Change subject: mb/google/dedede/var/sasukette: Generate SPD ID for supported memory parts
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/58196/comment/3315f64e_63c1744f
PS2, Line 7: mb/google/dedede/var/sasukette: Generate SPD ID for supported memory parts
Maybe:
> Generate SPD ID for Samsung K4U6E3S4AB-MGCL
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Change subject: mb/google/dedede/var/sasukette: Generate SPD ID for supported memory parts
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Patch Set 2: Code-Review+1
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Change subject: mb/adlrvp: Add hook function to return EC in RW status
......................................................................
Patch Set 7:
(5 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/58099/comment/a044bc5d_5ac30d3d
PS7, Line 7: mb/adlrvp
mb/intel/adlrvp
https://review.coreboot.org/c/coreboot/+/58099/comment/6ef8026d_ec33a488
PS7, Line 11: un trusted
untrusted
https://review.coreboot.org/c/coreboot/+/58099/comment/6a74b6f9_c77cf0ac
PS7, Line 9: EC_IN_RW signal from EC GPIO is connected to GPIO E7
: of SOC. The function reads this GPIO to check if EC is in
: RW (un trusted) or RO (trusted)
Please reflow for 75 characters per line, and please add a dot/period to the end of sentences.
File src/mainboard/intel/adlrvp/chromeos.c:
https://review.coreboot.org/c/coreboot/+/58099/comment/2f8028cf_3b0f82b1
PS7, Line 51: int
bool or unsigned int?
File src/mainboard/intel/adlrvp/include/baseboard/gpio.h:
https://review.coreboot.org/c/coreboot/+/58099/comment/7f5bdc25_a16977ca
PS7, Line 15: #define GPIO_EC_IN_RW GPP_E7
Please align with a tabs as done above.
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