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Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58096 )
Change subject: soc/intel: drop P_BLK support
......................................................................
Patch Set 4: Code-Review+1
(3 comments)
Patchset:
PS2:
> ugh. once again a SkipMpInit case.......... […]
Guess it might just be broken atm. Probably doesn't matter on Linux because
a driver like `intel_idle` might use MWAIT instead (if that works on DNV).
File src/soc/intel/apollolake/cpu.c:
https://review.coreboot.org/c/coreboot/+/58096/comment/f92b2447_5332ae74
PS1, Line 37: IO_MWAIT_REDIRECT_MASK
> erm, oh, well... […]
This case is fixed but the `IO_MWAIT_REDIRECT_MASK` still needs to be removed
for Xeon-SP?
File src/soc/intel/xeon_sp/skx/cpu.c:
https://review.coreboot.org/c/coreboot/+/58096/comment/69ab2e7f_6cdaac97
PS1, Line 57: IO_MWAIT_REDIRECTION_ENABLE
> Same as APL
Ping
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Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56017 )
Change subject: Documentation: Improve x86_64
......................................................................
Patch Set 7: Code-Review+1
(8 comments)
File Documentation/arch/x86/x86_64.md:
https://review.coreboot.org/c/coreboot/+/56017/comment/d00f4047_29f155e1
PS7, Line 36: compability
Still not fixed: compa*ti*bility
https://review.coreboot.org/c/coreboot/+/56017/comment/9d8c4fd5_6da6c429
PS7, Line 40: phase
plural `phases`?
https://review.coreboot.org/c/coreboot/+/56017/comment/50394c22_7e63d1e2
PS7, Line 41: runs
If the above is changed to plural, this also needs to be changed to `run`
https://review.coreboot.org/c/coreboot/+/56017/comment/9bfd6069_a8104b9b
PS7, Line 45: the compiler
Which one? `the compiler` sounds like there's only one compiler, which is not the case.
https://review.coreboot.org/c/coreboot/+/56017/comment/ab2d646b_4172a772
PS7, Line 45: when
nit: Capitalize `When` for consistency with the other bullet points
https://review.coreboot.org/c/coreboot/+/56017/comment/3a481d74_9dfe2d25
PS7, Line 49: todays
today's
https://review.coreboot.org/c/coreboot/+/56017/comment/7fc9cacc_8854636c
PS7, Line 109: Options
`Option` (`Option ROMs` is a compound name, the plural `s` is in `ROMs`)
https://review.coreboot.org/c/coreboot/+/56017/comment/d4339484_60edc069
PS7, Line 125: Until now it could be verified by FOSS developers on various Intel platforms
: and no issues have been found.
I'd prefer to avoid using the word `verify` here, as there's no way to ensure x86_64 in CAR is fully working. Instead, how about:
However, coreboot developers working on x86_64 support have tried this on various Intel platforms, and so far haven't found any issues with CAR when running in x86_64 mode.
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Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/49233 )
Change subject: payloads/tianocore/Kconfig: Extend help for bootsplash file
......................................................................
payloads/tianocore/Kconfig: Extend help for bootsplash file
Add more detail as to why a smaller-than-screen-size image is to be
preferred, in contrast to other payloads' bootsplash images.
Signed-off-by: Felix Friedlander <felix(a)ffetc.net>
Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com>
Change-Id: Ib4c6666bb0e49369fe8fe2ae3dc12c023f668da0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49233
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Angel Pons <th3fanbus(a)gmail.com>
---
M payloads/external/tianocore/Kconfig
1 file changed, 12 insertions(+), 2 deletions(-)
Approvals:
build bot (Jenkins): Verified
Angel Pons: Looks good to me, approved
diff --git a/payloads/external/tianocore/Kconfig b/payloads/external/tianocore/Kconfig
index 5349f25..a3c9981 100644
--- a/payloads/external/tianocore/Kconfig
+++ b/payloads/external/tianocore/Kconfig
@@ -76,8 +76,18 @@
default "bootsplash.bmp"
help
The path and filename of the file to use as graphical bootsplash
- screen. The file format must be uncompressed BMP, and the file's
- resolution must be less than the native resolution of the display.
+ image. The file must be an uncompressed BMP.
+
+ This image will also be used as the BGRT boot image, which may
+ persist through your OS boot process, and will be displayed
+ vertically centered 38.2% from the top of the display.
+
+ See ACPI spec 6.3, 5.2.22 Boot Graphics Resource Table (BGRT), and
+ Microsoft's documentation on BGRT positioning:
+ Docs/Windows/Windows Drivers/Bring up guide/Boot screen components
+
+ Accordingly, the image used should be no taller/wider than 40% of
+ the display panel's native pixel height/width (or resolution set).
If an absolute path is not given, the path will assumed to be
relative to the coreboot root directory.
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Change subject: mb/system76: tgl-u: Add gfx register for GMA ACPI
......................................................................
Patch Set 2: Code-Review+2
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Change subject: Documentation: Improve x86_64
......................................................................
Patch Set 7:
(1 comment)
File Documentation/arch/x86/x86_64.md:
https://review.coreboot.org/c/coreboot/+/56017/comment/66283f71_47ad1a8b
PS6, Line 35: coreboot's
> `coreboot`
Done
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Change subject: arch/x86/mmu: Port armv8 MMU to x86_64
......................................................................
Patch Set 17:
(1 comment)
File src/arch/x86/mmu.c:
https://review.coreboot.org/c/coreboot/+/30119/comment/accc765f_45c3d957
PS16, Line 335: (uint64_t *)cbmem_add(CBMEM_ID_PAGE, pages * 4 * KiB);
> Should this be 4K aligned?
Done
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Patrick Rudolph has uploaded a new patch set (#17) to the change originally created by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/30119 )
Change subject: arch/x86/mmu: Port armv8 MMU to x86_64
......................................................................
arch/x86/mmu: Port armv8 MMU to x86_64
Add functions to set up page tables for long mode and generate
new page tables at end of BS_DEV_RESOURCES.
At end of BS_DEV_RESOURCES the memory map is fully known and the
page tables can be properly generated based on the memory resources.
This allows the CPU to access all DRAM and MMIO even beyond 4GiB.
Right now there's no use case for this, but the code is necessary to:
- Load payloads above 4GiB
- Install tables (like ACPI/SMBIOS) above 4GiB
- allow coreboot PCI drivers to access BARs mapped above 4GiB
Tested on prodrive/hermes: Still boots to payload.
Doesn't affect existing x86_32 code.
Change-Id: I6e8b46e65925823a84b8ccd647c7d6848aa20992
Signed-off-by: Patrick Rudolph <siro(a)das-labor.org>
---
M Documentation/arch/x86/x86_64.md
M src/arch/x86/Makefile.inc
A src/arch/x86/include/arch/mmu.h
A src/arch/x86/mmu.c
M src/commonlib/include/commonlib/cbmem_id.h
5 files changed, 495 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/30119/17
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