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Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58118 )
Change subject: acpigen,soc/amd/cezanne,intel/{common,skl}: rework CPPC table passing
......................................................................
Patch Set 8:
(1 comment)
Patchset:
PS8:
> TBH, I'm missing the incentive here?
Well, I did this as part of deobfuscating that whole code. After some iterations, that is left as a separate change. IMO it's a bit cleaner to have a static table instead of a function when there is nothing runtime related yet. However, it's not a must. I let you decide
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Hello Felix Singer, build bot (Jenkins), Furquan Shaikh, Benjamin Doron, Matt DeVillier, Paul Menzel, Mimoja, Angel Pons, Subrata Banik, Arthur Heymans, Kyösti Mälkki, Matthew Garrett, Patrick Rudolph, Aaron Durbin, Tim Crawford, Nico Huber, Tim Wawrzynczak, Maxim Polyakov, Michal Zygowski, Wim Vervoorn,
I'd like you to reexamine a change. Please visit
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Change subject: soc/intel/skylake: switch to common ACPI code
......................................................................
soc/intel/skylake: switch to common ACPI code
Use the common ACPI code to reduce code duplication.
Change-Id: I1ec804ae4006a2d9b69c0d93a658eb3b84d60b40
Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de>
---
M src/mainboard/supermicro/x11-lga1151-series/fadt.c
M src/soc/intel/skylake/Kconfig
M src/soc/intel/skylake/acpi.c
M src/soc/intel/skylake/chip.c
M src/soc/intel/skylake/fadt.c
D src/soc/intel/skylake/include/soc/acpi.h
M src/soc/intel/skylake/include/soc/pm.h
M src/soc/intel/skylake/include/soc/pmc.h
M src/soc/intel/skylake/include/soc/ramstage.h
9 files changed, 62 insertions(+), 423 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/44138/22
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Change subject: soc/intel: drop P_BLK support
......................................................................
soc/intel: drop P_BLK support
P_BLK is legacy and superseeded by ACPI _CST. Also, the implementation
for most platforms in soc/intel is broken. Thus, drop it.
For APL the IO redirection is kept since it's used as replacement for
the broken MWAIT instructions.
Change-Id: I489aa7886dd9a4c1e6c12542bc2a1feba245ec36
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---
M src/soc/intel/apollolake/acpi.c
M src/soc/intel/baytrail/acpi.c
M src/soc/intel/baytrail/fadt.c
M src/soc/intel/braswell/acpi.c
M src/soc/intel/braswell/fadt.c
M src/soc/intel/broadwell/pch/fadt.c
M src/soc/intel/common/block/acpi/acpi.c
M src/soc/intel/denverton_ns/acpi.c
M src/soc/intel/denverton_ns/include/soc/msr.h
M src/soc/intel/elkhartlake/acpi.c
M src/soc/intel/skylake/fadt.c
M src/soc/intel/xeon_sp/include/soc/msr.h
M src/soc/intel/xeon_sp/skx/cpu.c
M src/soc/intel/xeon_sp/skx/soc_acpi.c
14 files changed, 10 insertions(+), 79 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/58096/5
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Bill XIE has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51671 )
Change subject: arch/x86: Init firmware pointer for EC SMSC KBC1098/KBC1126 at build time
......................................................................
Patch Set 10:
(1 comment)
File src/ec/hp/kbc1126/ecfw_ptr.c:
https://review.coreboot.org/c/coreboot/+/51671/comment/f27a9738_78d435ec
PS9, Line 6: __attribute__((used, __section__(".ecfw_ptr"))) const uint8_t ecfw_ptr[CONFIG_ECFW_PTR_SIZE];
> > Is the EC firmware pointer a part of the CBFS and hashed? […]
Done: Now I initialize it in C.
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Hello build bot (Jenkins), Patrick Georgi, Julius Werner, Iru Cai,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#10).
Change subject: arch/x86: Init firmware pointer for EC SMSC KBC1098/KBC1126 at build time
......................................................................
arch/x86: Init firmware pointer for EC SMSC KBC1098/KBC1126 at build time
According to util/kbc1126/README.md, for these ECs to work, the
address and size of their two firmware should be written to $s-0x100`
(`$s` means the image size, done with kbc1126_ec_insert), which means
that every existing section (especially those used to store code)
should not overlap this address, otherwise the bootblock will get
damaged when inserting firmwares of the EC.
In this commit, ecfw_ptr is a structure initialized at build time
according to CONFIG_KBC1126_FW1_OFFSET and CONFIG_KBC1126_FW2_OFFSET
(to do so, they should be redefined as hex), and linked to
CONFIG_ECFW_PTR_ADDR within bootblock, so kbc1126_ec_insert is not
needed at build time any more.
Test passed on Elitebook Folio 9470m.
Signed-off-by: Bill XIE <persmule(a)hardenedlinux.org>
Change-Id: I4f0de0c4d7283e630242fbe84a46e0547783c49e
---
M src/arch/x86/bootblock.ld
M src/ec/hp/kbc1126/Kconfig
M src/ec/hp/kbc1126/Makefile.inc
A src/ec/hp/kbc1126/ecfw_ptr.c
A src/ec/hp/kbc1126/ecfw_ptr.h
5 files changed, 61 insertions(+), 14 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/51671/10
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Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30119 )
Change subject: arch/x86/mmu: Port armv8 MMU to x86_64
......................................................................
Patch Set 17:
(1 comment)
File src/arch/x86/mmu.c:
https://review.coreboot.org/c/coreboot/+/30119/comment/14e8ea78_251d4326
PS16, Line 335: (uint64_t *)cbmem_add(CBMEM_ID_PAGE, pages * 4 * KiB);
> Done
It might be even better to have page tables in heap. That would make it easier to reuse this code in all _RAM_ stages.
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