Attention is currently required from: Felix Singer, Lance Zhao, Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Paul Menzel, Angel Pons, Subrata Banik, Patrick Rudolph.
Hello Felix Singer, Lance Zhao, build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Tim Wawrzynczak, Paul Menzel, Angel Pons, Subrata Banik, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#14).
Change subject: soc/intel/pmc: add a note about legacy OSes/payloads to PM Timer Kconfig
......................................................................
soc/intel/pmc: add a note about legacy OSes/payloads to PM Timer Kconfig
Since ACPI 5.0A it is allowed to disable the ACPI Timer, when the
according FADT flag `ACPI_FADT_PLATFORM_CLOCK` is unset.
Starting with Skylake, most platforms (except Xeon-SP) support PM Timer
emulation, so even legacy OSes and payloads should work fine with the
hardware PM Timer disabled. However, when the `TMR_STS` functionality
is required, some legacy OSes might still not work (properly).
Add a note about this to the Kconfig help.
Change-Id: I53f1814113902124779ed85da030374439570688
Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de>
---
M src/soc/intel/common/block/pmc/Kconfig
1 file changed, 6 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/58018/14
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Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57934 )
Change subject: soc/intel/{common,skl}: set ACPI_FADT_PLATFORM_CLOCK based on Kconfig
......................................................................
Patch Set 27:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/57934/comment/652ded89_5f88a4f5
PS26, Line 17: - Apollo Lake and Gemini Lake, which do not have a hardware PM timer
> These two do not select PM_ACPI_TIMER_OPTIONAL hence are not affected anymore?
Done
File src/soc/intel/common/block/acpi/acpi.c:
https://review.coreboot.org/c/coreboot/+/57934/comment/98dc9f7c_7d01a9bb
PS26, Line 155: if (CONFIG(USE_PM_ACPI_TIMER) || !CONFIG(PM_ACPI_TIMER_OPTIONAL))
> I need to think about this again...
yup, right.
the latter part is temporary only and will vanish here: https://review.coreboot.org/c/coreboot/+/58017/15/src/soc/intel/common/bloc…
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Attention is currently required from: Felix Singer, Furquan Shaikh, Mariusz Szafrański, Paul Menzel, Subrata Banik, Angel Pons, Patrick Rudolph, Lance Zhao, Nico Huber, Tim Wawrzynczak, Suresh Bellampalli, Vanessa Eusebio, Michal Motyl.
Hello Felix Singer, build bot (Jenkins), Furquan Shaikh, Mariusz Szafrański, Paul Menzel, Angel Pons, Subrata Banik, Patrick Rudolph, Lance Zhao, Nico Huber, Tim Wawrzynczak, Suresh Bellampalli, Vanessa Eusebio, Michal Motyl,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/57934
to look at the new patch set (#27).
Change subject: soc/intel/{common,skl}: set ACPI_FADT_PLATFORM_CLOCK based on Kconfig
......................................................................
soc/intel/{common,skl}: set ACPI_FADT_PLATFORM_CLOCK based on Kconfig
The FADT contains a flag `ACPI_FADT_PLATFORM_CLOCK` telling the OSPM if
a specification-compliant PM Timer is present. Currently, this flag is
set regardless of the timer being enabled or disabled.
To be specification-compliant, only set that flag, when the hardware PM
Timer is enabled. This changes behaviour of all mainboards defaulting to
USE_PM_ACPI_TIMER=n.
Note: On platforms supporting uCode PM ACPI Timer emulation, this is
required, too, because emulation does not support `TMR_STS`. Any
OS or software checking this flag and thus relying on the overflow
flag would not work (properly).
Change-Id: Id2e5d69b5515c21e6ce922dab2cb88b494c65ebe
Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de>
---
M src/soc/intel/common/block/acpi/acpi.c
M src/soc/intel/skylake/fadt.c
2 files changed, 8 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/57934/27
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Change subject: acpigen,soc/amd/cezanne,intel/{common,skl}: rework CPPC table passing
......................................................................
Patch Set 9:
(10 comments)
File src/soc/amd/cezanne/cppc.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130152):
https://review.coreboot.org/c/coreboot/+/58118/comment/d9aec64f_4d74a837
PS9, Line 15: [CPPC_HIGHEST_PERF] = CPPC_REG_MSR(MSR_CPPC_CAPABILITY_1, SHIFT_CPPC_CAPABILITY_1_HIGHEST_PERF, 8),
line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130152):
https://review.coreboot.org/c/coreboot/+/58118/comment/a7126cfc_504aa2c4
PS9, Line 16: [CPPC_NOMINAL_PERF] = CPPC_REG_MSR(MSR_CPPC_CAPABILITY_1, SHIFT_CPPC_CAPABILITY_1_NOMINAL_PERF, 8),
line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130152):
https://review.coreboot.org/c/coreboot/+/58118/comment/756d2f74_89a27bc6
PS9, Line 17: [CPPC_LOWEST_NONL_PERF] = CPPC_REG_MSR(MSR_CPPC_CAPABILITY_1, SHIFT_CPPC_CAPABILITY_1_LOW_NON_LIN_PERF, 8),
line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130152):
https://review.coreboot.org/c/coreboot/+/58118/comment/659d3e15_e858d7b1
PS9, Line 18: [CPPC_LOWEST_PERF] = CPPC_REG_MSR(MSR_CPPC_CAPABILITY_1, SHIFT_CPPC_CAPABILITY_1_LOWEST_PERF, 8),
line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130152):
https://review.coreboot.org/c/coreboot/+/58118/comment/68d66491_831699de
PS9, Line 20: [CPPC_DESIRED_PERF] = CPPC_REG_MSR(MSR_CPPC_REQUEST, SHIFT_CPPC_REQUEST_DES_PERF, 8),
line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130152):
https://review.coreboot.org/c/coreboot/+/58118/comment/4dcdd033_f5adb7db
PS9, Line 21: [CPPC_MIN_PERF] = CPPC_REG_MSR(MSR_CPPC_REQUEST, SHIFT_CPPC_REQUEST_MIN_PERF, 8),
line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130152):
https://review.coreboot.org/c/coreboot/+/58118/comment/38964dba_516d4110
PS9, Line 22: [CPPC_MAX_PERF] = CPPC_REG_MSR(MSR_CPPC_REQUEST, SHIFT_CPPC_REQUEST_MAX_PERF, 8),
line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130152):
https://review.coreboot.org/c/coreboot/+/58118/comment/d474666a_a9b6e78e
PS9, Line 26: [CPPC_REF_PERF_COUNTER] = CPPC_REG_MSR(MSR_MAX_PERFORMANCE_FREQUENCY_CLOCK_COUNT, 0, 64),
line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130152):
https://review.coreboot.org/c/coreboot/+/58118/comment/3949a691_a7356162
PS9, Line 27: [CPPC_DELIVERED_PERF_COUNTER] = CPPC_REG_MSR(MSR_ACTUAL_PERFORMANCE_FREQUENCY_CLOCK_COUNT, 0, 64),
line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130152):
https://review.coreboot.org/c/coreboot/+/58118/comment/e5244bd3_96654f2c
PS9, Line 34: [CPPC_PERF_PREF] = CPPC_REG_MSR(MSR_CPPC_REQUEST, SHIFT_CPPC_REQUEST_ENERGY_PERF_PREF, 8),
line over 96 characters
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build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57886 )
Change subject: acpigen,soc/amd,cpu/intel: rework static DWORD for CPPC table
......................................................................
Patch Set 11:
(15 comments)
File src/cpu/intel/common/common_init.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130151):
https://review.coreboot.org/c/coreboot/+/57886/comment/b5253dc4_12fab34d
PS11, Line 108: config->entries[CPPC_HIGHEST_PERF] = CPPC_REG_MSR(IA32_HWP_CAPABILITIES, 0, 8);
line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130151):
https://review.coreboot.org/c/coreboot/+/57886/comment/acb4dc7f_ceceb7b6
PS11, Line 110: config->entries[CPPC_LOWEST_NONL_PERF] = CPPC_REG_MSR(IA32_HWP_CAPABILITIES, 16, 8);
line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130151):
https://review.coreboot.org/c/coreboot/+/57886/comment/7a870c69_1ff8738d
PS11, Line 111: config->entries[CPPC_LOWEST_PERF] = CPPC_REG_MSR(IA32_HWP_CAPABILITIES, 24, 8);
line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130151):
https://review.coreboot.org/c/coreboot/+/57886/comment/5262abae_b08a1c13
PS11, Line 112: config->entries[CPPC_GUARANTEED_PERF] = CPPC_REG_MSR(IA32_HWP_CAPABILITIES, 8, 8);
line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130151):
https://review.coreboot.org/c/coreboot/+/57886/comment/dd060bbf_95f6e983
PS11, Line 128: config->entries[CPPC_AUTO_ACTIVITY_WINDOW] = CPPC_REG_MSR(IA32_HWP_REQUEST, 32, 10);
line over 96 characters
File src/soc/amd/cezanne/cppc.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130151):
https://review.coreboot.org/c/coreboot/+/57886/comment/b3d4c683_23aab728
PS11, Line 18: config->entries[CPPC_HIGHEST_PERF] = CPPC_REG_MSR(MSR_CPPC_CAPABILITY_1, SHIFT_CPPC_CAPABILITY_1_HIGHEST_PERF, 8);
line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130151):
https://review.coreboot.org/c/coreboot/+/57886/comment/fe80531e_00823cc1
PS11, Line 19: config->entries[CPPC_NOMINAL_PERF] = CPPC_REG_MSR(MSR_CPPC_CAPABILITY_1, SHIFT_CPPC_CAPABILITY_1_NOMINAL_PERF, 8);
line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130151):
https://review.coreboot.org/c/coreboot/+/57886/comment/962f75ad_4ef0a18c
PS11, Line 20: config->entries[CPPC_LOWEST_NONL_PERF] = CPPC_REG_MSR(MSR_CPPC_CAPABILITY_1, SHIFT_CPPC_CAPABILITY_1_LOW_NON_LIN_PERF, 8);
line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130151):
https://review.coreboot.org/c/coreboot/+/57886/comment/c66d378a_5245d57d
PS11, Line 21: config->entries[CPPC_LOWEST_PERF] = CPPC_REG_MSR(MSR_CPPC_CAPABILITY_1, SHIFT_CPPC_CAPABILITY_1_LOWEST_PERF, 8);
line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130151):
https://review.coreboot.org/c/coreboot/+/57886/comment/6e602a10_ad5df217
PS11, Line 23: config->entries[CPPC_DESIRED_PERF] = CPPC_REG_MSR(MSR_CPPC_REQUEST, SHIFT_CPPC_REQUEST_DES_PERF, 8);
line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130151):
https://review.coreboot.org/c/coreboot/+/57886/comment/3f1aeb3e_c2650f96
PS11, Line 24: config->entries[CPPC_MIN_PERF] = CPPC_REG_MSR(MSR_CPPC_REQUEST, SHIFT_CPPC_REQUEST_MIN_PERF, 8);
line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130151):
https://review.coreboot.org/c/coreboot/+/57886/comment/e160f136_8a2ac75b
PS11, Line 25: config->entries[CPPC_MAX_PERF] = CPPC_REG_MSR(MSR_CPPC_REQUEST, SHIFT_CPPC_REQUEST_MAX_PERF, 8);
line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130151):
https://review.coreboot.org/c/coreboot/+/57886/comment/21e2cdca_e395d018
PS11, Line 29: config->entries[CPPC_REF_PERF_COUNTER] = CPPC_REG_MSR(MSR_MAX_PERFORMANCE_FREQUENCY_CLOCK_COUNT, 0, 64);
line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130151):
https://review.coreboot.org/c/coreboot/+/57886/comment/e9d4002d_56d74c26
PS11, Line 30: config->entries[CPPC_DELIVERED_PERF_COUNTER] = CPPC_REG_MSR(MSR_ACTUAL_PERFORMANCE_FREQUENCY_CLOCK_COUNT, 0, 64);
line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130151):
https://review.coreboot.org/c/coreboot/+/57886/comment/c4d3707b_2459c366
PS11, Line 39: config->entries[CPPC_PERF_PREF] = CPPC_REG_MSR(MSR_CPPC_REQUEST, SHIFT_CPPC_REQUEST_ENERGY_PERF_PREF, 8);
line over 96 characters
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Attention is currently required from: Lance Zhao, Felix Singer, Matt Delco, Nico Huber, Furquan Shaikh, Paul Menzel, Tim Wawrzynczak, Ravindra, Subrata Banik, Lean Sheng Tan, Patrick Rudolph.
Hello Felix Singer, Lance Zhao, build bot (Jenkins), Matt Delco, Nico Huber, Furquan Shaikh, Paul Menzel, Tim Wawrzynczak, Ravindra, Subrata Banik, Lean Sheng Tan, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/47543
to look at the new patch set (#31).
Change subject: soc/intel/{icl,tgl,jsl,ehl}: enable ACPI CPPC entries
......................................................................
soc/intel/{icl,tgl,jsl,ehl}: enable ACPI CPPC entries
Enable CPPC entries generation, needed for Intel SpeedShift.
This can be tested by checking sysfs in Linux:
$ grep . /sys/devices/system/cpu/cpu?/acpi_cppc/*perf
The output should look like this, while the values may differ:
/sys/devices/system/cpu/cpu0/acpi_cppc/highest_perf:28
/sys/devices/system/cpu/cpu0/acpi_cppc/lowest_nonlinear_perf:5
/sys/devices/system/cpu/cpu0/acpi_cppc/lowest_perf:1
/sys/devices/system/cpu/cpu0/acpi_cppc/nominal_perf:24
/sys/devices/system/cpu/cpu1/acpi_cppc/highest_perf:28
/sys/devices/system/cpu/cpu1/acpi_cppc/lowest_nonlinear_perf:5
...
Change-Id: I910b4e17d4044f1bf1ecfa0643ac62fc7a8cb51b
Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de>
---
M src/soc/intel/elkhartlake/Kconfig
M src/soc/intel/icelake/Kconfig
M src/soc/intel/jasperlake/Kconfig
M src/soc/intel/tigerlake/Kconfig
4 files changed, 4 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/47543/31
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Attention is currently required from: Felix Singer, Lance Zhao, Jason Glenesk, Raul Rangel, Nico Huber, Furquan Shaikh, Marshall Dawson, Tim Wawrzynczak, Angel Pons, Patrick Rudolph, Felix Held.
Hello Felix Singer, build bot (Jenkins), Raul Rangel, Furquan Shaikh, Paul Menzel, Angel Pons, Patrick Rudolph, Lance Zhao, Jason Glenesk, Nico Huber, Marshall Dawson, Tim Wawrzynczak, Tim Wawrzynczak, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/58118
to look at the new patch set (#9).
Change subject: acpigen,soc/amd/cezanne,intel/{common,skl}: rework CPPC table passing
......................................................................
acpigen,soc/amd/cezanne,intel/{common,skl}: rework CPPC table passing
Instead of passing around a magic struct with embedded version, use
pointers and pass the CPPC version directly to the ACPI generator.
Test: dumped SSDT before and after do not differ.
Change-Id: I26c5e80c2a16a50ed73245c7c32d61b17e45c22a
Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de>
---
M src/acpi/acpigen.c
M src/cpu/intel/common/common.h
M src/cpu/intel/common/common_init.c
M src/include/acpi/acpi.h
M src/include/acpi/acpigen.h
M src/soc/amd/cezanne/cppc.c
M src/soc/amd/cezanne/include/soc/cppc.h
M src/soc/intel/common/block/acpi/acpi.c
M src/soc/intel/skylake/acpi.c
9 files changed, 99 insertions(+), 98 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/58118/9
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Hello Felix Singer, build bot (Jenkins), Raul Rangel, Furquan Shaikh, Paul Menzel, Angel Pons, Subrata Banik, Kyösti Mälkki, Patrick Rudolph, Lance Zhao, Jason Glenesk, Matt Delco, Nico Huber, Marshall Dawson, Tim Wawrzynczak, Tim Wawrzynczak, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/57886
to look at the new patch set (#11).
Change subject: acpigen,soc/amd,cpu/intel: rework static DWORD for CPPC table
......................................................................
acpigen,soc/amd,cpu/intel: rework static DWORD for CPPC table
Some elements in the ACPI CPPC table allow static DWORDs. Instead of
using a fake register resource, use a tagged union with the two types
"register" and "DWORD" and respective macros for CPPC table entries.
Test: dumped SSDT before and after do not differ.
Change-Id: Ib853261b5c0ea87ae2424fed188f2d1872be9a06
Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de>
---
M src/acpi/acpigen.c
M src/cpu/intel/common/common.h
M src/cpu/intel/common/common_init.c
M src/include/acpi/acpigen.h
M src/soc/amd/cezanne/cppc.c
M src/soc/amd/cezanne/include/soc/cppc.h
6 files changed, 73 insertions(+), 67 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/57886/11
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Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58018 )
Change subject: soc/intel/pmc: add a note about legacy OSes/payloads to PM Timer Kconfig
......................................................................
Patch Set 13:
(1 comment)
File src/soc/intel/common/block/pmc/Kconfig:
https://review.coreboot.org/c/coreboot/+/58018/comment/5c89f624_a05df032
PS13, Line 80: or payloads with ACPI version < 5.0A might not work.
> Is there a platform that supports disabling the timer but doesn't offer emulation?
currently only Xeon-SP (at least we don't know if it supports emulation)
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