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Hello Tim Wawrzynczak, Bernardo Perez Priego, Patrick Rudolph,
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Change subject: soc/intel/common/block/cse: Use newly added `create-cse-region`
......................................................................
soc/intel/common/block/cse: Use newly added `create-cse-region`
This change uses the newly added `create-cse-region` command for
cse_serger tool instead of performing `dd` operations for each
partition.
BUG=b:189177580
Change-Id: Ia915e3ac423f9461876e9ae186fb8ddce55f3194
Signed-off-by: Furquan Shaikh <furquan(a)google.com>
---
M src/soc/intel/common/block/cse/Makefile.inc
1 file changed, 5 insertions(+), 12 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/58216/2
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Attention is currently required from: Tim Wawrzynczak, Bernardo Perez Priego.
Hello Tim Wawrzynczak, Bernardo Perez Priego,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#2).
Change subject: util/cse_serger: Add command `create-cse-region`
......................................................................
util/cse_serger: Add command `create-cse-region`
This change adds a new command `create-cse-region` to cse_serger tool
which takes as inputs offset:size and file for different CSE
partitions and generates the entire CSE region image.
BUG=b:189177186
Change-Id: Ib087f5516e5beb6390831ef4e34b0b067d3fbc8b
Signed-off-by: Furquan Shaikh <furquan(a)google.com>
---
M util/cbfstool/cse_serger.c
1 file changed, 98 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/58215/2
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Hello build bot (Jenkins), Tim Wawrzynczak, Bernardo Perez Priego,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/58214
to look at the new patch set (#2).
Change subject: util/cse_serger: Replace cse_layout_regions with array of regions
......................................................................
util/cse_serger: Replace cse_layout_regions with array of regions
This change replaces `struct cse_layout_regions` with an array of
`struct region` and introduces enums for DP and BP[1-4]. This makes it
easier to loop over the different regions in following changes.
BUG=b:189177186
Change-Id: If3cced4506d26dc534047cb9c385aaa9418d8522
Signed-off-by: Furquan Shaikh <furquan(a)google.com>
---
M util/cbfstool/bpdt_formats/bpdt_1_6.c
M util/cbfstool/bpdt_formats/bpdt_1_7.c
M util/cbfstool/cse_serger.c
M util/cbfstool/cse_serger.h
4 files changed, 50 insertions(+), 38 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/58214/2
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build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58215 )
Change subject: util/cse_serger: Add command `create-cse-region`
......................................................................
Patch Set 1:
(1 comment)
File util/cbfstool/cse_serger.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130185):
https://review.coreboot.org/c/coreboot/+/58215/comment/481232eb_d35bf98a
PS1, Line 720: if (i == 0) {
braces {} are not necessary for any arm of this statement
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Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58213 )
Change subject: mb/google/brya: Set same size for CSE_RW, ME_RW_A and ME_RW_B
......................................................................
mb/google/brya: Set same size for CSE_RW, ME_RW_A and ME_RW_B
CSE RW firmware from ME_RW_A/ME_RW_B is copied over to CSE_RW region
in case of firmware update. Ensure that the size of the regions match
so that we do not have situations where ME_RW_A/B firmware grows
bigger than what CSE_RW can hold.
BUG=b:189177538
Change-Id: I374db5d490292eeb98f67dc684c2106d42779dac
Signed-off-by: Furquan Shaikh <furquan(a)google.com>
---
M src/mainboard/google/brya/chromeos.fmd
1 file changed, 3 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/58213/1
diff --git a/src/mainboard/google/brya/chromeos.fmd b/src/mainboard/google/brya/chromeos.fmd
index 656b65b..fee1a53 100644
--- a/src/mainboard/google/brya/chromeos.fmd
+++ b/src/mainboard/google/brya/chromeos.fmd
@@ -5,7 +5,7 @@
CSE_LAYOUT 8K
CSE_RO 1600K
CSE_DATA 512K
- CSE_RW
+ CSE_RW 2996K
}
}
SI_BIOS 27M {
@@ -13,7 +13,7 @@
VBLOCK_A 64K
FW_MAIN_A(CBFS)
RW_FWID_A 64
- ME_RW_A(CBFS) 3M
+ ME_RW_A(CBFS) 2996K
}
RW_LEGACY(CBFS) 2M
RW_MISC 1M {
@@ -42,7 +42,7 @@
VBLOCK_B 64K
FW_MAIN_B(CBFS)
RW_FWID_B 64
- ME_RW_B(CBFS) 3M
+ ME_RW_B(CBFS) 2996K
}
# Make WP_RO region align with SPI vendor
# memory protected range specification.
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Anil Kumar K has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58099 )
Change subject: mb/intel/adlrvp: Add hook function to return EC in RW status
......................................................................
Patch Set 9:
(5 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/58099/comment/d26b5337_a6e78f7e
PS7, Line 7: mb/adlrvp
> mb/intel/adlrvp
Ack
https://review.coreboot.org/c/coreboot/+/58099/comment/91139e26_a392c990
PS7, Line 9: EC_IN_RW signal from EC GPIO is connected to GPIO E7
: of SOC. The function reads this GPIO to check if EC is in
: RW (un trusted) or RO (trusted)
> Please reflow for 75 characters per line, and please add a dot/period to the end of sentences.
Ack
https://review.coreboot.org/c/coreboot/+/58099/comment/b49a7a52_d3f1f6cc
PS7, Line 11: un trusted
> untrusted
Ack
File src/mainboard/intel/adlrvp/chromeos.c:
https://review.coreboot.org/c/coreboot/+/58099/comment/4335b723_901ddf4c
PS7, Line 51: int
> bool or unsigned int?
i followed the definition in src/include/bootmode.h
int get_ec_is_trusted(void);
File src/mainboard/intel/adlrvp/include/baseboard/gpio.h:
https://review.coreboot.org/c/coreboot/+/58099/comment/e2079a7a_476bf27d
PS7, Line 15: #define GPIO_EC_IN_RW GPP_E7
> Please align with a tabs as done above.
Ack
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Hello Bora Guvendik, build bot (Jenkins), Selma Bensaid, Hsuan-ting Chen, Bernardo Perez Priego,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/58099
to look at the new patch set (#9).
Change subject: mb/intel/adlrvp: Add hook function to return EC in RW status
......................................................................
mb/intel/adlrvp: Add hook function to return EC in RW status
EC_IN_RW signal from EC GPIO is connected to GPIO E7 of SOC. The function
reads this GPIO to check if EC is in RW (untrusted) or RO (trusted).
Branch=none
Bug=none
Test=Issue manual recovery and confirm DUT is entering recovery mode on
ADL-M RVP.
Signed-off-by: Anil Kumar <anil.kumar.k(a)intel.com>
Change-Id: I20804db450ab0b3ebe19c51ba2b294a0137d81a7
---
M src/mainboard/intel/adlrvp/chromeos.c
M src/mainboard/intel/adlrvp/early_gpio.c
M src/mainboard/intel/adlrvp/early_gpio_m.c
M src/mainboard/intel/adlrvp/gpio.c
M src/mainboard/intel/adlrvp/include/baseboard/gpio.h
5 files changed, 19 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/58099/9
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