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Change subject: soc/intel/alderlake: [WIP]Trigger cse_fw_sync before DRAM Init
......................................................................
Patch Set 7: Verified+1
(1 comment)
File src/soc/intel/alderlake/romstage/romstage.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130197):
https://review.coreboot.org/c/coreboot/+/55364/comment/24673bd7_16170b51
PS7, Line 140: if (!s3wake) {
braces {} are not necessary for single statement blocks
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Change subject: soc/intel/common: Add HECI Reset flow in the CSE driver
......................................................................
Patch Set 7:
(6 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/55363/comment/b32824ca_ef4e9166
PS2, Line 8:
> Please start by stating the problem.
Done
https://review.coreboot.org/c/coreboot/+/55363/comment/c5a300e3_74d57616
PS2, Line 9: This is required as part
: of the HECI Interface initialization in order to put the host and CSE into
: a known good state for communication.
> Please reference the specification.
Done
https://review.coreboot.org/c/coreboot/+/55363/comment/5eabee31_1ed4b686
PS2, Line 15:
> Is there bug for this?
There is no bug.
File src/soc/intel/common/block/cse/cse.c:
https://review.coreboot.org/c/coreboot/+/55363/comment/5507b3a3_38904044
PS2, Line 104: Triggers
> Imperative mood: Trigger.
Done
https://review.coreboot.org/c/coreboot/+/55363/comment/2ca5511a_050e482a
PS2, Line 104: makes
> make
Done
https://review.coreboot.org/c/coreboot/+/55363/comment/9cb8ea0d_ff42ea46
PS2, Line 105: heci_reset();
> I notice heci_reset()is taking maximum of 1ms and min of 0.2ms in my tests. […]
Done
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Hello build bot (Jenkins), Sridhar Siricilla, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#8).
Change subject: soc/intel/common: Add HECI Reset flow in the CSE driver
......................................................................
soc/intel/common: Add HECI Reset flow in the CSE driver
This change is required as part of HECI Interface initialization in order
to put the host and CSE into a known good state for communication. Please
refer ME BIOS specification for more details. The change adds HECI
interface reset flow in the CSE driver. It enables coreboot to send HECI
commands before DRAM Init.
TEST=Run 50 cold reset cycles on Brya
Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com>
Change-Id: Ie078beaa33c6a35ae8f5f460d4354766aa710fba
---
M src/soc/intel/common/block/cse/cse.c
1 file changed, 3 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/55363/8
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Change subject: mb/siemens/mc_ehl: Use SPD data from HW-Info in the first place
......................................................................
Patch Set 1: Code-Review+2
(1 comment)
Patchset:
PS1:
tested on mc_ehl2, works well
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Change subject: util/cse_serger: Add command `create-cse-region`
......................................................................
Patch Set 3:
(1 comment)
File util/cbfstool/cse_serger.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130192):
https://review.coreboot.org/c/coreboot/+/58215/comment/c261a538_ae7d4742
PS3, Line 720: if (i == 0) {
braces {} are not necessary for any arm of this statement
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Change subject: util/cse_serger: Add command `create-cse-region`
......................................................................
util/cse_serger: Add command `create-cse-region`
This change adds a new command `create-cse-region` to cse_serger tool
which takes as inputs offset:size and file for different CSE
partitions and generates the entire CSE region image.
BUG=b:189177186
Change-Id: Ib087f5516e5beb6390831ef4e34b0b067d3fbc8b
Signed-off-by: Furquan Shaikh <furquan(a)google.com>
---
M util/cbfstool/cse_serger.c
1 file changed, 99 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/58215/3
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Change subject: util/cse_serger: Replace cse_layout_regions with array of regions
......................................................................
util/cse_serger: Replace cse_layout_regions with array of regions
This change replaces `struct cse_layout_regions` with an array of
`struct region` and introduces enums for DP and BP[1-4]. This makes it
easier to loop over the different regions in following changes.
BUG=b:189177186
Change-Id: If3cced4506d26dc534047cb9c385aaa9418d8522
Signed-off-by: Furquan Shaikh <furquan(a)google.com>
---
M util/cbfstool/bpdt_formats/bpdt_1_6.c
M util/cbfstool/bpdt_formats/bpdt_1_7.c
M util/cbfstool/cse_serger.c
M util/cbfstool/cse_serger.h
4 files changed, 49 insertions(+), 38 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/58214/3
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Change subject: mb/siemens/mc_ehl: Remove unneeded 'half_populated' variable
......................................................................
Patch Set 1: Code-Review+2
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Change subject: util/cse_serger: Add command `create-cse-region`
......................................................................
Patch Set 2:
(1 comment)
File util/cbfstool/cse_serger.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130188):
https://review.coreboot.org/c/coreboot/+/58215/comment/0a9a280a_f979be62
PS2, Line 720: if (i == 0) {
braces {} are not necessary for any arm of this statement
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