Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58166 )
Change subject: mb/siemens/mc_ehl2: Enable SD-Card
......................................................................
mb/siemens/mc_ehl2: Enable SD-Card
This mainboard has SD slot available and therefore it should be enabled.
Change-Id: I0c97e2dc589bf6b89713a473925e42a20278f457
Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58166
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh(a)siemens.com>
Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org>
---
M src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb
1 file changed, 1 insertion(+), 1 deletion(-)
Approvals:
build bot (Jenkins): Verified
Paul Menzel: Looks good to me, but someone else must approve
Werner Zeh: Looks good to me, approved
diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb
index 859f08b..21f4626 100644
--- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb
+++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb
@@ -217,7 +217,7 @@
device pci 19.2 on end # UART2
device pci 1a.0 on end # eMMC
- device pci 1a.1 off end # SD
+ device pci 1a.1 on end # SD
device pci 1a.3 off end # Intel Safety Island
device pci 1b.0 off end # Intel PSE I2C0
1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I0c97e2dc589bf6b89713a473925e42a20278f457
Gerrit-Change-Number: 58166
Gerrit-PatchSet: 3
Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com>
Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org>
Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-MessageType: merged
Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58174 )
Change subject: drivers/intel/dptf: return package with value
......................................................................
drivers/intel/dptf: return package with value
Return the package with a value for the dptf user space service.
This is required in write tpch method for pch device under dptf
driver.
BUG=b:198582766
BRANCH=None
TEST=Build FW and test on brya0 board
Change-Id: I64e1bb04a6115c7f93c84a5d6644101ac1d3d8ba
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58174
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
---
M src/drivers/intel/dptf/dptf.c
1 file changed, 2 insertions(+), 1 deletion(-)
Approvals:
build bot (Jenkins): Verified
Tim Wawrzynczak: Looks good to me, approved
diff --git a/src/drivers/intel/dptf/dptf.c b/src/drivers/intel/dptf/dptf.c
index 4a65127..c6ead0f 100644
--- a/src/drivers/intel/dptf/dptf.c
+++ b/src/drivers/intel/dptf/dptf.c
@@ -227,7 +227,8 @@
acpigen_write_zero();
/* The reason for returning a value here is a W/A for the ESIF shell */
acpigen_emit_byte(RETURN_OP);
- acpigen_write_package(0);
+ acpigen_write_package(1);
+ acpigen_write_zero();
acpigen_write_package_end();
acpigen_write_method_end();
}
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I64e1bb04a6115c7f93c84a5d6644101ac1d3d8ba
Gerrit-Change-Number: 58174
Gerrit-PatchSet: 2
Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com>
Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com>
Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com>
Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org>
Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-MessageType: merged
Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/57625 )
Change subject: soc/intel/tigerlake: Add ACPI addition for USB4/TBT latency optimization
......................................................................
soc/intel/tigerlake: Add ACPI addition for USB4/TBT latency optimization
The PCI-SIG engineering change requirement provides the ACPI additions
for firmware latency optimization. This change adds additional ACPI DSM
function with both of FW_RESET_TIME and FW_D3HOT_TO_D0_TIME to the
USB4/TBT topology. The OS is informed to reduce latency for upstream
ports while connecting USB4/TBT devices.
BUG=b:199757442
TEST=It was validated that the first connected device waits only 50ms
instead of 100ms and all functions work on Voxel board.
Signed-off-by: John Zhao <john.zhao(a)intel.com>
Change-Id: I5a19118b75ed0a78b7436f2f90295c03928300d7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57625
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
---
M src/soc/intel/tigerlake/acpi/tcss_pcierp.asl
1 file changed, 59 insertions(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Tim Wawrzynczak: Looks good to me, approved
diff --git a/src/soc/intel/tigerlake/acpi/tcss_pcierp.asl b/src/soc/intel/tigerlake/acpi/tcss_pcierp.asl
index 847d87e..7576564 100644
--- a/src/soc/intel/tigerlake/acpi/tcss_pcierp.asl
+++ b/src/soc/intel/tigerlake/acpi/tcss_pcierp.asl
@@ -1,5 +1,25 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * The PCI-SIG engineering change requirement provides the ACPI additions for firmware latency
+ * optimization. Both of FW_RESET_TIME and FW_D3HOT_TO_D0_TIME are applicable to the upstream
+ * port of the USB4/TBT topology.
+ */
+/* Number of microseconds to wait after a conventional reset */
+#define FW_RESET_TIME 50000
+
+/* Number of microseconds to wait after data link layer active report */
+#define FW_DL_UP_TIME 1
+
+/* Number of microseconds to wait after a function level reset */
+#define FW_FLR_RESET_TIME 1
+
+/* Number of microseconds to wait from D3 hot to D0 transition */
+#define FW_D3HOT_TO_D0_TIME 50000
+
+/* Number of microseconds to wait after setting the VF enable bit */
+#define FW_VF_ENABLE_TIME 1
+
OperationRegion (PXCS, SystemMemory, BASE(_ADR), 0x800)
Field (PXCS, AnyAcc, NoLock, Preserve)
{
@@ -64,10 +84,49 @@
Return (Buffer() { 0x00 })
}
+/*
+ * A bitmask of functions support
+ */
+Name(OPTS, Buffer(2) {0, 0})
+
Device (PXSX)
{
Name (_ADR, 0x00000000)
+ /*
+ * _DSM Device Specific Method
+ *
+ * Arg0: UUID: E5C937D0-3553-4d7a-9117-EA4D19C3434D
+ * Arg1: Revision ID: 3
+ * Arg2: Function index: 0, 9
+ * Arg3: Empty package
+ */
+ Method (_DSM, 4, Serialized)
+ {
+ If (Arg0 == ToUUID("E5C937D0-3553-4d7a-9117-EA4D19C3434D")) {
+ If (Arg1 >= 3) {
+ If (Arg2 == 0) {
+ /*
+ * Function index: 0
+ * Standard query - A bitmask of functions supported
+ */
+ CreateBitField(OPTS, 9, FUN9)
+ FUN9 = 1
+ Return (OPTS)
+ } ElseIf (Arg2 == 9) {
+ /*
+ * Function index: 9
+ * Specifying device readiness durations
+ */
+ Return (Package() { FW_RESET_TIME, FW_DL_UP_TIME,
+ FW_FLR_RESET_TIME, FW_D3HOT_TO_D0_TIME,
+ FW_VF_ENABLE_TIME })
+ }
+ }
+ }
+ Return (Buffer() { 0x0 })
+ }
+
Method (_PRW, 0)
{
Return (Package() { 0x69, 4 })
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I5a19118b75ed0a78b7436f2f90295c03928300d7
Gerrit-Change-Number: 57625
Gerrit-PatchSet: 4
Gerrit-Owner: John Zhao <john.zhao(a)intel.com>
Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com>
Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>
Gerrit-MessageType: merged
Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58135 )
Change subject: mb/google/guybrush/var/nipperkin: Enable RTD3 support for eMMC as NVMe
......................................................................
mb/google/guybrush/var/nipperkin: Enable RTD3 support for eMMC as NVMe
nipperkin has different H/W topology to guybrush that the eMMC device
is on a different GPP:
guybrush: GPP3
nipperkin: GPP2
Hence we need to enable RTD3 for nipperkin additionally which refers
to this one:
https://review.coreboot.org/c/coreboot/+/54967
BUG=b:200246826
BRANCH=guybrush
TEST=emerge-guybrush coreboot chromeos-bootimage
run suspend test on eMMC sku
Signed-off-by: Kevin Chiu <kevin.chiu(a)quantatw.com>
Change-Id: I1dca8f9e4739514d2d024374d8686f27b25582a9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58135
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Raul Rangel <rrangel(a)chromium.org>
---
M src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb
1 file changed, 7 insertions(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Raul Rangel: Looks good to me, approved
diff --git a/src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb b/src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb
index ecaf0cd..a53a6e5 100644
--- a/src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb
+++ b/src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb
@@ -32,6 +32,13 @@
chip soc/amd/cezanne
device domain 0 on
+ device ref gpp_bridge_2 on
+ # Required so the NVMe gets placed into D3 when entering S0i3.
+ chip drivers/pcie/rtd3/device
+ register "name" = ""NVME""
+ device pci 00.0 on end
+ end
+ end # NVMe
device ref gpp_bridge_a on # Internal GPP Bridge 0 to Bus A
device ref acp on
chip drivers/amd/i2s_machine_dev
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I1dca8f9e4739514d2d024374d8686f27b25582a9
Gerrit-Change-Number: 58135
Gerrit-PatchSet: 2
Gerrit-Owner: Kevin Chiu <kevin.chiu.17802(a)gmail.com>
Gerrit-Reviewer: Bhanu Prakash Maiya <bhanumaiya(a)google.com>
Gerrit-Reviewer: Eric Peers <epeers(a)google.com>
Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com>
Gerrit-Reviewer: Martin Roth <martinroth(a)google.com>
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Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-MessageType: merged