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Change subject: soc/intel/cannonlake: Lock PKG_CST_CONFIG_CONTROL MSR
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Patch Set 1: Code-Review+2
(1 comment)
Patchset:
PS1:
> Let me know which ones and I'll take care of them. […]
Thanks! Just these two (model_1067x, Skylake)
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Change subject: soc/intel/cannonlake: Enable Energy/Performance Bias control
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
> Who is "we"? […]
Sorry, I was wrong. Even FSP sets it by default (EnergyEfficientPState is 1 in bsf). However, it's only set when SkipMpInit == 0. So, all platforms >= ICL don't need to set it (SkipMpInit=0 forced). KBL should set the bit, too, though
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Change subject: cpu/intel/haswell: Lock PKG_CST_CONFIG_CONTROL MSR
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Patch Set 1: Code-Review+2
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Change subject: soc/intel/cannonlake: Enable Energy/Performance Bias control
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Change subject: soc/intel/*/cpu.c: Add missing space in comment
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Change subject: soc/intel/cannonlake: Enable Energy/Performance Bias control
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Patch Set 1:
(1 comment)
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PS1:
> IIRC we intentionally left this to the OS
Who is "we"?
Intel recommends setting POWER_CTL bit 18 in BIOS (boot firmware) to enable EPB control. The OS can then use the IA32_ENERGY_PERF_BIAS MSR to control EPB.
Yes, coreboot programs this MSR in the `set_energy_perf_bias()` function, but I'm pretty sure it's for backwards compatibility with older OSes without EPB support. OSes with EPB support simply overwrite coreboot's value as needed.
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Change subject: soc/intel/cannonlake: Lock PKG_CST_CONFIG_CONTROL MSR
......................................................................
Patch Set 1:
(1 comment)
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PS1:
> What about other platforms?
Let me know which ones and I'll take care of them. CB:58222 does Haswell and I can do model_1067x as well as Skylake. The rest I cannot test (or already set bit 15).
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Change subject: soc/intel/cannonlake: Lock PKG_CST_CONFIG_CONTROL MSR
......................................................................
Patch Set 1:
(1 comment)
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PS1:
> What about other platforms?
oh, well, on anything >= ICL fsp sets the lock when SkipMpInit == 0, which is the default there :/
We can set it on SKL, though
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