Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55294 )
Change subject: soc/amd/common/include/lpc: add definitions for LPC LDRQ control bits
......................................................................
soc/amd/common/include/lpc: add definitions for LPC LDRQ control bits
The definitions of bit 9 and 10 somehow got swapped between Picasso and
Renoir/Cezanne, so put those in the Cezanne-specific header file. The
reference code writes the same values to the raw bits in both, so we
probably would still get away with putting this into the common header,
but it's better to keep the defines consistent with the documentation in
all cases.
Register and bit definitions are from the Cezanne PPR #56569 Rev 3.03
and cross-checked to be compatible with the Picasso PPR #55570 Rev 3.16.
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: I3a033d63eeb06eed6783e4c3797ad8dea490db8d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55294
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Raul Rangel <rrangel(a)chromium.org>
---
M src/soc/amd/cezanne/include/soc/lpc.h
M src/soc/amd/common/block/include/amdblocks/lpc.h
2 files changed, 8 insertions(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Raul Rangel: Looks good to me, approved
diff --git a/src/soc/amd/cezanne/include/soc/lpc.h b/src/soc/amd/cezanne/include/soc/lpc.h
index fcdcd96..123a13f 100644
--- a/src/soc/amd/cezanne/include/soc/lpc.h
+++ b/src/soc/amd/cezanne/include/soc/lpc.h
@@ -3,6 +3,12 @@
#ifndef AMD_CEZANNE_LPC_H
#define AMD_CEZANNE_LPC_H
+/* LPC_MISC_CONTROL_BITS at D14F3x078 */
+/* The definitions of bits 9 and 10 are swapped on Picasso and older compared to Renoir/Cezanne
+ and newer, so we need to keep those in a SoC-specific header file. */
+#define LPC_LDRQ0_PU_EN BIT(10)
+#define LPC_LDRQ0_PD_EN BIT(9)
+
#define SPIROM_BASE_ADDRESS_REGISTER 0xa0
#define SPI_BASE_ALIGNMENT BIT(8)
#define SPI_BASE_RESERVED (BIT(5) | BIT(6) | BIT(7))
diff --git a/src/soc/amd/common/block/include/amdblocks/lpc.h b/src/soc/amd/common/block/include/amdblocks/lpc.h
index aa483e4..daa51f1 100644
--- a/src/soc/amd/common/block/include/amdblocks/lpc.h
+++ b/src/soc/amd/common/block/include/amdblocks/lpc.h
@@ -105,6 +105,8 @@
#define LPC_ALT_WIDEIO0_ENABLE BIT(0)
#define LPC_MISC_CONTROL_BITS 0x78
+#define LPC_LDRQ1_EN BIT(3)
+#define LPC_LDRQ0_EN BIT(2)
#define LPC_NOHOG BIT(0)
#define LPC_TRUSTED_PLATFORM_MODULE 0x7c
--
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Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57051 )
Change subject: mb/google/guybrush: Use register and bit defines for eSPI setup
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS3:
> You can add a comment when you move it.
ok. i've done a local change for that, so i won't forget. will push that when i've moved the functions which i'll try to do today
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Hello build bot (Jenkins), Julius Werner, Karthik Ramasubramanian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/58203
to look at the new patch set (#2).
Change subject: arch/x86/assembly_entry: Remove cpu_info
......................................................................
arch/x86/assembly_entry: Remove cpu_info
Since cpu_info() is no longer required to use threads, we no longer need
to initialize it in romstage or earlier. This code was also incomplete
since it didn't initialize the %gs segment.
BUG=b:179699789
TEST=Boot guybrush to OS
Signed-off-by: Raul E Rangel <rrangel(a)chromium.org>
Change-Id: I615b718e9f035ca68ecca9f57d7f4121db0c83b0
---
M src/arch/x86/assembly_entry.S
1 file changed, 0 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/58203/2
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Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58199 )
Change subject: arch/x86,cpu/x86,lib/thread: Remove usage of cpu_info from lib/thread
......................................................................
Patch Set 2:
(1 comment)
File src/lib/thread.c:
https://review.coreboot.org/c/coreboot/+/58199/comment/f64f1702_0db3dce7
PS1, Line 249: !boot_cpu()
> Yeah, I think an assert(boot_cpu()) in set_current_thread would make sense (and then you shouldn't n […]
Done
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Hello build bot (Jenkins), Julius Werner, Karthik Ramasubramanian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/58199
to look at the new patch set (#2).
Change subject: arch/x86,cpu/x86,lib/thread: Remove usage of cpu_info from lib/thread
......................................................................
arch/x86,cpu/x86,lib/thread: Remove usage of cpu_info from lib/thread
We only ever start and execute threads on the BSP. By explicitly
checking to see if the CPU is the BSP we can remove the dependency on
cpu_info. With this change we can in theory enable threads in bootblock
and romstage.
BUG=b:194391185, b:179699789
TEST=Boot guybrush to OS and verify coop multithreading still works
Suggested-by: Julius Werner <jwerner(a)chromium.org>
Signed-off-by: Raul E Rangel <rrangel(a)chromium.org>
Change-Id: Iea4622d52c36d529e100b7ea55f32c334acfdf3e
---
M src/arch/x86/include/arch/cpu.h
M src/cpu/x86/cpu_info.S.inc
M src/cpu/x86/lapic/lapic_cpu_init.c
M src/cpu/x86/mp_init.c
M src/include/thread.h
M src/lib/thread.c
6 files changed, 16 insertions(+), 23 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/58199/2
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Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58149 )
Change subject: soc/intel/*/me.c: Check more than PCI interface for printing ME info
......................................................................
Patch Set 1:
(1 comment)
File src/soc/intel/alderlake/me.c:
https://review.coreboot.org/c/coreboot/+/58149/comment/7fe53a6c_8101ae44
PS1, Line 103: !cse_is_hfs1_cws_normal() ||
: !cse_is_hfs1_com_normal() ||
: !cse_is_hfs1_com_soft_temp_disable())
: return;
> Just realised your point! Think this would account for that? […]
Frankly speaking, I *always* want these printed in my logs. We have found CSME bugs before by having these in the logs. Also you're already reading HFS1 several times here in order to avoid printing it later. For example, maybe the CSE is accidentally in soft temp disable but you wanted it in normal (and so these register dumps could be helpful). What is the harm in always printing these?
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Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58077 )
Change subject: mb/google/guybrush: drop printk in bootblock_mainboard_early_init
......................................................................
Patch Set 1: Code-Review+2
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Change subject: mb/google/guybrush/bootblock: add comment to PM_ACPI_CONF write
......................................................................
Patch Set 2: Code-Review+2
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Change subject: mb/google/guybrush: Use register and bit defines for eSPI setup
......................................................................
Patch Set 3: Code-Review+2
(1 comment)
Patchset:
PS3:
> should i add a comment about the bit definitions of LPC_LDRQ0_PU_EN and LPC_LDRQ0_PD_EN that were sw […]
You can add a comment when you move it.
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