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Change subject: mb/google/guybrush: Add PCIe Reset GPIO69 to SD DXIO Descriptor
......................................................................
Patch Set 3: Code-Review+2
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Change subject: mb/google/guybrush: Add PCIe Reset GPIO69 to SD DXIO Descriptor
......................................................................
Patch Set 3:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/58198/comment/501b1d0c_86c2a824
PS1, Line 16: Cq-Depend: chrome-internal:4157948
> Nit: Move this line right above Change-Id line.
Done
File src/mainboard/google/guybrush/port_descriptors.c:
https://review.coreboot.org/c/coreboot/+/58198/comment/67325e86_c33e4ff7
PS1, Line 54: NVME
> SSD_AUX_RST_L/AGPIO40 is in S5 domain. So I dont think FSP passes that GPIO to SMU. […]
You are correct Karthik
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Hello build bot (Jenkins), Raul Rangel, Marshall Dawson, Paul Menzel, Karthik Ramasubramanian, Felix Held,
I'd like you to reexamine a change. Please visit
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Change subject: mb/google/guybrush: Add PCIe Reset GPIO69 to SD DXIO Descriptor
......................................................................
mb/google/guybrush: Add PCIe Reset GPIO69 to SD DXIO Descriptor
coreboot normally owns PCIe resets for all Cezanne based systems.
However during S0i3 resume coreboot cannot intervene for S0 GPIOs
(S5 carry over fine) so we needed an alternate way to de-assert
this reset on guybrush. This change feeds in the given S0 reset
GPIO (69 in this case) so that SMU may de-assert this reset on
S0i3 resume.
BUG=b:199780346
TEST=With latest FSP verify SD device trains each of 10 cycles
Cq-Depend: chrome-internal:4157948
Change-Id: Ieee31651db30147fda84ee1aa31df7cb1c206356
Signed-off-by: Matt Papageorge <matthewpapa07(a)gmail.com>
---
M src/mainboard/google/guybrush/port_descriptors.c
1 file changed, 2 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/58198/3
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Hello build bot (Jenkins), Raul Rangel, Marshall Dawson, Paul Menzel, Karthik Ramasubramanian, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/58198
to look at the new patch set (#2).
Change subject: mb/google/guybrush: Add PCIe Reset GPIO69 to SD DXIO Descriptor
......................................................................
mb/google/guybrush: Add PCIe Reset GPIO69 to SD DXIO Descriptor
coreboot normally owns PCIe resets for all Cezanne based systems.
However during S0i3 resume coreboot cannot intervene for S0 GPIOs
(S5 carry over fine) so we needed an alternate way to de-assert
this reset on guybrush. This change feeds in the given S0 reset
GPIO (69 in this case) so that SMU may de-assert this reset on
S0i3 resume.
BUG=b:199780346
TEST=With latest FSP verify SD device trains each of 10 cycles
Cq-Depend: chrome-internal:4157948
Change-Id: Ieee31651db30147fda84ee1aa31df7cb1c206356
Signed-off-by: Matt Papageorge <matthewpapa07(a)gmail.com>
---
M src/mainboard/google/guybrush/port_descriptors.c
1 file changed, 2 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/58198/2
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Matt Papageorge has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58197 )
Change subject: vc/amd/fsp/cezanne: Add UPD fsp_owns_pcie_resets to FSP-M for Cezanne
......................................................................
Patch Set 4:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/58197/comment/a14c4556_1844b430
PS2, Line 7: vc/amd/fsp/cezanne: Update Cezanne FSP-M UPD definition
> Maybe be more specific: […]
Done
https://review.coreboot.org/c/coreboot/+/58197/comment/c462b497_7f29463d
PS2, Line 10: newer FSP
> If you have a version number, please add it.
Done
https://review.coreboot.org/c/coreboot/+/58197/comment/0a6a884b_317c0c1c
PS2, Line 15:
> Nit: Cq-Depend: chrome-internal:4170351
Done
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Change subject: vc/amd/fsp/cezanne: Add UPD fsp_owns_pcie_resets to FSP-M for Cezanne
......................................................................
vc/amd/fsp/cezanne: Add UPD fsp_owns_pcie_resets to FSP-M for Cezanne
Update UPD to include option for FSP to de-assert PCIe reset GPIOs as
specified in the DXIO descriptors. This change requires FSP version
1.0.4 revision 2 otherwise setting this value does affect any FSP
behavior.
BUG=b:199780346
TEST=Verify toggling this value is reflected in FSP
Cq-Depend: chrome-internal:4170351
Change-Id: I0dee05fb0a650f026c2f09581117fa7fb5f6a90a
Signed-off-by: Matt Papageorge <matthewpapa07(a)gmail.com>
---
M src/vendorcode/amd/fsp/cezanne/FspmUpd.h
1 file changed, 2 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/58197/4
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I'd like you to reexamine a change. Please visit
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to look at the new patch set (#3).
Change subject: vc/amd/fsp/cezanne: Add UPD fsp_owns_pcie_resets to FSP-M for Cezanne
......................................................................
vc/amd/fsp/cezanne: Add UPD fsp_owns_pcie_resets to FSP-M for Cezanne
Update UPD to include option for FSP to de-assert PCIe reset GPIOs.
This change requires FSP version 1.0.4 revision 2 otherwise setting
this value does affect any FSP behavior.
BUG=b:199780346
TEST=Verify toggling this value is reflected in FSP
Cq-Depend: chrome-internal:4170351
Change-Id: I0dee05fb0a650f026c2f09581117fa7fb5f6a90a
Signed-off-by: Matt Papageorge <matthewpapa07(a)gmail.com>
---
M src/vendorcode/amd/fsp/cezanne/FspmUpd.h
1 file changed, 2 insertions(+), 1 deletion(-)
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Sean Rhodes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58149 )
Change subject: soc/intel/*/me.c: Check more than PCI interface for printing ME info
......................................................................
Patch Set 1:
(1 comment)
File src/soc/intel/alderlake/me.c:
https://review.coreboot.org/c/coreboot/+/58149/comment/16a20427_6ac7886d
PS1, Line 103: !cse_is_hfs1_cws_normal() ||
: !cse_is_hfs1_com_normal() ||
: !cse_is_hfs1_com_soft_temp_disable())
: return;
> Frankly speaking, I *always* want these printed in my logs.
Same!
I'm just trying to avoid removing the below, as people complain when I've tried to remove existing things in the past (presumably it was added for some reason...):
```
- if (!is_cse_enabled())
- return;
```
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