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Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58157 )
Change subject: soc/intel/common/cse: Reorganize firmware update checks for CSE Lite
......................................................................
Patch Set 6: Code-Review+1
(1 comment)
File src/soc/intel/common/block/cse/cse_lite.c:
https://review.coreboot.org/c/coreboot/+/58157/comment/a5eb075c_957c8f64
PS5, Line 651: (status == CSE_UPDATE_CORRUPTED
> I added the check for corrupted case here because it seems safe to clear off data in case we encount […]
If the last update is downgrade case, then coreboot first clears the runtime data and triggers downgrade(erase & flash). So, during corrupted case, again clearing the data can be redundant.
Coreboot still handles data mismatch error by checking the boot partition status, but it involves additional global reset as CSE boots from RO when the CSE finds data error.
BTW, I am still fine with clearing the data proactively when coreboot finds CSE partition is corrupted.
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Change subject: util/autoport/bd82x6x.go: Fix includes
......................................................................
Patch Set 4:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/58210/comment/a3399d99_b8290ec5
PS3, Line 10: commit 661ad4666ca0e78195f6901fce7b44a7e56e6331;
> Why short hashes?
Done
https://review.coreboot.org/c/coreboot/+/58210/comment/26e0a10b_a0ef3709
PS3, Line 12: commit 0aad0531dcbdd0628f9d16e27e34abb3f6e183aa,
> Ditto.
Done
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Hello build bot (Jenkins), Paul Menzel, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/58210
to look at the new patch set (#4).
Change subject: util/autoport/bd82x6x.go: Fix includes
......................................................................
util/autoport/bd82x6x.go: Fix includes
Fix include of nvs.h to reflect commit 661ad4666c (ACPI: Select
ACPI_SOC_NVS only where suitable); and re-add <device/pci_ops.h>,
removed in commit 0aad0531dc (util/autoport/bd82x6x.go: Drop unused
includes), as the generated early_init.c uses pci_write_config16().
Signed-off-by: Nicholas Chin <nic.c3.14(a)gmail.com>
Change-Id: Ic1e97cfa7dce0e4d25f7a37c28d3635bdbf6c2a5
---
M util/autoport/bd82x6x.go
1 file changed, 2 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/58210/4
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Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58221 )
Change subject: soc/intel/cannonlake: Enable Energy/Performance Bias control
......................................................................
Patch Set 1: Code-Review+2
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Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58224 )
Change subject: soc/amd/common/block/include/psp_efs: use unsigned type for bitfield
......................................................................
soc/amd/common/block/include/psp_efs: use unsigned type for bitfield
For 1 bit long bitfields an unsigned type should be used.
TEST=Resulting image of a timeless build for google/guybrush results in
identical binary.
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: Ic630d1709174d90336746bc37da504437c12643c
---
M src/soc/amd/common/block/include/amdblocks/psp_efs.h
1 file changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/58224/1
diff --git a/src/soc/amd/common/block/include/amdblocks/psp_efs.h b/src/soc/amd/common/block/include/amdblocks/psp_efs.h
index 7afd295..77da70a 100644
--- a/src/soc/amd/common/block/include/amdblocks/psp_efs.h
+++ b/src/soc/amd/common/block/include/amdblocks/psp_efs.h
@@ -26,8 +26,8 @@
struct second_gen_efs { /* todo: expand for Server products */
- int gen:1; /* Client products only use bit 0 */
- int reserved:31;
+ uint32_t gen:1; /* Client products only use bit 0 */
+ uint32_t reserved:31;
} __attribute__((packed));
/* Copied from coreboot/util/amdfwtool.h */
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