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Change subject: soc/amd/common/include/lpc: add definitions for LPC LDRQ control bits
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Patch Set 2: Code-Review+2
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Change subject: soc/amd/cezanne/include/southbridge: add some more PM register defines
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Patch Set 1: Code-Review+2
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Change subject: mb/google/caroline: Update _HID for digitizer
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Patch Set 2:
(1 comment)
Patchset:
PS1:
> I'm not sure offhand, CAROLINE shipped with a 3. […]
ACPI0C50 is (one of) the _HID for i2c-hid in linux. A quick grep does not turn up that _HID in torvalds/master... just curious, do you have any kernel logs showing the driver binding?
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Change subject: mb/google/guybrush: Use register and bit defines for eSPI setup
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(1 comment)
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PS3:
should i add a comment about the bit definitions of LPC_LDRQ0_PU_EN and LPC_LDRQ0_PD_EN that were swapped between picasso and cezanne near the code that sets/clears those bits, so that if anyone ever decides to port this functionality back to picasso won't run into problems? my plan is to factor out this functionality and move it to soc/amd/cezanne in a follow up patch and i could add the comment there then
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Change subject: soc/amd/common/include/lpc: add definitions for LPC LDRQ control bits
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Patch Set 2:
(1 comment)
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PS2:
> Are we sure this wasn't a documentation error? Seems strange they would change the hardware like tha […]
i also find this change to be rather unexpected, but i was told that the cezanne ppr matches the hardware design and those definitions are also consistent with the ppr of some other newer socs; the change seems to be between picasso and renoir. i have verified that the cezanne ppr matches the hardware register definitions and that the reference code for picasso and cezanne ends up writing the same bit pattern into the register. no idea what the reason for this definition change was.
the register and bit definitions part of the ppr is generated from the register and bit definitions, so it's very unlikely that the register and bit documentation won't be consistent with the hardware design. also haven't found any bug in those parts of the pprs yet, so i'll just treat that as the main reference
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Change subject: soc/intel/*/cpu.c: Add missing space in comment
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Change subject: soc/intel/cannonlake: Enable Energy/Performance Bias control
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Patch Set 1:
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File src/soc/intel/cannonlake/cpu.c:
https://review.coreboot.org/c/coreboot/+/58221/comment/7d695ba9_8f58ea30
PS1, Line 54: 1 << 18
tbh I'd prefer if these bits were defined where MSR_POWER_CTL is, but since the others aren't too, let's keep it this way
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Change subject: soc/intel/cannonlake: Enable Energy/Performance Bias control
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