Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58100 )
Change subject: mb/ocp/deltalake: Fix SMBIOS type 9 bugs
......................................................................
mb/ocp/deltalake: Fix SMBIOS type 9 bugs
1. Fix PCIe slot capabilities not being really read from an IIO root
port device. The Hot-Plug capability of IIO root port cannot be
enabled due to FSP limitation (v2.1-0.2.2.0), but the code should
reflect the true capabilities by reading the root port device's CSR.
2. Initialize the characteristics flags to 0 in the for-loop to fix the
issue of the flags values persists to the next iterations.
Tested=On OCP Delta Lake, dmidecode -t 9 shows the expected results.
For example without the fix it shows 'Hot-plug devices are supported'
but in fact it's not:
System Slot Information
Designation: SSD1_M2_Data_Drive
Type: x4 PCI Express 3 x4
Current Usage: Available
Length: Short
ID: 1
Characteristics:
3.3 V is provided
PME signal is supported
Hot-plug devices are supported
Bus Address: 0000:00:1d.0
With the fix it shows the correct result:
Handle 0x0016, DMI type 9, 19 bytes
System Slot Information
Designation: SSD1_M2_Data_Drive
Type: x4 PCI Express 3 x4
Current Usage: Available
Length: Short
ID: 1
Characteristics:
3.3 V is provided
PME signal is supported
Bus Address: 0000:00:1d.0
Change-Id: Iea437cdf3da5410b6b7a749a1be970f0948d92d9
Signed-off-by: Johnny Lin <johnny_lin(a)wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58100
Reviewed-by: Johnny Lin <Johnny_Lin(a)wiwynn.com>
Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org>
Reviewed-by: Angel Pons <th3fanbus(a)gmail.com>
Reviewed-by: Jonathan Zhang <jonzhang(a)fb.com>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
---
M src/mainboard/ocp/deltalake/ramstage.c
1 file changed, 13 insertions(+), 9 deletions(-)
Approvals:
build bot (Jenkins): Verified
Paul Menzel: Looks good to me, but someone else must approve
Angel Pons: Looks good to me, approved
Jonathan Zhang: Looks good to me, approved
Johnny Lin: Looks good to me, but someone else must approve
diff --git a/src/mainboard/ocp/deltalake/ramstage.c b/src/mainboard/ocp/deltalake/ramstage.c
index 8d9de82..d8653b9 100644
--- a/src/mainboard/ocp/deltalake/ramstage.c
+++ b/src/mainboard/ocp/deltalake/ramstage.c
@@ -194,11 +194,9 @@
uint8_t sec_bus;
uint8_t slot_usage;
uint8_t pcie_config = 0;
- uint8_t characteristics_1 = 0;
- uint8_t characteristics_2 = 0;
uint32_t vendor_device_id;
uint8_t stack_busnos[MAX_IIO_STACK];
- pci_devfn_t pci_dev;
+ pci_devfn_t pci_dev_slot, pci_dev = 0;
unsigned int cap;
uint16_t sltcap;
@@ -209,6 +207,9 @@
stack_busnos[index] = get_stack_busno(index);
for (index = 0; index < ARRAY_SIZE(slotinfo); index++) {
+ uint8_t characteristics_1 = 0;
+ uint8_t characteristics_2 = 0;
+
if (pcie_config == PCIE_CONFIG_A) {
if (index == 0 || index == 1 || index == 2)
printk(BIOS_INFO, "Find Config-A slot: %s\n",
@@ -251,14 +252,14 @@
else
slot_length = SlotLengthShort;
- pci_dev = PCI_DEV(stack_busnos[slotinfo[index].stack],
+ pci_dev_slot = PCI_DEV(stack_busnos[slotinfo[index].stack],
slotinfo[index].dev_func >> 3, slotinfo[index].dev_func & 0x7);
- sec_bus = pci_s_read_config8(pci_dev, PCI_SECONDARY_BUS);
+ sec_bus = pci_s_read_config8(pci_dev_slot, PCI_SECONDARY_BUS);
if (sec_bus == 0xFF) {
slot_usage = SlotUsageUnknown;
} else {
- /* Checking for Slot device availability */
+ /* Checking for downstream device availability */
pci_dev = PCI_DEV(sec_bus, 0, 0);
vendor_device_id = pci_s_read_config32(pci_dev, 0);
if (vendor_device_id == 0xFFFFFFFF)
@@ -269,13 +270,16 @@
characteristics_1 |= SMBIOS_SLOT_3P3V; // Provides33Volts
characteristics_2 |= SMBIOS_SLOT_PME; // PmeSiganalSupported
-
- cap = pci_s_find_capability(pci_dev, PCI_CAP_ID_PCIE);
- sltcap = pci_s_read_config16(pci_dev, cap + PCI_EXP_SLTCAP);
+ /* Read IIO root port device CSR for slot capabilities */
+ cap = pci_s_find_capability(pci_dev_slot, PCI_CAP_ID_PCIE);
+ sltcap = pci_s_read_config16(pci_dev_slot, cap + PCI_EXP_SLTCAP);
if (sltcap & PCI_EXP_SLTCAP_HPC)
characteristics_2 |= SMBIOS_SLOT_HOTPLUG;
const uint16_t slot_id = index + 1;
+ /* According to SMBIOS spec, the BDF number should be the end
+ point on the slot, for now we keep using the root port's BDF to
+ be aligned with our UEFI reference BIOS. */
length += smbios_write_type9(current, handle,
slotinfo[index].slot_designator,
slotinfo[index].slot_type,
--
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Gerrit-Change-Id: Iea437cdf3da5410b6b7a749a1be970f0948d92d9
Gerrit-Change-Number: 58100
Gerrit-PatchSet: 9
Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com>
Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com>
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Gerrit-MessageType: merged
Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58172 )
Change subject: mb/siemens/mc_ehl2: Adjust Legacy IRQ routing for PCI devices
......................................................................
mb/siemens/mc_ehl2: Adjust Legacy IRQ routing for PCI devices
On this mainboard there is a legacy PCI device, which is connected to
the PCIe root port via a PCIe-2-PCI bridge. This device only supports
legacy interrupt routing. For this reason, we have to adjust the PIR8
register (0x3150) which is responsible for PCIe device 25h. The bridge
is connected to PCIe root port 7.
The following routing is required:
INTA#->PIRQC#, INTB#->PIRQD#, INTC#->PIRQA#, INTD#-> PIRQB#
TEST:
- Boot into system software
Change-Id: Id6bb8d00458c4d1e3fefd01ac3848078355868d9
Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58172
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh(a)siemens.com>
---
M src/mainboard/siemens/mc_ehl/variants/mc_ehl2/Makefile.inc
A src/mainboard/siemens/mc_ehl/variants/mc_ehl2/mainboard.c
2 files changed, 14 insertions(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Werner Zeh: Looks good to me, approved
diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/Makefile.inc b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/Makefile.inc
index 9cb0f1d..2903dd1 100644
--- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/Makefile.inc
+++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/Makefile.inc
@@ -3,6 +3,7 @@
bootblock-y += gpio.c
romstage-y += memory.c
ramstage-y += gpio.c
+ramstage-y += mainboard.c
SPD_SOURCES = mc_ehl2 # 0b000
LIB_SPD_DEPS := $(foreach f, $(SPD_SOURCES), \
diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/mainboard.c b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/mainboard.c
new file mode 100644
index 0000000..4ae857c
--- /dev/null
+++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/mainboard.c
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <baseboard/variants.h>
+#include <console/console.h>
+#include <intelblocks/pcr.h>
+#include <soc/pcr_ids.h>
+
+void variant_mainboard_final(void)
+{
+ /* PIR8 register mapping for PCIe root ports
+ INTA#->PIRQC#, INTB#->PIRQD#, INTC#->PIRQA#, INTD#-> PIRQB# */
+ pcr_write16(PID_ITSS, 0x3150, 0x1032);
+}
--
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Gerrit-Change-Id: Id6bb8d00458c4d1e3fefd01ac3848078355868d9
Gerrit-Change-Number: 58172
Gerrit-PatchSet: 3
Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com>
Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de>
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Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58171 )
Change subject: mb/siemens/mc_ehl: Add variant_mainboard_final()
......................................................................
mb/siemens/mc_ehl: Add variant_mainboard_final()
In upcoming patches, we need mainboard specific adjustments.
Change-Id: Icf9d829b19b2d26a39ad34be4658064083e9da6d
Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58171
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh(a)siemens.com>
Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org>
---
M src/mainboard/siemens/mc_ehl/mainboard.c
M src/mainboard/siemens/mc_ehl/variants/baseboard/include/baseboard/variants.h
2 files changed, 11 insertions(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Paul Menzel: Looks good to me, but someone else must approve
Werner Zeh: Looks good to me, approved
diff --git a/src/mainboard/siemens/mc_ehl/mainboard.c b/src/mainboard/siemens/mc_ehl/mainboard.c
index d347567..e64dbda 100644
--- a/src/mainboard/siemens/mc_ehl/mainboard.c
+++ b/src/mainboard/siemens/mc_ehl/mainboard.c
@@ -127,6 +127,9 @@
{
struct device *dev;
+ /* Do board specific things */
+ variant_mainboard_final();
+
if (CONFIG(PCI_ALLOW_BUS_MASTER_ANY_DEVICE)) {
/* Set Master Enable for on-board PCI devices if allowed. */
dev = dev_find_device(PCI_VENDOR_ID_SIEMENS, 0x403e, 0);
@@ -139,6 +142,11 @@
}
}
+/* The following function performs board specific things. */
+void __weak variant_mainboard_final(void)
+{
+}
+
struct chip_operations mainboard_ops = {
.init = mainboard_init,
.final = mainboard_final
diff --git a/src/mainboard/siemens/mc_ehl/variants/baseboard/include/baseboard/variants.h b/src/mainboard/siemens/mc_ehl/variants/baseboard/include/baseboard/variants.h
index bf05765..0893d99 100644
--- a/src/mainboard/siemens/mc_ehl/variants/baseboard/include/baseboard/variants.h
+++ b/src/mainboard/siemens/mc_ehl/variants/baseboard/include/baseboard/variants.h
@@ -15,4 +15,7 @@
/* This function returns SPD related FSP-M mainboard configs */
const struct mb_cfg *variant_memcfg_config(void);
+/* The following function performs board specific things. */
+void variant_mainboard_final(void);
+
#endif /*__BASEBOARD_VARIANTS_H__ */
--
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Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58221 )
Change subject: soc/intel/cannonlake: Enable Energy/Performance Bias control
......................................................................
Patch Set 1:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/58221/comment/9a618298_f75ed595
PS1, Line 10:
> How can this be tested? Does Linux log something?
The easiest way to see if this works is to check if the `set_energy_perf_bias()` function in coreboot prints something now. I'll try this later today, hopefully.
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Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58170 )
Change subject: mb/siemens/mc_ehl2: Enable LPC ComB
......................................................................
mb/siemens/mc_ehl2: Enable LPC ComB
Enable LPC ComB on this mainboard.
TEST:
- Boot Linux and check with 'dmesg | grep tty'
Change-Id: I7ec58685a723c177df18144011934b206e6425d0
Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58170
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh(a)siemens.com>
Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org>
---
M src/mainboard/siemens/mc_ehl/variants/mc_ehl2/Kconfig
1 file changed, 1 insertion(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Paul Menzel: Looks good to me, but someone else must approve
Werner Zeh: Looks good to me, approved
diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/Kconfig b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/Kconfig
index 0dbb800..b3d42ff 100644
--- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/Kconfig
+++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/Kconfig
@@ -3,6 +3,7 @@
config BOARD_SPECIFIC_OPTIONS
def_bool y
select DRIVER_INTEL_I210
+ select SOC_INTEL_COMMON_BLOCK_LPC_COMB_ENABLE
config FMDFILE
default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/mc_ehl.fmd"
1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
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Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58169 )
Change subject: mb/siemens/mc_ehl2: Disable INTEL_LPSS_UART_FOR_CONSOLE
......................................................................
mb/siemens/mc_ehl2: Disable INTEL_LPSS_UART_FOR_CONSOLE
This mainboard uses an eSPI-to-LPC bridge for console output. For this
reason, the internal LPSS UART must be disabled.
Change-Id: I86777cf719def331f4d257ddd94e9a87125ebce8
Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58169
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh(a)siemens.com>
Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org>
---
M src/mainboard/siemens/mc_ehl/variants/mc_ehl2/Kconfig
1 file changed, 0 insertions(+), 1 deletion(-)
Approvals:
build bot (Jenkins): Verified
Paul Menzel: Looks good to me, but someone else must approve
Werner Zeh: Looks good to me, approved
diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/Kconfig b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/Kconfig
index f577b24..0dbb800 100644
--- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/Kconfig
+++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/Kconfig
@@ -3,7 +3,6 @@
config BOARD_SPECIFIC_OPTIONS
def_bool y
select DRIVER_INTEL_I210
- select INTEL_LPSS_UART_FOR_CONSOLE
config FMDFILE
default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/mc_ehl.fmd"
1 is the latest approved patch-set.
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Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58167 )
Change subject: mb/siemens/mc_ehl2: Disable SATA Port 0
......................................................................
mb/siemens/mc_ehl2: Disable SATA Port 0
This mainboard has only SATA Port 1 available with no device sleep
feature.
Change-Id: I338833f2f9bcb407599cfc676ead0b8a9d7379bd
Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58167
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh(a)siemens.com>
Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org>
---
M src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb
1 file changed, 1 insertion(+), 1 deletion(-)
Approvals:
build bot (Jenkins): Verified
Paul Menzel: Looks good to me, but someone else must approve
Werner Zeh: Looks good to me, approved
diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb
index 21f4626..062ac5f 100644
--- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb
+++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb
@@ -87,7 +87,7 @@
# Storage (SATA/SDCARD/EMMC) related UPDs
register "SataSalpSupport" = "0"
- register "SataPortsEnable[0]" = "1"
+ register "SataPortsEnable[0]" = "0"
register "SataPortsEnable[1]" = "1"
register "SataPortsDevSlp[0]" = "0"
register "SataPortsDevSlp[1]" = "0"
1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
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