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Patrick Rudolph has uploaded a new patch set (#7) to the change originally created by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/56017 )
Change subject: Documentation: Improve x86_64
......................................................................
Documentation: Improve x86_64
* Move to own markdown document
* Better describe current implementation
* Update TODOs
Change-Id: Ia5ba51be629a8c878aad64d3297176457cf8e855
Signed-off-by: Patrick Rudolph <siro(a)das-labor.org>
---
M Documentation/arch/x86/index.md
A Documentation/arch/x86/x86_64.md
2 files changed, 154 insertions(+), 92 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/56017/7
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Change subject: mb/google/caroline: Update _HID for digitizer
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
> Why does it work in Chromium OS?
I'm not sure offhand, CAROLINE shipped with a 3.1x kernel IIRC, so I'd have to go back to the chromium kernel source and check. For current 5.x kernels, this change is needed for it to work
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Hello build bot (Jenkins), Paul Menzel, Angel Pons, Michael Niewöhner,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#2).
Change subject: purism/librem_bdw: add support for ACPI brightness controls
......................................................................
purism/librem_bdw: add support for ACPI brightness controls
Test: build/boot Purism Librem 13v1, verify brightness controls
work under Windows 10/11 with Tianocore payload.
Change-Id: I27d04655adcd4a5dd42b025cfccb508cfd7aaeae
Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com>
---
M src/mainboard/purism/librem_bdw/devicetree.cb
M src/mainboard/purism/librem_bdw/dsdt.asl
2 files changed, 4 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/58187/2
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Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58187 )
Change subject: purism/librem_bdw: add support for ACPI brightness controls
......................................................................
Patch Set 1:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/58187/comment/adbc9179_3c960598
PS1, Line 10: Windows
> Which version?
it honestly doesn't matter, Windows + UEFI = ACPI needed for LCD backlight controls with Intel iGPU. But I'll edit the commit msg
https://review.coreboot.org/c/coreboot/+/58187/comment/53e5a918_cec95bca
PS1, Line 11:
> The i915 kernel driver in Linux exposes its own brightness control devicec, so I'm pretty sure the a […]
yes, ACPI brightness controls are not needed under Linux. This just brings the librem_bdw boards up to par with librem_skl and librem_cnl - not sure why it wasn't done at the same time
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build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58118 )
Change subject: acpigen,soc/amd/cezanne,intel/{common,skl}: rework CPPC table passing
......................................................................
Patch Set 8:
(10 comments)
File src/soc/amd/cezanne/cppc.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130138):
https://review.coreboot.org/c/coreboot/+/58118/comment/ef1ff955_f037b730
PS8, Line 15: [CPPC_HIGHEST_PERF] = CPPC_REG_MSR(MSR_CPPC_CAPABILITY_1, SHIFT_CPPC_CAPABILITY_1_HIGHEST_PERF, 8),
line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130138):
https://review.coreboot.org/c/coreboot/+/58118/comment/01906c14_0d3242fc
PS8, Line 16: [CPPC_NOMINAL_PERF] = CPPC_REG_MSR(MSR_CPPC_CAPABILITY_1, SHIFT_CPPC_CAPABILITY_1_NOMINAL_PERF, 8),
line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130138):
https://review.coreboot.org/c/coreboot/+/58118/comment/1ee333ab_4962b473
PS8, Line 17: [CPPC_LOWEST_NONL_PERF] = CPPC_REG_MSR(MSR_CPPC_CAPABILITY_1, SHIFT_CPPC_CAPABILITY_1_LOW_NON_LIN_PERF, 8),
line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130138):
https://review.coreboot.org/c/coreboot/+/58118/comment/8999195c_21c47942
PS8, Line 18: [CPPC_LOWEST_PERF] = CPPC_REG_MSR(MSR_CPPC_CAPABILITY_1, SHIFT_CPPC_CAPABILITY_1_LOWEST_PERF, 8),
line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130138):
https://review.coreboot.org/c/coreboot/+/58118/comment/350164b4_95b4e807
PS8, Line 20: [CPPC_DESIRED_PERF] = CPPC_REG_MSR(MSR_CPPC_REQUEST, SHIFT_CPPC_REQUEST_DES_PERF, 8),
line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130138):
https://review.coreboot.org/c/coreboot/+/58118/comment/e298b8b2_43916d64
PS8, Line 21: [CPPC_MIN_PERF] = CPPC_REG_MSR(MSR_CPPC_REQUEST, SHIFT_CPPC_REQUEST_MIN_PERF, 8),
line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130138):
https://review.coreboot.org/c/coreboot/+/58118/comment/fc6f1320_287dfeb2
PS8, Line 22: [CPPC_MAX_PERF] = CPPC_REG_MSR(MSR_CPPC_REQUEST, SHIFT_CPPC_REQUEST_MAX_PERF, 8),
line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130138):
https://review.coreboot.org/c/coreboot/+/58118/comment/5eddd3e5_28ffb09c
PS8, Line 26: [CPPC_REF_PERF_COUNTER] = CPPC_REG_MSR(MSR_MAX_PERFORMANCE_FREQUENCY_CLOCK_COUNT, 0, 64),
line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130138):
https://review.coreboot.org/c/coreboot/+/58118/comment/94405c13_29ce9ae3
PS8, Line 27: [CPPC_DELIVERED_PERF_COUNTER] = CPPC_REG_MSR(MSR_ACTUAL_PERFORMANCE_FREQUENCY_CLOCK_COUNT, 0, 64),
line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130138):
https://review.coreboot.org/c/coreboot/+/58118/comment/afa126b4_c46c0caf
PS8, Line 34: [CPPC_PERF_PREF] = CPPC_REG_MSR(MSR_CPPC_REQUEST, SHIFT_CPPC_REQUEST_ENERGY_PERF_PREF, 8),
line over 96 characters
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Change subject: acpigen,soc/amd,cpu/intel: rework static DWORD for CPPC table
......................................................................
Patch Set 10:
(15 comments)
File src/cpu/intel/common/common_init.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130137):
https://review.coreboot.org/c/coreboot/+/57886/comment/d3a215e1_3dc83cd8
PS10, Line 108: config->entries[CPPC_HIGHEST_PERF] = CPPC_REG_MSR(IA32_HWP_CAPABILITIES, 0, 8);
line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130137):
https://review.coreboot.org/c/coreboot/+/57886/comment/04767d70_642fc733
PS10, Line 110: config->entries[CPPC_LOWEST_NONL_PERF] = CPPC_REG_MSR(IA32_HWP_CAPABILITIES, 16, 8);
line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130137):
https://review.coreboot.org/c/coreboot/+/57886/comment/3fe98d0e_d2908f5c
PS10, Line 111: config->entries[CPPC_LOWEST_PERF] = CPPC_REG_MSR(IA32_HWP_CAPABILITIES, 24, 8);
line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130137):
https://review.coreboot.org/c/coreboot/+/57886/comment/b5d4a1bb_e13206bc
PS10, Line 112: config->entries[CPPC_GUARANTEED_PERF] = CPPC_REG_MSR(IA32_HWP_CAPABILITIES, 8, 8);
line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130137):
https://review.coreboot.org/c/coreboot/+/57886/comment/f1531f06_bb90cbf9
PS10, Line 128: config->entries[CPPC_AUTO_ACTIVITY_WINDOW] = CPPC_REG_MSR(IA32_HWP_REQUEST, 32, 10);
line over 96 characters
File src/soc/amd/cezanne/cppc.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130137):
https://review.coreboot.org/c/coreboot/+/57886/comment/caa37326_f042d72d
PS10, Line 18: config->entries[CPPC_HIGHEST_PERF] = CPPC_REG_MSR(MSR_CPPC_CAPABILITY_1, SHIFT_CPPC_CAPABILITY_1_HIGHEST_PERF, 8);
line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130137):
https://review.coreboot.org/c/coreboot/+/57886/comment/d667b70a_1614e9c7
PS10, Line 19: config->entries[CPPC_NOMINAL_PERF] = CPPC_REG_MSR(MSR_CPPC_CAPABILITY_1, SHIFT_CPPC_CAPABILITY_1_NOMINAL_PERF, 8);
line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130137):
https://review.coreboot.org/c/coreboot/+/57886/comment/c78c95aa_23dc2c4f
PS10, Line 20: config->entries[CPPC_LOWEST_NONL_PERF] = CPPC_REG_MSR(MSR_CPPC_CAPABILITY_1, SHIFT_CPPC_CAPABILITY_1_LOW_NON_LIN_PERF, 8);
line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130137):
https://review.coreboot.org/c/coreboot/+/57886/comment/965d6e98_3ce94650
PS10, Line 21: config->entries[CPPC_LOWEST_PERF] = CPPC_REG_MSR(MSR_CPPC_CAPABILITY_1, SHIFT_CPPC_CAPABILITY_1_LOWEST_PERF, 8);
line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130137):
https://review.coreboot.org/c/coreboot/+/57886/comment/85578ce3_d22ab0d0
PS10, Line 23: config->entries[CPPC_DESIRED_PERF] = CPPC_REG_MSR(MSR_CPPC_REQUEST, SHIFT_CPPC_REQUEST_DES_PERF, 8);
line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130137):
https://review.coreboot.org/c/coreboot/+/57886/comment/c130b01c_cc5369d5
PS10, Line 24: config->entries[CPPC_MIN_PERF] = CPPC_REG_MSR(MSR_CPPC_REQUEST, SHIFT_CPPC_REQUEST_MIN_PERF, 8);
line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130137):
https://review.coreboot.org/c/coreboot/+/57886/comment/c7074cd1_50ba87cf
PS10, Line 25: config->entries[CPPC_MAX_PERF] = CPPC_REG_MSR(MSR_CPPC_REQUEST, SHIFT_CPPC_REQUEST_MAX_PERF, 8);
line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130137):
https://review.coreboot.org/c/coreboot/+/57886/comment/78aa79f2_a619993f
PS10, Line 29: config->entries[CPPC_REF_PERF_COUNTER] = CPPC_REG_MSR(MSR_MAX_PERFORMANCE_FREQUENCY_CLOCK_COUNT, 0, 64);
line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130137):
https://review.coreboot.org/c/coreboot/+/57886/comment/c47ca34f_e3fa44c7
PS10, Line 30: config->entries[CPPC_DELIVERED_PERF_COUNTER] = CPPC_REG_MSR(MSR_ACTUAL_PERFORMANCE_FREQUENCY_CLOCK_COUNT, 0, 64);
line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130137):
https://review.coreboot.org/c/coreboot/+/57886/comment/8a23a179_51f6d0dc
PS10, Line 39: config->entries[CPPC_PERF_PREF] = CPPC_REG_MSR(MSR_CPPC_REQUEST, SHIFT_CPPC_REQUEST_ENERGY_PERF_PREF, 8);
line over 96 characters
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build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57888 )
Change subject: soc/amd/cezanne,soc/intel/common: rework CPPC table generation
......................................................................
Patch Set 13:
(15 comments)
File src/cpu/intel/common/common_init.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130136):
https://review.coreboot.org/c/coreboot/+/57888/comment/25bde6dc_6531b494
PS13, Line 108: config->regs[CPPC_HIGHEST_PERF] = ACPI_REG_MSR(IA32_HWP_CAPABILITIES, 0, 8);
line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130136):
https://review.coreboot.org/c/coreboot/+/57888/comment/634ec17a_f9dbf8f6
PS13, Line 110: config->regs[CPPC_LOWEST_NONL_PERF] = ACPI_REG_MSR(IA32_HWP_CAPABILITIES, 16, 8);
line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130136):
https://review.coreboot.org/c/coreboot/+/57888/comment/3f894a84_079206e1
PS13, Line 111: config->regs[CPPC_LOWEST_PERF] = ACPI_REG_MSR(IA32_HWP_CAPABILITIES, 24, 8);
line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130136):
https://review.coreboot.org/c/coreboot/+/57888/comment/0376ecdf_7326e5ea
PS13, Line 112: config->regs[CPPC_GUARANTEED_PERF] = ACPI_REG_MSR(IA32_HWP_CAPABILITIES, 8, 8);
line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130136):
https://review.coreboot.org/c/coreboot/+/57888/comment/fe878dd1_0bbd5f5a
PS13, Line 135: config->regs[CPPC_AUTO_ACTIVITY_WINDOW] = ACPI_REG_MSR(IA32_HWP_REQUEST, 32, 10);
line over 96 characters
File src/soc/amd/cezanne/cppc.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130136):
https://review.coreboot.org/c/coreboot/+/57888/comment/61aea07e_9fbbfc93
PS13, Line 18: config->regs[CPPC_HIGHEST_PERF] = ACPI_REG_MSR(MSR_CPPC_CAPABILITY_1, SHIFT_CPPC_CAPABILITY_1_HIGHEST_PERF, 8);
line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130136):
https://review.coreboot.org/c/coreboot/+/57888/comment/2bd2cc1f_750afa4a
PS13, Line 19: config->regs[CPPC_NOMINAL_PERF] = ACPI_REG_MSR(MSR_CPPC_CAPABILITY_1, SHIFT_CPPC_CAPABILITY_1_NOMINAL_PERF, 8);
line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130136):
https://review.coreboot.org/c/coreboot/+/57888/comment/d1c781cf_fe1f8735
PS13, Line 20: config->regs[CPPC_LOWEST_NONL_PERF] = ACPI_REG_MSR(MSR_CPPC_CAPABILITY_1, SHIFT_CPPC_CAPABILITY_1_LOW_NON_LIN_PERF, 8);
line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130136):
https://review.coreboot.org/c/coreboot/+/57888/comment/bd7f3cca_5324dfdd
PS13, Line 21: config->regs[CPPC_LOWEST_PERF] = ACPI_REG_MSR(MSR_CPPC_CAPABILITY_1, SHIFT_CPPC_CAPABILITY_1_LOWEST_PERF, 8);
line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130136):
https://review.coreboot.org/c/coreboot/+/57888/comment/be47ab3b_e19b8281
PS13, Line 23: config->regs[CPPC_DESIRED_PERF] = ACPI_REG_MSR(MSR_CPPC_REQUEST, SHIFT_CPPC_REQUEST_DES_PERF, 8);
line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130136):
https://review.coreboot.org/c/coreboot/+/57888/comment/85d12b99_2d435bee
PS13, Line 24: config->regs[CPPC_MIN_PERF] = ACPI_REG_MSR(MSR_CPPC_REQUEST, SHIFT_CPPC_REQUEST_MIN_PERF, 8);
line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130136):
https://review.coreboot.org/c/coreboot/+/57888/comment/02b2a751_04d01848
PS13, Line 25: config->regs[CPPC_MAX_PERF] = ACPI_REG_MSR(MSR_CPPC_REQUEST, SHIFT_CPPC_REQUEST_MAX_PERF, 8);
line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130136):
https://review.coreboot.org/c/coreboot/+/57888/comment/919917f4_ef3aa757
PS13, Line 29: config->regs[CPPC_REF_PERF_COUNTER] = ACPI_REG_MSR(MSR_MAX_PERFORMANCE_FREQUENCY_CLOCK_COUNT, 0, 64);
line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130136):
https://review.coreboot.org/c/coreboot/+/57888/comment/6cc4e94b_c341a026
PS13, Line 30: config->regs[CPPC_DELIVERED_PERF_COUNTER] = ACPI_REG_MSR(MSR_ACTUAL_PERFORMANCE_FREQUENCY_CLOCK_COUNT, 0, 64);
line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130136):
https://review.coreboot.org/c/coreboot/+/57888/comment/8c490252_309fd2e4
PS13, Line 39: config->regs[CPPC_PERF_PREF] = ACPI_REG_MSR(MSR_CPPC_REQUEST, SHIFT_CPPC_REQUEST_ENERGY_PERF_PREF, 8);
line over 96 characters
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Gerrit-Comment-Date: Sat, 09 Oct 2021 10:21:19 +0000
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Attention is currently required from: Lance Zhao, Felix Singer, Matt Delco, Nico Huber, Furquan Shaikh, Paul Menzel, Tim Wawrzynczak, Ravindra, Subrata Banik, Lean Sheng Tan, Patrick Rudolph.
Hello Felix Singer, Lance Zhao, build bot (Jenkins), Matt Delco, Nico Huber, Furquan Shaikh, Paul Menzel, Tim Wawrzynczak, Ravindra, Subrata Banik, Lean Sheng Tan, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/47543
to look at the new patch set (#30).
Change subject: soc/intel/{icl,tgl,jsl,ehl}: enable ACPI CPPC entries
......................................................................
soc/intel/{icl,tgl,jsl,ehl}: enable ACPI CPPC entries
Enable CPPC entries generation, needed for Intel SpeedShift.
This can be tested by checking sysfs in Linux:
$ grep . /sys/devices/system/cpu/cpu?/acpi_cppc/*perf
The output should look like this, while the values may differ:
/sys/devices/system/cpu/cpu0/acpi_cppc/highest_perf:28
/sys/devices/system/cpu/cpu0/acpi_cppc/lowest_nonlinear_perf:5
/sys/devices/system/cpu/cpu0/acpi_cppc/lowest_perf:1
/sys/devices/system/cpu/cpu0/acpi_cppc/nominal_perf:24
/sys/devices/system/cpu/cpu1/acpi_cppc/highest_perf:28
/sys/devices/system/cpu/cpu1/acpi_cppc/lowest_nonlinear_perf:5
...
Change-Id: I910b4e17d4044f1bf1ecfa0643ac62fc7a8cb51b
Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de>
---
M src/soc/intel/elkhartlake/Kconfig
M src/soc/intel/icelake/Kconfig
M src/soc/intel/jasperlake/Kconfig
M src/soc/intel/tigerlake/Kconfig
4 files changed, 4 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/47543/30
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Attention is currently required from: Felix Singer, Lance Zhao, Jason Glenesk, Raul Rangel, Nico Huber, Furquan Shaikh, Marshall Dawson, Tim Wawrzynczak, Angel Pons, Patrick Rudolph, Felix Held.
Hello Felix Singer, build bot (Jenkins), Raul Rangel, Furquan Shaikh, Paul Menzel, Angel Pons, Patrick Rudolph, Lance Zhao, Jason Glenesk, Nico Huber, Marshall Dawson, Tim Wawrzynczak, Tim Wawrzynczak, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/58118
to look at the new patch set (#8).
Change subject: acpigen,soc/amd/cezanne,intel/{common,skl}: rework CPPC table passing
......................................................................
acpigen,soc/amd/cezanne,intel/{common,skl}: rework CPPC table passing
Instead of passing around a magic struct with embedded version, use
pointers and pass the CPPC version directly to the ACPI generator.
Test: dumped SSDT before and after do not differ.
Change-Id: I26c5e80c2a16a50ed73245c7c32d61b17e45c22a
Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de>
---
M src/acpi/acpigen.c
M src/cpu/intel/common/common.h
M src/cpu/intel/common/common_init.c
M src/include/acpi/acpi.h
M src/include/acpi/acpigen.h
M src/soc/amd/cezanne/cppc.c
M src/soc/amd/cezanne/include/soc/cppc.h
M src/soc/intel/common/block/acpi/acpi.c
M src/soc/intel/skylake/acpi.c
9 files changed, 99 insertions(+), 108 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/58118/8
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