Attention is currently required from: Felix Singer, Raul Rangel, Furquan Shaikh, Paul Menzel, Angel Pons, Subrata Banik, Kyösti Mälkki, Patrick Rudolph, Jason Glenesk, Matt Delco, Nico Huber, Marshall Dawson, Tim Wawrzynczak, Felix Held.
Hello Felix Singer, build bot (Jenkins), Raul Rangel, Furquan Shaikh, Paul Menzel, Angel Pons, Subrata Banik, Kyösti Mälkki, Patrick Rudolph, Lance Zhao, Jason Glenesk, Matt Delco, Nico Huber, Marshall Dawson, Tim Wawrzynczak, Tim Wawrzynczak, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/57886
to look at the new patch set (#10).
Change subject: acpigen,soc/amd,cpu/intel: rework static DWORD for CPPC table
......................................................................
acpigen,soc/amd,cpu/intel: rework static DWORD for CPPC table
Some elements in the ACPI CPPC table allow static DWORDs. Instead of
using a fake register resource, use a tagged union with the two types
"register" and "DWORD" and respective macros for CPPC table entries.
Test: dumped SSDT before and after do not differ.
Change-Id: Ib853261b5c0ea87ae2424fed188f2d1872be9a06
Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de>
---
M src/acpi/acpigen.c
M src/cpu/intel/common/common.h
M src/cpu/intel/common/common_init.c
M src/include/acpi/acpigen.h
M src/soc/amd/cezanne/cppc.c
M src/soc/amd/cezanne/include/soc/cppc.h
6 files changed, 73 insertions(+), 57 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/57886/10
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Hello Felix Singer, build bot (Jenkins), Raul Rangel, Furquan Shaikh, Paul Menzel, Angel Pons, Subrata Banik, Kyösti Mälkki, Patrick Rudolph, Lance Zhao, Jason Glenesk, Matt Delco, Nico Huber, Marshall Dawson, Tim Wawrzynczak, Tim Wawrzynczak, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/57888
to look at the new patch set (#14).
Change subject: soc/amd/cezanne,soc/intel/common: rework CPPC table generation
......................................................................
soc/amd/cezanne,soc/intel/common: rework CPPC table generation
Make use of the newly introduced ACPI macros for CPPC table generation
that currently exists of a bunch of confusing assignments of structs
that only get partially filled.
Test: dumped SSDT before and after do not differ.
Change-Id: I844d191b1134b98e409240ede71e2751e51e2159
Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de>
---
M src/cpu/intel/common/common_init.c
M src/include/acpi/acpi.h
M src/soc/amd/cezanne/cppc.c
3 files changed, 58 insertions(+), 317 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/57888/14
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Attention is currently required from: Felix Singer, Lance Zhao, Jason Glenesk, Raul Rangel, Nico Huber, Furquan Shaikh, Marshall Dawson, Tim Wawrzynczak, Angel Pons, Patrick Rudolph, Felix Held.
Hello Felix Singer, build bot (Jenkins), Raul Rangel, Furquan Shaikh, Paul Menzel, Angel Pons, Patrick Rudolph, Lance Zhao, Jason Glenesk, Nico Huber, Marshall Dawson, Tim Wawrzynczak, Tim Wawrzynczak, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/58118
to look at the new patch set (#7).
Change subject: acpigen,soc/amd/cezanne,intel/{common,skl}: rework CPPC table passing
......................................................................
acpigen,soc/amd/cezanne,intel/{common,skl}: rework CPPC table passing
Instead of passing around a magic struct with embedded version, use
pointers and pass the CPPC version directly to the ACPI generator.
Test: dumped SSDT before and after do not differ.
Change-Id: I26c5e80c2a16a50ed73245c7c32d61b17e45c22a
Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de>
---
M src/acpi/acpigen.c
M src/cpu/intel/common/common.h
M src/cpu/intel/common/common_init.c
M src/include/acpi/acpi.h
M src/include/acpi/acpigen.h
M src/soc/amd/cezanne/cppc.c
M src/soc/amd/cezanne/include/soc/cppc.h
M src/soc/intel/common/block/acpi/acpi.c
M src/soc/intel/skylake/acpi.c
9 files changed, 99 insertions(+), 108 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/58118/7
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Hello Felix Singer, build bot (Jenkins), Raul Rangel, Furquan Shaikh, Paul Menzel, Angel Pons, Subrata Banik, Kyösti Mälkki, Patrick Rudolph, Lance Zhao, Jason Glenesk, Matt Delco, Nico Huber, Marshall Dawson, Tim Wawrzynczak, Tim Wawrzynczak, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/57886
to look at the new patch set (#9).
Change subject: acpigen,soc/amd,cpu/intel: rework static DWORD for CPPC table
......................................................................
acpigen,soc/amd,cpu/intel: rework static DWORD for CPPC table
Some elements in the ACPI CPPC table allow static DWORDs. Instead of
using a fake register resource, use a tagged union with the two types
"register" and "DWORD" and respective macros for CPPC table entries.
Test: dumped SSDT before and after do not differ.
Change-Id: Ib853261b5c0ea87ae2424fed188f2d1872be9a06
Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de>
---
M src/acpi/acpigen.c
M src/cpu/intel/common/common.h
M src/cpu/intel/common/common_init.c
M src/include/acpi/acpigen.h
M src/soc/amd/cezanne/cppc.c
M src/soc/amd/cezanne/include/soc/cppc.h
6 files changed, 73 insertions(+), 57 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/57886/9
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Hello Felix Singer, build bot (Jenkins), Raul Rangel, Furquan Shaikh, Paul Menzel, Angel Pons, Subrata Banik, Kyösti Mälkki, Patrick Rudolph, Lance Zhao, Jason Glenesk, Matt Delco, Nico Huber, Marshall Dawson, Tim Wawrzynczak, Tim Wawrzynczak, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/57888
to look at the new patch set (#13).
Change subject: soc/amd/cezanne,soc/intel/common: rework CPPC table generation
......................................................................
soc/amd/cezanne,soc/intel/common: rework CPPC table generation
Make use of the newly introduced ACPI macros for CPPC table generation
that currently exists of a bunch of confusing assignments of structs
that only get filled partly.
Test: dumped SSDT before and after do not differ.
Change-Id: I844d191b1134b98e409240ede71e2751e51e2159
Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de>
---
M src/cpu/intel/common/common_init.c
M src/include/acpi/acpi.h
M src/soc/amd/cezanne/cppc.c
3 files changed, 58 insertions(+), 317 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/57888/13
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Zhi7 Li has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58196 )
Change subject: mb/google/dedede/var/sasukette: Generate SPD ID for Samsung K4U6E3S4AB-MGCL
......................................................................
Patch Set 3:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/58196/comment/bf319ef9_f8b85f4d
PS2, Line 7: mb/google/dedede/var/sasukette: Generate SPD ID for supported memory parts
> Maybe: […]
Done
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Hello build bot (Jenkins), Paul Menzel, Weimin Wu,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/58196
to look at the new patch set (#3).
Change subject: mb/google/dedede/var/sasukette: Generate SPD ID for Samsung K4U6E3S4AB-MGCL
......................................................................
mb/google/dedede/var/sasukette: Generate SPD ID for Samsung K4U6E3S4AB-MGCL
Add supported memory parts in the mem_parts_used.txt and generate the
SPD ID for the memory parts. The memory parts being added are:
1. Samsung K4U6E3S4AB-MGCL
BUG=b:202480992
TEST=emerge-dedede coreboot
Signed-off-by: Zhi Li <lizhi7(a)huaqin.corp-partner.google.com>
Change-Id: I811f32defd50a940a09f238d38c962d2caf42855
---
M src/mainboard/google/dedede/variants/sasukette/memory/Makefile.inc
M src/mainboard/google/dedede/variants/sasukette/memory/dram_id.generated.txt
M src/mainboard/google/dedede/variants/sasukette/memory/mem_parts_used.txt
3 files changed, 3 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/58196/3
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