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build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58118 )
Change subject: acpigen,soc/amd/cezanne,intel/{common,skl}: rework CPPC table passing
......................................................................
Patch Set 6:
(10 comments)
File src/soc/amd/cezanne/cppc.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130116):
https://review.coreboot.org/c/coreboot/+/58118/comment/e9469bd3_121731c6
PS6, Line 15: [CPPC_HIGHEST_PERF] = CPPC_REG_MSR(MSR_CPPC_CAPABILITY_1, SHIFT_CPPC_CAPABILITY_1_HIGHEST_PERF, 8),
line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130116):
https://review.coreboot.org/c/coreboot/+/58118/comment/fa77c562_505fa2c1
PS6, Line 16: [CPPC_NOMINAL_PERF] = CPPC_REG_MSR(MSR_CPPC_CAPABILITY_1, SHIFT_CPPC_CAPABILITY_1_NOMINAL_PERF, 8),
line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130116):
https://review.coreboot.org/c/coreboot/+/58118/comment/b8101c06_a5336f6c
PS6, Line 17: [CPPC_LOWEST_NONL_PERF] = CPPC_REG_MSR(MSR_CPPC_CAPABILITY_1, SHIFT_CPPC_CAPABILITY_1_LOW_NON_LIN_PERF, 8),
line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130116):
https://review.coreboot.org/c/coreboot/+/58118/comment/4e6a16c4_0fff24e9
PS6, Line 18: [CPPC_LOWEST_PERF] = CPPC_REG_MSR(MSR_CPPC_CAPABILITY_1, SHIFT_CPPC_CAPABILITY_1_LOWEST_PERF, 8),
line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130116):
https://review.coreboot.org/c/coreboot/+/58118/comment/f06e905f_8163660c
PS6, Line 20: [CPPC_DESIRED_PERF] = CPPC_REG_MSR(MSR_CPPC_REQUEST, SHIFT_CPPC_REQUEST_DES_PERF, 8),
line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130116):
https://review.coreboot.org/c/coreboot/+/58118/comment/c3b7622a_9ecba681
PS6, Line 21: [CPPC_MIN_PERF] = CPPC_REG_MSR(MSR_CPPC_REQUEST, SHIFT_CPPC_REQUEST_MIN_PERF, 8),
line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130116):
https://review.coreboot.org/c/coreboot/+/58118/comment/47f0c28f_f87032d0
PS6, Line 22: [CPPC_MAX_PERF] = CPPC_REG_MSR(MSR_CPPC_REQUEST, SHIFT_CPPC_REQUEST_MAX_PERF, 8),
line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130116):
https://review.coreboot.org/c/coreboot/+/58118/comment/a5f9b685_944e03b8
PS6, Line 26: [CPPC_REF_PERF_COUNTER] = CPPC_REG_MSR(MSR_MAX_PERFORMANCE_FREQUENCY_CLOCK_COUNT, 0, 64),
line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130116):
https://review.coreboot.org/c/coreboot/+/58118/comment/794cd797_2cacd18e
PS6, Line 27: [CPPC_DELIVERED_PERF_COUNTER] = CPPC_REG_MSR(MSR_ACTUAL_PERFORMANCE_FREQUENCY_CLOCK_COUNT, 0, 64),
line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130116):
https://review.coreboot.org/c/coreboot/+/58118/comment/883a4e31_cd2bbeba
PS6, Line 34: [CPPC_PERF_PREF] = CPPC_REG_MSR(MSR_CPPC_REQUEST, SHIFT_CPPC_REQUEST_ENERGY_PERF_PREF, 8),
line over 96 characters
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Hello Felix Singer, build bot (Jenkins), Raul Rangel, Furquan Shaikh, Paul Menzel, Angel Pons, Patrick Rudolph, Lance Zhao, Jason Glenesk, Nico Huber, Marshall Dawson, Tim Wawrzynczak, Tim Wawrzynczak, Felix Held,
I'd like you to reexamine a change. Please visit
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Change subject: acpigen,soc/amd/cezanne,intel/{common,skl}: rework CPPC table passing
......................................................................
acpigen,soc/amd/cezanne,intel/{common,skl}: rework CPPC table passing
Instead of passing around a magic struct with embedded version, use
pointers and pass the CPPC version directly to the ACPI generator.
Change-Id: I26c5e80c2a16a50ed73245c7c32d61b17e45c22a
Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de>
---
M src/acpi/acpigen.c
M src/cpu/intel/common/common.h
M src/cpu/intel/common/common_init.c
M src/include/acpi/acpi.h
M src/include/acpi/acpigen.h
M src/soc/amd/cezanne/cppc.c
M src/soc/amd/cezanne/include/soc/cppc.h
M src/soc/intel/common/block/acpi/acpi.c
M src/soc/intel/skylake/acpi.c
9 files changed, 99 insertions(+), 108 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/58118/6
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Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57951 )
Change subject: Revert "vboot_logic: Set VB2_CONTEXT_EC_TRUSTED in verstage_main"
......................................................................
Patch Set 2: Code-Review+1
(4 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/57951/comment/58ec7ea2_0e5f57f7
PS2, Line 11: intel
Intel
https://review.coreboot.org/c/coreboot/+/57951/comment/6d48b4f5_10621d5a
PS2, Line 11: intel
Intel
https://review.coreboot.org/c/coreboot/+/57951/comment/74d113e6_d1392d9f
PS2, Line 11: We need to add GPIO_EC_IN_RW into early_gpio_table for platforms using intel SoC
Please add a dot/period to the end of sentences.
Patchset:
PS2:
Three nits.
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Hello build bot (Jenkins), Cliff Huang, Tim Wawrzynczak, Sridhar Siricilla, Bernardo Perez Priego, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/58181
to look at the new patch set (#9).
Change subject: soc/intel/common/cse: Support RW update when stitching CSE binary
......................................................................
soc/intel/common/cse: Support RW update when stitching CSE binary
This change updates the STITCH_ME_BIN path to enable support for
including CSE RW update in CBFS. CSE_RW_FILE is set to either
CONFIG_SOC_INTEL_CSE_RW_FILE or CSE_BP2_BIN depending upon the
selection of STITCH_ME_BIN config.
BUG=b:189177580
Change-Id: I0478f6b2a3342ed29c7ca21aa8e26655c58265f4
Signed-off-by: Furquan Shaikh <furquan(a)google.com>
---
M src/soc/intel/common/block/cse/Kconfig
M src/soc/intel/common/block/cse/Makefile.inc
2 files changed, 10 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/58181/9
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Furquan Shaikh has uploaded a new patch set (#20) to the change originally created by Bernardo Perez Priego. ( https://review.coreboot.org/c/coreboot/+/57353 )
Change subject: soc/intel/common/cse: Add support for stitching CSE components
......................................................................
soc/intel/common/cse: Add support for stitching CSE components
This change adds support for allowing mainboards to stitch CSE
components during build time instead of adding a pre-built CSE
binary. Several Kconfig options are added to allow mainboard to
provide the file names for different CSE region components. This makes
use of the newly added cse_serger and cse_fpt tools to create
following partitions:
1. BP1 - RO
2. BP2 - RW
3. Layout
In addition to this, it accepts CSE data partition as an input using
Kconfig CSE_DATA_FILE. All these partitions are then assembled
together as per the following mainboard FMAP regions:
1. BP1(RO) : CSE_RO
2. BP2(RW) : CSE_RW
3. Layout : CSE_LAYOUT
4. Data : CSE_DATA
Finally, it generates the target $(OBJ_ME_BIN) which is used to put
together the binary in final coreboot.rom image.
Several helper functions are added to soc/intel/Makefile.inc to allow
SoCs to define which components use:
1. Decomposed files: Files decomposed from Intel release CSE binary in
FPT format.
2. Input files: Mainboard provided input files using corresponding
Kconfigs.
3. Dummy: Components that are required to have dummy entries in
BPDT header.
These helpers are added to soc/intel/Makefile.inc to ensure that the
functions are defined by the time the invocations are encountered in
SoC Makefile.inc.
BUG=b:189177580
Change-Id: I8359cd49ad256703285e55bc4319c6e9c9fccb67
Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com>
Signed-off-by: Furquan Shaikh <furquan(a)google.com>
---
A src/soc/intel/Makefile.inc
M src/soc/intel/common/block/cse/Kconfig
M src/soc/intel/common/block/cse/Makefile.inc
3 files changed, 170 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/57353/20
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Hello build bot (Jenkins), Cliff Huang, Tim Wawrzynczak, Sridhar Siricilla, Bernardo Perez Priego, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/58181
to look at the new patch set (#8).
Change subject: soc/intel/common/cse: Support RW update when stitching CSE binary
......................................................................
soc/intel/common/cse: Support RW update when stitching CSE binary
This change updates the STITCH_ME_BIN path to enable support for
including CSE RW update in CBFS. CSE_RW_FILE is set to either
CONFIG_SOC_INTEL_CSE_RW_FILE or CSE_BP2_BIN depending upon the
selection of STITCH_ME_BIN config.
BUG=b:189177580
Change-Id: I0478f6b2a3342ed29c7ca21aa8e26655c58265f4
Signed-off-by: Furquan Shaikh <furquan(a)google.com>
---
M src/soc/intel/common/block/cse/Kconfig
M src/soc/intel/common/block/cse/Makefile.inc
2 files changed, 41 insertions(+), 37 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/58181/8
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Change subject: soc/intel/common/cse: Add support for stitching CSE components
......................................................................
soc/intel/common/cse: Add support for stitching CSE components
This change adds support for allowing mainboards to stitch CSE
components during build time instead of adding a pre-built CSE
binary. Several Kconfig options are added to allow mainboard to
provide the file names for different CSE region components. This makes
use of the newly added cse_serger and cse_fpt tools to create
following partitions:
1. BP1 - RO
2. BP2 - RW
3. Layout
In addition to this, it accepts CSE data partition as an input using
Kconfig CSE_DATA_FILE. All these partitions are then assembled
together as per the following mainboard FMAP regions:
1. BP1(RO) : CSE_RO
2. BP2(RW) : CSE_RW
3. Layout : CSE_LAYOUT
4. Data : CSE_DATA
Finally, it generates the target $(OBJ_ME_BIN) which is used to put
together the binary in final coreboot.rom image.
Several helper functions are added to soc/intel/Makefile.inc to allow
SoCs to define which components use:
1. Decomposed files: Files decomposed from Intel release CSE binary in
FPT format.
2. Input files: Mainboard provided input files using corresponding
Kconfigs.
3. Dummy: Components that are required to have dummy entries in
BPDT header.
These helpers are added to soc/intel/Makefile.inc to ensure that the
functions are defined by the time the invocations are encountered in
SoC Makefile.inc.
BUG=b:189177580
Change-Id: I8359cd49ad256703285e55bc4319c6e9c9fccb67
Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com>
Signed-off-by: Furquan Shaikh <furquan(a)google.com>
---
A src/soc/intel/Makefile.inc
M src/soc/intel/common/block/cse/Kconfig
M src/soc/intel/common/block/cse/Makefile.inc
3 files changed, 170 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/57353/19
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Gerrit-Change-Id: I8359cd49ad256703285e55bc4319c6e9c9fccb67
Gerrit-Change-Number: 57353
Gerrit-PatchSet: 19
Gerrit-Owner: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com>
Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com>
Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com>
Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org>
Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com>
Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com>
Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com>
Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com>
Gerrit-Attention: Furquan Shaikh <furquan(a)google.com>
Gerrit-Attention: Selma Bensaid <selma.bensaid(a)intel.com>
Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com>
Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com>
Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org>
Gerrit-MessageType: newpatchset