coreboot-gerrit October 2021

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: mb/google/guybrush: Add GPIO EC in RW to early GPIO tables
by Yu-Ping Wu (Code Review) 09 Oct '21

09 Oct '21

Attention is currently required from: Hsuan Ting Chen, Hsuan-ting Chen. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58192 ) Change subject: mb/google/guybrush: Add GPIO EC in RW to early GPIO tables ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/58192 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia6dcb225bbca89f3a873aad75a7d67625cdd3742 Gerrit-Change-Number: 58192 Gerrit-PatchSet: 2 Gerrit-Owner: Hsuan-ting Chen <roccochen(a)google.com> Gerrit-Reviewer: Hsuan Ting Chen <roccochen(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hsuan Ting Chen <roccochen(a)chromium.org> Gerrit-Attention: Hsuan-ting Chen <roccochen(a)google.com> Gerrit-Comment-Date: Sat, 09 Oct 2021 03:27:01 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/dedede/var/sasukette: Generate SPD ID for supported memory ...
by Weimin Wu (Code Review) 09 Oct '21

09 Oct '21

Attention is currently required from: Zhi7 Li. Weimin Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58196 ) Change subject: mb/google/dedede/var/sasukette: Generate SPD ID for supported memory parts ...................................................................... Patch Set 2: Code-Review+1 (1 comment) Patchset: PS2: double-checked -- To view, visit https://review.coreboot.org/c/coreboot/+/58196 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I811f32defd50a940a09f238d38c962d2caf42855 Gerrit-Change-Number: 58196 Gerrit-PatchSet: 2 Gerrit-Owner: Zhi7 Li <lizhi7(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Echo Huang <huangrui(a)huaqin.corp-partner.google.com> Gerrit-Attention: Zhi7 Li <lizhi7(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Sat, 09 Oct 2021 01:03:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: libpayload: Add mock architecture
by Julius Werner (Code Review) 09 Oct '21

09 Oct '21

Attention is currently required from: Jakub Czapiga, Paul Menzel, Jan Dabros. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57708 ) Change subject: libpayload: Add mock architecture ...................................................................... Patch Set 10: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/57708 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie3a6e6f6cad2f8a2e48a8e546d3b79c577653080 Gerrit-Change-Number: 57708 Gerrit-PatchSet: 10 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Jan Dabros <jsd(a)semihalf.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jan Dabros <jsd(a)semihalf.com> Gerrit-Comment-Date: Sat, 09 Oct 2021 00:12:14 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: tests: Add lib/lzma-test test case
by Julius Werner (Code Review) 09 Oct '21

09 Oct '21

Attention is currently required from: Jakub Czapiga, Jan Dabros. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57555 ) Change subject: tests: Add lib/lzma-test test case ...................................................................... Patch Set 8: (3 comments) File tests/lib/lzma-test.c: https://review.coreboot.org/c/coreboot/+/57555/comment/5f1ef881_ba5dbd39 PS7, Line 65: goto error; > If setup function exits with non-zero exit code, the teardown function is not called by CMocka. I am calling it in the error section and passing correct pointer `(void **)&s)` before returning from setup function. Oh, you are... okay, sorry, didn't look at that closely enough. File tests/lib/lzma-test.c: https://review.coreboot.org/c/coreboot/+/57555/comment/23d4db1e_f69f89f3 PS8, Line 64: comp_file_suffix); Not sure why you moved these around now? You can't snprintf() into the pointer before you check it for NULL. https://review.coreboot.org/c/coreboot/+/57555/comment/86f7156b_71caba0f PS8, Line 167: */ No, sorry, this isn't what I meant. I meant documenting what the different files 1, 2, 3, 4 are, e.g. are they text files, binaries, etc., were they compressed with different versions of lzmautils... basically, why are we testing exactly these 4 and not more or less? Each test file should have a specific purpose for being there and a notable difference from the other test cases. -- To view, visit https://review.coreboot.org/c/coreboot/+/57555 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id75e0b41991382d4c391b031862106de58eacdf7 Gerrit-Change-Number: 57555 Gerrit-PatchSet: 8 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Jan Dabros <jsd(a)semihalf.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Jan Dabros <jsd(a)semihalf.com> Gerrit-Comment-Date: Sat, 09 Oct 2021 00:10:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jakub Czapiga <jacz(a)semihalf.com> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/{icl,tgl,jsl,ehl}: enable ACPI CPPC entries
by Lance Zhao (Code Review) 09 Oct '21

09 Oct '21

Attention is currently required from: Felix Singer, Matt Delco, Nico Huber, Furquan Shaikh, Paul Menzel, Tim Wawrzynczak, Ravindra, Subrata Banik, Michael Niewöhner, Lean Sheng Tan, Patrick Rudolph. Lance Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47543 ) Change subject: soc/intel/{icl,tgl,jsl,ehl}: enable ACPI CPPC entries ...................................................................... Patch Set 27: (1 comment) Patchset: PS27: Need rebase for verify build failed? -- To view, visit https://review.coreboot.org/c/coreboot/+/47543 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I910b4e17d4044f1bf1ecfa0643ac62fc7a8cb51b Gerrit-Change-Number: 47543 Gerrit-PatchSet: 27 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Reviewer: Matt Delco <delco(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Ravindra <ravindra(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Matt Delco <delco(a)chromium.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Ravindra <ravindra(a)intel.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 08 Oct 2021 23:40:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/qualcomm/sc7280: Enable compression of SHRM
by Paul Menzel (Code Review) 09 Oct '21

09 Oct '21

Attention is currently required from: Shelley Chen. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58191 ) Change subject: soc/qualcomm/sc7280: Enable compression of SHRM ...................................................................... Patch Set 3: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/58191/comment/f2c9862d_ce37c5c3 PS3, Line 15: Also, did some cleanup in this file based on comments in CB:49392. In the future, it would be great to have this in a separate commit. https://review.coreboot.org/c/coreboot/+/58191/comment/72fbfbd2_326c02f0 PS3, Line 19: TEST=Make sure we can still boot to kernel on herobrine What timing differences are there? -- To view, visit https://review.coreboot.org/c/coreboot/+/58191 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaad8a8a02abe40bd01766d94ef0b61aac7671936 Gerrit-Change-Number: 58191 Gerrit-PatchSet: 3 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-CC: Sudheer Amrabadi <samrabad(a)codeaurora.org> Gerrit-CC: mturney mturney <mturney(a)codeaurora.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Comment-Date: Fri, 08 Oct 2021 23:35:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: arch/x86,cpu/x86,lib/thread: Remove usage of cpu_info from lib/thread
by Julius Werner (Code Review) 09 Oct '21

09 Oct '21

Attention is currently required from: Raul Rangel, Karthik Ramasubramanian. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58199 ) Change subject: arch/x86,cpu/x86,lib/thread: Remove usage of cpu_info from lib/thread ...................................................................... Patch Set 1: (2 comments) Patchset: PS1: Thanks! File src/lib/thread.c: https://review.coreboot.org/c/coreboot/+/58199/comment/f7e16610_3c1664b9 PS1, Line 249: !boot_cpu() > Would you expect it to die in set_current_thread? […] Yeah, I think an assert(boot_cpu()) in set_current_thread would make sense (and then you shouldn't need this here -- this being called from a non-boot CPU is a programming error). -- To view, visit https://review.coreboot.org/c/coreboot/+/58199 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iea4622d52c36d529e100b7ea55f32c334acfdf3e Gerrit-Change-Number: 58199 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Fri, 08 Oct 2021 23:15:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/cezanne,soc/intel/common: rework CPPC table generation
by Lance Zhao (Code Review) 09 Oct '21

09 Oct '21

Attention is currently required from: Felix Singer, Raul Rangel, Furquan Shaikh, Angel Pons, Subrata Banik, Michael Niewöhner, Kyösti Mälkki, Patrick Rudolph, Jason Glenesk, Matt Delco, Marshall Dawson, Tim Wawrzynczak, Felix Held. Lance Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57888 ) Change subject: soc/amd/cezanne,soc/intel/common: rework CPPC table generation ...................................................................... Patch Set 12: (16 comments) Patchset: PS12: Line over 96? File src/cpu/intel/common/common_init.c: https://review.coreboot.org/c/coreboot/+/57888/comment/e3dd6178_254232ae PS12, Line 108: config->regs[CPPC_HIGHEST_PERF] = ACPI_REG_MSR(IA32_HWP_CAPABILITIES, 0, 8); > line over 96 characters Please fix. https://review.coreboot.org/c/coreboot/+/57888/comment/3b39223c_afe7e1fd PS12, Line 110: config->regs[CPPC_LOWEST_NONL_PERF] = ACPI_REG_MSR(IA32_HWP_CAPABILITIES, 16, 8); > line over 96 characters Please fix. https://review.coreboot.org/c/coreboot/+/57888/comment/33eb0c55_7adc9de8 PS12, Line 111: config->regs[CPPC_LOWEST_PERF] = ACPI_REG_MSR(IA32_HWP_CAPABILITIES, 24, 8); > line over 96 characters Please fix. https://review.coreboot.org/c/coreboot/+/57888/comment/95a4bb65_1a02f612 PS12, Line 112: config->regs[CPPC_GUARANTEED_PERF] = ACPI_REG_MSR(IA32_HWP_CAPABILITIES, 8, 8); > line over 96 characters Please fix. https://review.coreboot.org/c/coreboot/+/57888/comment/f0009844_ea61131c PS12, Line 135: config->regs[CPPC_AUTO_ACTIVITY_WINDOW] = ACPI_REG_MSR(IA32_HWP_REQUEST, 32, 10); > line over 96 characters Please fix. File src/soc/amd/cezanne/cppc.c: https://review.coreboot.org/c/coreboot/+/57888/comment/7f6819ef_b5d78c36 PS12, Line 18: config->regs[CPPC_HIGHEST_PERF] = ACPI_REG_MSR(MSR_CPPC_CAPABILITY_1, SHIFT_CPPC_CAPABILITY_1_HIGHEST_PERF, 8); > line over 96 characters Please fix. https://review.coreboot.org/c/coreboot/+/57888/comment/3b6fa0a6_7cc17044 PS12, Line 19: config->regs[CPPC_NOMINAL_PERF] = ACPI_REG_MSR(MSR_CPPC_CAPABILITY_1, SHIFT_CPPC_CAPABILITY_1_NOMINAL_PERF, 8); > line over 96 characters Please fix. https://review.coreboot.org/c/coreboot/+/57888/comment/d5d41f31_f0d35e01 PS12, Line 20: config->regs[CPPC_LOWEST_NONL_PERF] = ACPI_REG_MSR(MSR_CPPC_CAPABILITY_1, SHIFT_CPPC_CAPABILITY_1_LOW_NON_LIN_PERF, 8); > line over 96 characters Please fix. https://review.coreboot.org/c/coreboot/+/57888/comment/866322bf_62d31aec PS12, Line 21: config->regs[CPPC_LOWEST_PERF] = ACPI_REG_MSR(MSR_CPPC_CAPABILITY_1, SHIFT_CPPC_CAPABILITY_1_LOWEST_PERF, 8); > line over 96 characters Please fix. https://review.coreboot.org/c/coreboot/+/57888/comment/6c702356_155fdd5f PS12, Line 23: config->regs[CPPC_DESIRED_PERF] = ACPI_REG_MSR(MSR_CPPC_REQUEST, SHIFT_CPPC_REQUEST_DES_PERF, 8); > line over 96 characters Please fix. https://review.coreboot.org/c/coreboot/+/57888/comment/1ad61c5b_2fc41007 PS12, Line 24: config->regs[CPPC_MIN_PERF] = ACPI_REG_MSR(MSR_CPPC_REQUEST, SHIFT_CPPC_REQUEST_MIN_PERF, 8); > line over 96 characters Please fix. https://review.coreboot.org/c/coreboot/+/57888/comment/ce9ce022_fd9fe634 PS12, Line 25: config->regs[CPPC_MAX_PERF] = ACPI_REG_MSR(MSR_CPPC_REQUEST, SHIFT_CPPC_REQUEST_MAX_PERF, 8); > line over 96 characters Please fix. https://review.coreboot.org/c/coreboot/+/57888/comment/ceab9752_f7ce03bb PS12, Line 29: config->regs[CPPC_REF_PERF_COUNTER] = ACPI_REG_MSR(MSR_MAX_PERFORMANCE_FREQUENCY_CLOCK_COUNT, 0, 64); > line over 96 characters Please fix. https://review.coreboot.org/c/coreboot/+/57888/comment/4412e84c_f25b40bb PS12, Line 30: config->regs[CPPC_DELIVERED_PERF_COUNTER] = ACPI_REG_MSR(MSR_ACTUAL_PERFORMANCE_FREQUENCY_CLOCK_COUNT, 0, 64); > line over 96 characters Please fix. https://review.coreboot.org/c/coreboot/+/57888/comment/3658a2bc_b5ffbd51 PS12, Line 39: config->regs[CPPC_PERF_PREF] = ACPI_REG_MSR(MSR_CPPC_REQUEST, SHIFT_CPPC_REQUEST_ENERGY_PERF_PREF, 8); > line over 96 characters Please fix. -- To view, visit https://review.coreboot.org/c/coreboot/+/57888 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I844d191b1134b98e409240ede71e2751e51e2159 Gerrit-Change-Number: 57888 Gerrit-PatchSet: 12 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Matt Delco <delco(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt Delco <delco(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 08 Oct 2021 23:12:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: cpu/x86/cpu_info.S: Remove ebx save/restore
by Raul Rangel (Code Review) 09 Oct '21

09 Oct '21

Raul Rangel has uploaded a new patch set (#3). ( https://review.coreboot.org/c/coreboot/+/58205 ) Change subject: cpu/x86/cpu_info.S: Remove ebx save/restore ...................................................................... cpu/x86/cpu_info.S: Remove ebx save/restore The push/pop of %ebx was only added because smm_stub saves the canary value in it. Now that we no longer use cpu_info in smm, we no longer need to save the register. BUG=b:179699789 TEST=Boot guybrush to the OS Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I554dbe016db8b1c61246c8ffc7fa252b2542ba92 --- M src/cpu/x86/cpu_info.S.inc 1 file changed, 1 insertion(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/58205/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/58205 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I554dbe016db8b1c61246c8ffc7fa252b2542ba92 Gerrit-Change-Number: 58205 Gerrit-PatchSet: 3 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: cpu/x86/smm/smm_stub: Remove cpu_info
by Raul Rangel (Code Review) 09 Oct '21

09 Oct '21

Raul Rangel has uploaded a new patch set (#3). ( https://review.coreboot.org/c/coreboot/+/58204 ) Change subject: cpu/x86/smm/smm_stub: Remove cpu_info ...................................................................... cpu/x86/smm/smm_stub: Remove cpu_info Now that cpu_info() is no longer used by COOP_MULTITASKING, we no longer need to setup cpu_info in SMM. When using CPU_INFO_V2, if something does manage to call cpu_info() while executing in SMM mode, the %gs segment is disabled, so it will generate an exception. BUG=b:179699789 TEST=Boot guybrush to OS with threads enabled Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: Id64f32cc63082880a92dab6deb473431b2238cd0 --- M src/cpu/x86/smm/smm_stub.S 1 file changed, 1 insertion(+), 31 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/58204/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/58204 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id64f32cc63082880a92dab6deb473431b2238cd0 Gerrit-Change-Number: 58204 Gerrit-PatchSet: 3 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: newpatchset

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coreboot-gerrit October 2021